1//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
11// are used to describe target instructions and their operands.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/MC/MCInstrDesc.h"
16#include "llvm/MC/MCInst.h"
17#include "llvm/MC/MCRegisterInfo.h"
18#include "llvm/MC/MCSubtargetInfo.h"
19
20using namespace llvm;
21
22bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
23                                    std::string &Info) const {
24  if (ComplexDeprecationInfo)
25    return ComplexDeprecationInfo(MI, STI, Info);
26  if (DeprecatedFeature != -1 && STI.getFeatureBits()[DeprecatedFeature]) {
27    // FIXME: it would be nice to include the subtarget feature here.
28    Info = "deprecated";
29    return true;
30  }
31  return false;
32}
33bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
34                                       const MCRegisterInfo &RI) const {
35  if (isBranch() || isCall() || isReturn() || isIndirectBranch())
36    return true;
37  unsigned PC = RI.getProgramCounter();
38  if (PC == 0)
39    return false;
40  if (hasDefOfPhysReg(MI, PC, RI))
41    return true;
42  // A variadic instruction may define PC in the variable operand list.
43  // There's currently no indication of which entries in a variable
44  // list are defs and which are uses. While that's the case, this function
45  // needs to assume they're defs in order to be conservatively correct.
46  for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
47    if (MI.getOperand(i).isReg() &&
48        RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
49      return true;
50  }
51  return false;
52}
53
54bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
55                                          const MCRegisterInfo *MRI) const {
56  if (const MCPhysReg *ImpDefs = ImplicitDefs)
57    for (; *ImpDefs; ++ImpDefs)
58      if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
59        return true;
60  return false;
61}
62
63bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
64                                  const MCRegisterInfo &RI) const {
65  for (int i = 0, e = NumDefs; i != e; ++i)
66    if (MI.getOperand(i).isReg() &&
67        RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
68      return true;
69  return hasImplicitDefOfPhysReg(Reg, &RI);
70}
71