1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8/// \file 9//===----------------------------------------------------------------------===// 10 11#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14#include "llvm/Support/TargetRegistry.h" 15#include "llvm/Target/TargetMachine.h" 16 17namespace llvm { 18 19class AMDGPUInstrPrinter; 20class AMDGPUSubtarget; 21class AMDGPUTargetMachine; 22class FunctionPass; 23struct MachineSchedContext; 24class MCAsmInfo; 25class raw_ostream; 26class ScheduleDAGInstrs; 27class Target; 28class TargetMachine; 29 30// R600 Passes 31FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 32FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 33FunctionPass *createR600EmitClauseMarkers(); 34FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 35FunctionPass *createR600Packetizer(TargetMachine &tm); 36FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 37FunctionPass *createAMDGPUCFGStructurizerPass(); 38 39// SI Passes 40FunctionPass *createSITypeRewriter(); 41FunctionPass *createSIAnnotateControlFlowPass(); 42FunctionPass *createSIFoldOperandsPass(); 43FunctionPass *createSILowerI1CopiesPass(); 44FunctionPass *createSIShrinkInstructionsPass(); 45FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 46FunctionPass *createSIWholeQuadModePass(); 47FunctionPass *createSILowerControlFlowPass(); 48FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 49FunctionPass *createSIFixSGPRCopiesPass(); 50FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 51FunctionPass *createSIDebuggerInsertNopsPass(); 52FunctionPass *createSIInsertWaitsPass(); 53FunctionPass *createAMDGPUCodeGenPreparePass(const TargetMachine *TM = nullptr); 54 55ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C); 56 57ModulePass *createAMDGPUAnnotateKernelFeaturesPass(); 58void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 59extern char &AMDGPUAnnotateKernelFeaturesID; 60 61void initializeSIFoldOperandsPass(PassRegistry &); 62extern char &SIFoldOperandsID; 63 64void initializeSIShrinkInstructionsPass(PassRegistry&); 65extern char &SIShrinkInstructionsID; 66 67void initializeSIFixSGPRCopiesPass(PassRegistry &); 68extern char &SIFixSGPRCopiesID; 69 70void initializeSILowerI1CopiesPass(PassRegistry &); 71extern char &SILowerI1CopiesID; 72 73void initializeSILoadStoreOptimizerPass(PassRegistry &); 74extern char &SILoadStoreOptimizerID; 75 76void initializeSIWholeQuadModePass(PassRegistry &); 77extern char &SIWholeQuadModeID; 78 79void initializeSILowerControlFlowPass(PassRegistry &); 80extern char &SILowerControlFlowPassID; 81 82 83// Passes common to R600 and SI 84FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr); 85void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 86extern char &AMDGPUPromoteAllocaID; 87 88FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST); 89Pass *createAMDGPUStructurizeCFGPass(); 90FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 91ModulePass *createAMDGPUAlwaysInlinePass(); 92ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 93FunctionPass *createAMDGPUAnnotateUniformValues(); 94 95void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 96extern char &SIFixControlFlowLiveIntervalsID; 97 98void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 99extern char &AMDGPUAnnotateUniformValuesPassID; 100 101void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 102extern char &AMDGPUCodeGenPrepareID; 103 104void initializeSIAnnotateControlFlowPass(PassRegistry&); 105extern char &SIAnnotateControlFlowPassID; 106 107void initializeSIDebuggerInsertNopsPass(PassRegistry&); 108extern char &SIDebuggerInsertNopsID; 109 110void initializeSIInsertWaitsPass(PassRegistry&); 111extern char &SIInsertWaitsID; 112 113extern Target TheAMDGPUTarget; 114extern Target TheGCNTarget; 115 116namespace AMDGPU { 117enum TargetIndex { 118 TI_CONSTDATA_START, 119 TI_SCRATCH_RSRC_DWORD0, 120 TI_SCRATCH_RSRC_DWORD1, 121 TI_SCRATCH_RSRC_DWORD2, 122 TI_SCRATCH_RSRC_DWORD3 123}; 124} 125 126} // End namespace llvm 127 128/// OpenCL uses address spaces to differentiate between 129/// various memory regions on the hardware. On the CPU 130/// all of the address spaces point to the same memory, 131/// however on the GPU, each address space points to 132/// a separate piece of memory that is unique from other 133/// memory locations. 134namespace AMDGPUAS { 135enum AddressSpaces : unsigned { 136 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 137 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 138 CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2) 139 LOCAL_ADDRESS = 3, ///< Address space for local memory. 140 FLAT_ADDRESS = 4, ///< Address space for flat memory. 141 REGION_ADDRESS = 5, ///< Address space for region memory. 142 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 143 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 144 145 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 146 // order to be able to dynamically index a constant buffer, for example: 147 // 148 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 149 150 CONSTANT_BUFFER_0 = 8, 151 CONSTANT_BUFFER_1 = 9, 152 CONSTANT_BUFFER_2 = 10, 153 CONSTANT_BUFFER_3 = 11, 154 CONSTANT_BUFFER_4 = 12, 155 CONSTANT_BUFFER_5 = 13, 156 CONSTANT_BUFFER_6 = 14, 157 CONSTANT_BUFFER_7 = 15, 158 CONSTANT_BUFFER_8 = 16, 159 CONSTANT_BUFFER_9 = 17, 160 CONSTANT_BUFFER_10 = 18, 161 CONSTANT_BUFFER_11 = 19, 162 CONSTANT_BUFFER_12 = 20, 163 CONSTANT_BUFFER_13 = 21, 164 CONSTANT_BUFFER_14 = 22, 165 CONSTANT_BUFFER_15 = 23, 166 167 // Some places use this if the address space can't be determined. 168 UNKNOWN_ADDRESS_SPACE = ~0u 169}; 170 171} // namespace AMDGPUAS 172 173#endif 174