1//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11///
12/// This file contains declaration for AMDGPU ISA disassembler
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18
19#include "llvm/ADT/ArrayRef.h"
20#include "llvm/MC/MCDisassembler/MCDisassembler.h"
21
22namespace llvm {
23
24  class MCContext;
25  class MCInst;
26  class MCOperand;
27  class MCSubtargetInfo;
28  class Twine;
29
30  class AMDGPUDisassembler : public MCDisassembler {
31  private:
32    mutable ArrayRef<uint8_t> Bytes;
33
34  public:
35    AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
36      MCDisassembler(STI, Ctx) {}
37
38    ~AMDGPUDisassembler() {}
39
40    DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
41                                ArrayRef<uint8_t> Bytes, uint64_t Address,
42                                raw_ostream &WS, raw_ostream &CS) const override;
43
44    const char* getRegClassName(unsigned RegClassID) const;
45
46    MCOperand createRegOperand(unsigned int RegId) const;
47    MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
48    MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
49
50    MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
51
52    DecodeStatus tryDecodeInst(const uint8_t* Table,
53                               MCInst &MI,
54                               uint64_t Inst,
55                               uint64_t Address) const;
56
57    MCOperand decodeOperand_VGPR_32(unsigned Val) const;
58    MCOperand decodeOperand_VS_32(unsigned Val) const;
59    MCOperand decodeOperand_VS_64(unsigned Val) const;
60
61    MCOperand decodeOperand_VReg_64(unsigned Val) const;
62    MCOperand decodeOperand_VReg_96(unsigned Val) const;
63    MCOperand decodeOperand_VReg_128(unsigned Val) const;
64
65    MCOperand decodeOperand_SReg_32(unsigned Val) const;
66    MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
67    MCOperand decodeOperand_SReg_64(unsigned Val) const;
68    MCOperand decodeOperand_SReg_128(unsigned Val) const;
69    MCOperand decodeOperand_SReg_256(unsigned Val) const;
70    MCOperand decodeOperand_SReg_512(unsigned Val) const;
71
72    enum OpWidthTy {
73      OPW32,
74      OPW64,
75      OPW128,
76      OPW_LAST_,
77      OPW_FIRST_ = OPW32
78    };
79    unsigned getVgprClassId(const OpWidthTy Width) const;
80    unsigned getSgprClassId(const OpWidthTy Width) const;
81    unsigned getTtmpClassId(const OpWidthTy Width) const;
82
83    static MCOperand decodeIntImmed(unsigned Imm);
84    static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
85    MCOperand decodeLiteralConstant() const;
86
87    MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
88    MCOperand decodeSpecialReg32(unsigned Val) const;
89    MCOperand decodeSpecialReg64(unsigned Val) const;
90  };
91} // namespace llvm
92
93#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
94