ARMCallingConv.td revision 76f920d316dc6a9e5e77c8e36f9312d1708e376b 
1//===- ARMCallingConv.td - Calling Conventions for ARM -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This describes the calling conventions for ARM architecture.
10//===----------------------------------------------------------------------===//
11
12/// CCIfSubtarget - Match if the current subtarget has a feature F.
13class CCIfSubtarget<string F, CCAction A>:
14  CCIf<!strconcat("State.getTarget().getSubtarget<ARMSubtarget>().", F), A>;
15
16/// CCIfAlign - Match of the original alignment of the arg
17class CCIfAlign<string Align, CCAction A>:
18  CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
19
20//===----------------------------------------------------------------------===//
21// ARM APCS Calling Convention
22//===----------------------------------------------------------------------===//
23def CC_ARM_APCS : CallingConv<[
24
25  CCIfType<[i8, i16], CCPromoteToType<i32>>,
26
27  // Handle all vector types as either f64 or v2f64.
28  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
29  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
30
31  // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
32  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
33
34  CCIfType<[f32], CCBitConvertToType<i32>>,
35  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
36
37  CCIfType<[i32], CCAssignToStack<4, 4>>,
38  CCIfType<[f64], CCAssignToStack<8, 4>>,
39  CCIfType<[v2f64], CCAssignToStack<16, 4>>
40]>;
41
42def RetCC_ARM_APCS : CallingConv<[
43  CCIfType<[f32], CCBitConvertToType<i32>>,
44
45  // Handle all vector types as either f64 or v2f64.
46  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
47  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
48
49  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
50
51  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
52  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
53]>;
54
55//===----------------------------------------------------------------------===//
56// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
57//===----------------------------------------------------------------------===//
58def FastCC_ARM_APCS : CallingConv<[
59  // Handle all vector types as either f64 or v2f64.
60  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
61  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
62
63  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
64  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
65  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
66                                 S9, S10, S11, S12, S13, S14, S15]>>,
67  CCDelegateTo<CC_ARM_APCS>
68]>;
69
70def RetFastCC_ARM_APCS : CallingConv<[
71  // Handle all vector types as either f64 or v2f64.
72  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
73  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
74
75  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
76  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
77  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
78                                 S9, S10, S11, S12, S13, S14, S15]>>,
79  CCDelegateTo<RetCC_ARM_APCS>
80]>;
81
82
83//===----------------------------------------------------------------------===//
84// ARM AAPCS (EABI) Calling Convention, common parts
85//===----------------------------------------------------------------------===//
86
87def CC_ARM_AAPCS_Common : CallingConv<[
88
89  CCIfType<[i8, i16], CCPromoteToType<i32>>,
90
91  // i64/f64 is passed in even pairs of GPRs
92  // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
93  // (and the same is true for f64 if VFP is not enabled)
94  CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
95  CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
96                       "ArgFlags.getOrigAlign() != 8",
97                       CCAssignToReg<[R0, R1, R2, R3]>>>,
98
99  CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, R3>>>,
100  CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
101  CCIfType<[f64], CCAssignToStack<8, 8>>,
102  CCIfType<[v2f64], CCAssignToStack<16, 8>>
103]>;
104
105def RetCC_ARM_AAPCS_Common : CallingConv<[
106  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
107  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
108]>;
109
110//===----------------------------------------------------------------------===//
111// ARM AAPCS (EABI) Calling Convention
112//===----------------------------------------------------------------------===//
113
114def CC_ARM_AAPCS : CallingConv<[
115  // Handle all vector types as either f64 or v2f64.
116  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
117  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
118
119  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
120  CCIfType<[f32], CCBitConvertToType<i32>>,
121  CCDelegateTo<CC_ARM_AAPCS_Common>
122]>;
123
124def RetCC_ARM_AAPCS : CallingConv<[
125  // Handle all vector types as either f64 or v2f64.
126  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
127  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
128
129  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
130  CCIfType<[f32], CCBitConvertToType<i32>>,
131  CCDelegateTo<RetCC_ARM_AAPCS_Common>
132]>;
133
134//===----------------------------------------------------------------------===//
135// ARM AAPCS-VFP (EABI) Calling Convention
136// Also used for FastCC (when VFP2 or later is available)
137//===----------------------------------------------------------------------===//
138
139def CC_ARM_AAPCS_VFP : CallingConv<[
140  // Handle all vector types as either f64 or v2f64.
141  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
142  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
143
144  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
145  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
146  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
147                                 S9, S10, S11, S12, S13, S14, S15]>>,
148  CCDelegateTo<CC_ARM_AAPCS_Common>
149]>;
150
151def RetCC_ARM_AAPCS_VFP : CallingConv<[
152  // Handle all vector types as either f64 or v2f64.
153  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
154  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
155
156  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
157  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
158  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
159                                 S9, S10, S11, S12, S13, S14, S15]>>,
160  CCDelegateTo<RetCC_ARM_AAPCS_Common>
161]>;
162