1//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMSubtarget.h"
15#include "ARMFrameLowering.h"
16#include "ARMISelLowering.h"
17#include "ARMInstrInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSelectionDAGInfo.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "Thumb1FrameLowering.h"
23#include "Thumb1InstrInfo.h"
24#include "Thumb2InstrInfo.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/IR/Attributes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/GlobalValue.h"
29#include "llvm/MC/MCAsmInfo.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/Target/TargetRegisterInfo.h"
34
35using namespace llvm;
36
37#define DEBUG_TYPE "arm-subtarget"
38
39#define GET_SUBTARGETINFO_TARGET_DESC
40#define GET_SUBTARGETINFO_CTOR
41#include "ARMGenSubtargetInfo.inc"
42
43static cl::opt<bool>
44UseFusedMulOps("arm-use-mulops",
45               cl::init(true), cl::Hidden);
46
47enum ITMode {
48  DefaultIT,
49  RestrictedIT,
50  NoRestrictedIT
51};
52
53static cl::opt<ITMode>
54IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
55   cl::ZeroOrMore,
56   cl::values(clEnumValN(DefaultIT, "arm-default-it",
57                         "Generate IT block based on arch"),
58              clEnumValN(RestrictedIT, "arm-restrict-it",
59                         "Disallow deprecated IT based on ARMv8"),
60              clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
61                         "Allow IT blocks based on ARMv7"),
62              clEnumValEnd));
63
64/// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65/// currently supported (for testing only).
66static cl::opt<bool>
67ForceFastISel("arm-force-fast-isel",
68               cl::init(false), cl::Hidden);
69
70/// initializeSubtargetDependencies - Initializes using a CPU and feature string
71/// so that we can use initializer lists for subtarget initialization.
72ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
73                                                            StringRef FS) {
74  initializeEnvironment();
75  initSubtargetFeatures(CPU, FS);
76  return *this;
77}
78
79ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
80                                                        StringRef FS) {
81  ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
82  if (STI.isThumb1Only())
83    return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
84
85  return new ARMFrameLowering(STI);
86}
87
88ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
89                           const std::string &FS,
90                           const ARMBaseTargetMachine &TM, bool IsLittle)
91    : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
92      CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
93      TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
94      // At this point initializeSubtargetDependencies has been called so
95      // we can query directly.
96      InstrInfo(isThumb1Only()
97                    ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
98                    : !isThumb()
99                          ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
100                          : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
101      TLInfo(TM, *this) {}
102
103void ARMSubtarget::initializeEnvironment() {
104  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
105  // directly from it, but we can try to make sure they're consistent when both
106  // available.
107  UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
108  assert((!TM.getMCAsmInfo() ||
109          (TM.getMCAsmInfo()->getExceptionHandlingType() ==
110           ExceptionHandling::SjLj) == UseSjLjEH) &&
111         "inconsistent sjlj choice between CodeGen and MC");
112}
113
114void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
115  if (CPUString.empty()) {
116    CPUString = "generic";
117
118    if (isTargetDarwin()) {
119      StringRef ArchName = TargetTriple.getArchName();
120      if (ArchName.endswith("v7s"))
121        // Default to the Swift CPU when targeting armv7s/thumbv7s.
122        CPUString = "swift";
123      else if (ArchName.endswith("v7k"))
124        // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
125        // ARMv7k does not use SjLj exception handling.
126        CPUString = "cortex-a7";
127    }
128  }
129
130  // Insert the architecture feature derived from the target triple into the
131  // feature string. This is important for setting features that are implied
132  // based on the architecture version.
133  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
134  if (!FS.empty()) {
135    if (!ArchFS.empty())
136      ArchFS = (Twine(ArchFS) + "," + FS).str();
137    else
138      ArchFS = FS;
139  }
140  ParseSubtargetFeatures(CPUString, ArchFS);
141
142  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
143  // Assert this for now to make the change obvious.
144  assert(hasV6T2Ops() || !hasThumb2());
145
146  // Keep a pointer to static instruction cost data for the specified CPU.
147  SchedModel = getSchedModelForCPU(CPUString);
148
149  // Initialize scheduling itinerary for the specified CPU.
150  InstrItins = getInstrItineraryForCPU(CPUString);
151
152  // FIXME: this is invalid for WindowsCE
153  if (isTargetWindows())
154    NoARM = true;
155
156  if (isAAPCS_ABI())
157    stackAlignment = 8;
158  if (isTargetNaCl() || isAAPCS16_ABI())
159    stackAlignment = 16;
160
161  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
162  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
163  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
164  // support in the assembler and linker to be used. This would need to be
165  // fixed to fully support tail calls in Thumb1.
166  //
167  // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
168  // LR.  This means if we need to reload LR, it takes an extra instructions,
169  // which outweighs the value of the tail call; but here we don't know yet
170  // whether LR is going to be used.  Probably the right approach is to
171  // generate the tail call here and turn it back into CALL/RET in
172  // emitEpilogue if LR is used.
173
174  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
175  // but we need to make sure there are enough registers; the only valid
176  // registers are the 4 used for parameters.  We don't currently do this
177  // case.
178
179  SupportsTailCall = !isThumb() || hasV8MBaselineOps();
180
181  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
182    SupportsTailCall = false;
183
184  switch (IT) {
185  case DefaultIT:
186    RestrictIT = hasV8Ops();
187    break;
188  case RestrictedIT:
189    RestrictIT = true;
190    break;
191  case NoRestrictedIT:
192    RestrictIT = false;
193    break;
194  }
195
196  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
197  const FeatureBitset &Bits = getFeatureBits();
198  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
199      (Options.UnsafeFPMath || isTargetDarwin()))
200    UseNEONForSinglePrecisionFP = true;
201
202  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
203  switch (ARMProcFamily) {
204  case Others:
205  case CortexA5:
206    break;
207  case CortexA7:
208    LdStMultipleTiming = DoubleIssue;
209    break;
210  case CortexA8:
211    LdStMultipleTiming = DoubleIssue;
212    break;
213  case CortexA9:
214    LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
215    PreISelOperandLatencyAdjustment = 1;
216    break;
217  case CortexA12:
218    break;
219  case CortexA15:
220    MaxInterleaveFactor = 2;
221    PreISelOperandLatencyAdjustment = 1;
222    PartialUpdateClearance = 12;
223    break;
224  case CortexA17:
225  case CortexA32:
226  case CortexA35:
227  case CortexA53:
228  case CortexA57:
229  case CortexA72:
230  case CortexA73:
231  case CortexR4:
232  case CortexR4F:
233  case CortexR5:
234  case CortexR7:
235  case CortexM3:
236  case ExynosM1:
237    break;
238  case Krait:
239    PreISelOperandLatencyAdjustment = 1;
240    break;
241  case Swift:
242    MaxInterleaveFactor = 2;
243    LdStMultipleTiming = SingleIssuePlusExtras;
244    PreISelOperandLatencyAdjustment = 1;
245    PartialUpdateClearance = 12;
246    break;
247  }
248}
249
250bool ARMSubtarget::isAPCS_ABI() const {
251  assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
252  return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
253}
254bool ARMSubtarget::isAAPCS_ABI() const {
255  assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
256  return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
257         TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
258}
259bool ARMSubtarget::isAAPCS16_ABI() const {
260  assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
261  return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
262}
263
264bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
265  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
266    return true;
267
268  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
269  // the section that is being relocated. This means we have to use o load even
270  // for GVs that are known to be local to the dso.
271  if (isTargetDarwin() && TM.isPositionIndependent() &&
272      (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
273    return true;
274
275  return false;
276}
277
278unsigned ARMSubtarget::getMispredictionPenalty() const {
279  return SchedModel.MispredictPenalty;
280}
281
282bool ARMSubtarget::hasSinCos() const {
283  return isTargetWatchOS() ||
284    (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
285}
286
287bool ARMSubtarget::enableMachineScheduler() const {
288  // Enable the MachineScheduler before register allocation for out-of-order
289  // architectures where we do not use the PostRA scheduler anymore (for now
290  // restricted to swift).
291  return getSchedModel().isOutOfOrder() && isSwift();
292}
293
294// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
295bool ARMSubtarget::enablePostRAScheduler() const {
296  // No need for PostRA scheduling on out of order CPUs (for now restricted to
297  // swift).
298  if (getSchedModel().isOutOfOrder() && isSwift())
299    return false;
300  return (!isThumb() || hasThumb2());
301}
302
303bool ARMSubtarget::enableAtomicExpand() const {
304  return hasAnyDataBarrier() && (!isThumb() || hasV8MBaselineOps());
305}
306
307bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
308  // For general targets, the prologue can grow when VFPs are allocated with
309  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
310  // format which it's more important to get right.
311  return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
312}
313
314bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
315  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
316  // immediates as it is inherently position independent, and may be out of
317  // range otherwise.
318  return !NoMovt && hasV8MBaselineOps() &&
319         (isTargetWindows() || !MF.getFunction()->optForMinSize());
320}
321
322bool ARMSubtarget::useFastISel() const {
323  // Enable fast-isel for any target, for testing only.
324  if (ForceFastISel)
325    return true;
326
327  // Limit fast-isel to the targets that are or have been tested.
328  if (!hasV6Ops())
329    return false;
330
331  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
332  return TM.Options.EnableFastISel &&
333         ((isTargetMachO() && !isThumb1Only()) ||
334          (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
335}
336