1//===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LanaiTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "LanaiISelLowering.h"
15
16#include "Lanai.h"
17#include "LanaiMachineFunctionInfo.h"
18#include "LanaiSubtarget.h"
19#include "LanaiTargetMachine.h"
20#include "LanaiTargetObjectFile.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAGISel.h"
27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28#include "llvm/CodeGen/ValueTypes.h"
29#include "llvm/IR/CallingConv.h"
30#include "llvm/IR/DerivedTypes.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/GlobalAlias.h"
33#include "llvm/IR/GlobalVariable.h"
34#include "llvm/IR/Intrinsics.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39
40#define DEBUG_TYPE "lanai-lower"
41
42using namespace llvm;
43
44// Limit on number of instructions the lowered multiplication may have before a
45// call to the library function should be generated instead. The threshold is
46// currently set to 14 as this was the smallest threshold that resulted in all
47// constant multiplications being lowered. A threshold of 5 covered all cases
48// except for one multiplication which required 14. mulsi3 requires 16
49// instructions (including the prologue and epilogue but excluding instructions
50// at call site). Until we can inline mulsi3, generating at most 14 instructions
51// will be faster than invoking mulsi3.
52static cl::opt<int> LanaiLowerConstantMulThreshold(
53    "lanai-constant-mul-threshold", cl::Hidden,
54    cl::desc("Maximum number of instruction to generate when lowering constant "
55             "multiplication instead of calling library function [default=14]"),
56    cl::init(14));
57
58LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
59                                         const LanaiSubtarget &STI)
60    : TargetLowering(TM) {
61  // Set up the register classes.
62  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
63
64  // Compute derived properties from the register classes
65  TRI = STI.getRegisterInfo();
66  computeRegisterProperties(TRI);
67
68  setStackPointerRegisterToSaveRestore(Lanai::SP);
69
70  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
71  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
72  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
73  setOperationAction(ISD::SETCC, MVT::i32, Custom);
74  setOperationAction(ISD::SETCCE, MVT::i32, Custom);
75  setOperationAction(ISD::SELECT, MVT::i32, Expand);
76  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
77
78  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
79  setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
80  setOperationAction(ISD::JumpTable, MVT::i32, Custom);
81  setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
82
83  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
84  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
85  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
86
87  setOperationAction(ISD::VASTART, MVT::Other, Custom);
88  setOperationAction(ISD::VAARG, MVT::Other, Expand);
89  setOperationAction(ISD::VACOPY, MVT::Other, Expand);
90  setOperationAction(ISD::VAEND, MVT::Other, Expand);
91
92  setOperationAction(ISD::SDIV, MVT::i32, Expand);
93  setOperationAction(ISD::UDIV, MVT::i32, Expand);
94  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
95  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
96  setOperationAction(ISD::SREM, MVT::i32, Expand);
97  setOperationAction(ISD::UREM, MVT::i32, Expand);
98
99  setOperationAction(ISD::MUL, MVT::i32, Custom);
100  setOperationAction(ISD::MULHU, MVT::i32, Expand);
101  setOperationAction(ISD::MULHS, MVT::i32, Expand);
102  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
103  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
104
105  setOperationAction(ISD::ROTR, MVT::i32, Expand);
106  setOperationAction(ISD::ROTL, MVT::i32, Expand);
107  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
108  setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
109  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
110
111  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
112  setOperationAction(ISD::CTPOP, MVT::i32, Legal);
113  setOperationAction(ISD::CTLZ, MVT::i32, Legal);
114  setOperationAction(ISD::CTTZ, MVT::i32, Legal);
115
116  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
117  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
118  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
119
120  // Extended load operations for i1 types must be promoted
121  for (MVT VT : MVT::integer_valuetypes()) {
122    setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
123    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
124    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
125  }
126
127  setTargetDAGCombine(ISD::ADD);
128  setTargetDAGCombine(ISD::SUB);
129  setTargetDAGCombine(ISD::AND);
130  setTargetDAGCombine(ISD::OR);
131  setTargetDAGCombine(ISD::XOR);
132
133  // Function alignments (log2)
134  setMinFunctionAlignment(2);
135  setPrefFunctionAlignment(2);
136
137  setJumpIsExpensive(true);
138
139  // TODO: Setting the minimum jump table entries needed before a
140  // switch is transformed to a jump table to 100 to avoid creating jump tables
141  // as this was causing bad performance compared to a large group of if
142  // statements. Re-evaluate this on new benchmarks.
143  setMinimumJumpTableEntries(100);
144
145  // Use fast calling convention for library functions.
146  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
147    setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
148  }
149
150  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
151  MaxStoresPerMemsetOptSize = 8;
152  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
153  MaxStoresPerMemcpyOptSize = 8;
154  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
155  MaxStoresPerMemmoveOptSize = 8;
156
157  // Booleans always contain 0 or 1.
158  setBooleanContents(ZeroOrOneBooleanContent);
159}
160
161SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
162                                            SelectionDAG &DAG) const {
163  switch (Op.getOpcode()) {
164  case ISD::MUL:
165    return LowerMUL(Op, DAG);
166  case ISD::BR_CC:
167    return LowerBR_CC(Op, DAG);
168  case ISD::ConstantPool:
169    return LowerConstantPool(Op, DAG);
170  case ISD::GlobalAddress:
171    return LowerGlobalAddress(Op, DAG);
172  case ISD::BlockAddress:
173    return LowerBlockAddress(Op, DAG);
174  case ISD::JumpTable:
175    return LowerJumpTable(Op, DAG);
176  case ISD::SELECT_CC:
177    return LowerSELECT_CC(Op, DAG);
178  case ISD::SETCC:
179    return LowerSETCC(Op, DAG);
180  case ISD::SETCCE:
181    return LowerSETCCE(Op, DAG);
182  case ISD::SRL_PARTS:
183    return LowerSRL_PARTS(Op, DAG);
184  case ISD::VASTART:
185    return LowerVASTART(Op, DAG);
186  case ISD::DYNAMIC_STACKALLOC:
187    return LowerDYNAMIC_STACKALLOC(Op, DAG);
188  case ISD::RETURNADDR:
189    return LowerRETURNADDR(Op, DAG);
190  case ISD::FRAMEADDR:
191    return LowerFRAMEADDR(Op, DAG);
192  default:
193    llvm_unreachable("unimplemented operand");
194  }
195}
196//===----------------------------------------------------------------------===//
197//                       Lanai Inline Assembly Support
198//===----------------------------------------------------------------------===//
199
200unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT VT,
201                                                SelectionDAG &DAG) const {
202  // Only unallocatable registers should be matched here.
203  unsigned Reg = StringSwitch<unsigned>(RegName)
204                     .Case("pc", Lanai::PC)
205                     .Case("sp", Lanai::SP)
206                     .Case("fp", Lanai::FP)
207                     .Case("rr1", Lanai::RR1)
208                     .Case("r10", Lanai::R10)
209                     .Case("rr2", Lanai::RR2)
210                     .Case("r11", Lanai::R11)
211                     .Case("rca", Lanai::RCA)
212                     .Default(0);
213
214  if (Reg)
215    return Reg;
216  report_fatal_error("Invalid register name global variable");
217}
218
219std::pair<unsigned, const TargetRegisterClass *>
220LanaiTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
221                                                  StringRef Constraint,
222                                                  MVT VT) const {
223  if (Constraint.size() == 1)
224    // GCC Constraint Letters
225    switch (Constraint[0]) {
226    case 'r': // GENERAL_REGS
227      return std::make_pair(0U, &Lanai::GPRRegClass);
228    default:
229      break;
230    }
231
232  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
233}
234
235// Examine constraint type and operand type and determine a weight value.
236// This object must already have been set up with the operand type
237// and the current alternative constraint selected.
238TargetLowering::ConstraintWeight
239LanaiTargetLowering::getSingleConstraintMatchWeight(
240    AsmOperandInfo &Info, const char *Constraint) const {
241  ConstraintWeight Weight = CW_Invalid;
242  Value *CallOperandVal = Info.CallOperandVal;
243  // If we don't have a value, we can't do a match,
244  // but allow it at the lowest weight.
245  if (CallOperandVal == NULL)
246    return CW_Default;
247  // Look at the constraint type.
248  switch (*Constraint) {
249  case 'I': // signed 16 bit immediate
250  case 'J': // integer zero
251  case 'K': // unsigned 16 bit immediate
252  case 'L': // immediate in the range 0 to 31
253  case 'M': // signed 32 bit immediate where lower 16 bits are 0
254  case 'N': // signed 26 bit immediate
255  case 'O': // integer zero
256    if (isa<ConstantInt>(CallOperandVal))
257      Weight = CW_Constant;
258    break;
259  default:
260    Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
261    break;
262  }
263  return Weight;
264}
265
266// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
267// vector.  If it is invalid, don't add anything to Ops.
268void LanaiTargetLowering::LowerAsmOperandForConstraint(
269    SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
270    SelectionDAG &DAG) const {
271  SDValue Result(0, 0);
272
273  // Only support length 1 constraints for now.
274  if (Constraint.length() > 1)
275    return;
276
277  char ConstraintLetter = Constraint[0];
278  switch (ConstraintLetter) {
279  case 'I': // Signed 16 bit constant
280    // If this fails, the parent routine will give an error
281    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
282      if (isInt<16>(C->getSExtValue())) {
283        Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
284                                       Op.getValueType());
285        break;
286      }
287    }
288    return;
289  case 'J': // integer zero
290  case 'O':
291    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
292      if (C->getZExtValue() == 0) {
293        Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
294        break;
295      }
296    }
297    return;
298  case 'K': // unsigned 16 bit immediate
299    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
300      if (isUInt<16>(C->getZExtValue())) {
301        Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
302                                       Op.getValueType());
303        break;
304      }
305    }
306    return;
307  case 'L': // immediate in the range 0 to 31
308    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
309      if (C->getZExtValue() <= 31) {
310        Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
311                                       Op.getValueType());
312        break;
313      }
314    }
315    return;
316  case 'M': // signed 32 bit immediate where lower 16 bits are 0
317    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
318      int64_t Val = C->getSExtValue();
319      if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
320        Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
321        break;
322      }
323    }
324    return;
325  case 'N': // signed 26 bit immediate
326    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
327      int64_t Val = C->getSExtValue();
328      if ((Val >= -33554432) && (Val <= 33554431)) {
329        Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
330        break;
331      }
332    }
333    return;
334  default:
335    break; // This will fall through to the generic implementation
336  }
337
338  if (Result.getNode()) {
339    Ops.push_back(Result);
340    return;
341  }
342
343  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
344}
345
346//===----------------------------------------------------------------------===//
347//                      Calling Convention Implementation
348//===----------------------------------------------------------------------===//
349
350#include "LanaiGenCallingConv.inc"
351
352static unsigned NumFixedArgs;
353static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
354                              CCValAssign::LocInfo LocInfo,
355                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
356  // Handle fixed arguments with default CC.
357  // Note: Both the default and fast CC handle VarArg the same and hence the
358  // calling convention of the function is not considered here.
359  if (ValNo < NumFixedArgs) {
360    return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
361  }
362
363  // Promote i8/i16 args to i32
364  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
365    LocVT = MVT::i32;
366    if (ArgFlags.isSExt())
367      LocInfo = CCValAssign::SExt;
368    else if (ArgFlags.isZExt())
369      LocInfo = CCValAssign::ZExt;
370    else
371      LocInfo = CCValAssign::AExt;
372  }
373
374  // VarArgs get passed on stack
375  unsigned Offset = State.AllocateStack(4, 4);
376  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
377  return false;
378}
379
380SDValue LanaiTargetLowering::LowerFormalArguments(
381    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
382    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
383    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
384  switch (CallConv) {
385  case CallingConv::C:
386  case CallingConv::Fast:
387    return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
388  default:
389    llvm_unreachable("Unsupported calling convention");
390  }
391}
392
393SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
394                                       SmallVectorImpl<SDValue> &InVals) const {
395  SelectionDAG &DAG = CLI.DAG;
396  SDLoc &DL = CLI.DL;
397  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
398  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
399  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
400  SDValue Chain = CLI.Chain;
401  SDValue Callee = CLI.Callee;
402  bool &IsTailCall = CLI.IsTailCall;
403  CallingConv::ID CallConv = CLI.CallConv;
404  bool IsVarArg = CLI.IsVarArg;
405
406  // Lanai target does not yet support tail call optimization.
407  IsTailCall = false;
408
409  switch (CallConv) {
410  case CallingConv::Fast:
411  case CallingConv::C:
412    return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
413                          OutVals, Ins, DL, DAG, InVals);
414  default:
415    llvm_unreachable("Unsupported calling convention");
416  }
417}
418
419// LowerCCCArguments - transform physical registers into virtual registers and
420// generate load operations for arguments places on the stack.
421SDValue LanaiTargetLowering::LowerCCCArguments(
422    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
423    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
424    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
425  MachineFunction &MF = DAG.getMachineFunction();
426  MachineFrameInfo *MFI = MF.getFrameInfo();
427  MachineRegisterInfo &RegInfo = MF.getRegInfo();
428  LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
429
430  // Assign locations to all of the incoming arguments.
431  SmallVector<CCValAssign, 16> ArgLocs;
432  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
433                 *DAG.getContext());
434  if (CallConv == CallingConv::Fast) {
435    CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
436  } else {
437    CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
438  }
439
440  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
441    CCValAssign &VA = ArgLocs[i];
442    if (VA.isRegLoc()) {
443      // Arguments passed in registers
444      EVT RegVT = VA.getLocVT();
445      switch (RegVT.getSimpleVT().SimpleTy) {
446      case MVT::i32: {
447        unsigned VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
448        RegInfo.addLiveIn(VA.getLocReg(), VReg);
449        SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
450
451        // If this is an 8/16-bit value, it is really passed promoted to 32
452        // bits. Insert an assert[sz]ext to capture this, then truncate to the
453        // right size.
454        if (VA.getLocInfo() == CCValAssign::SExt)
455          ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
456                                 DAG.getValueType(VA.getValVT()));
457        else if (VA.getLocInfo() == CCValAssign::ZExt)
458          ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
459                                 DAG.getValueType(VA.getValVT()));
460
461        if (VA.getLocInfo() != CCValAssign::Full)
462          ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
463
464        InVals.push_back(ArgValue);
465        break;
466      }
467      default:
468        DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
469                     << RegVT.getEVTString() << "\n");
470        llvm_unreachable("unhandled argument type");
471      }
472    } else {
473      // Sanity check
474      assert(VA.isMemLoc());
475      // Load the argument to a virtual register
476      unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
477      // Check that the argument fits in stack slot
478      if (ObjSize > 4) {
479        errs() << "LowerFormalArguments Unhandled argument type: "
480               << EVT(VA.getLocVT()).getEVTString() << "\n";
481      }
482      // Create the frame index object for this incoming parameter...
483      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
484
485      // Create the SelectionDAG nodes corresponding to a load
486      // from this parameter
487      SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
488      InVals.push_back(DAG.getLoad(
489          VA.getLocVT(), DL, Chain, FIN,
490          MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
491          false, false, false, 0));
492    }
493  }
494
495  // The Lanai ABI for returning structs by value requires that we copy
496  // the sret argument into rv for the return. Save the argument into
497  // a virtual register so that we can access it from the return points.
498  if (MF.getFunction()->hasStructRetAttr()) {
499    unsigned Reg = LanaiMFI->getSRetReturnReg();
500    if (!Reg) {
501      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
502      LanaiMFI->setSRetReturnReg(Reg);
503    }
504    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
505    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
506  }
507
508  if (IsVarArg) {
509    // Record the frame index of the first variable argument
510    // which is a value necessary to VASTART.
511    int FI = MFI->CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
512    LanaiMFI->setVarArgsFrameIndex(FI);
513  }
514
515  return Chain;
516}
517
518SDValue
519LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
520                                 bool IsVarArg,
521                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
522                                 const SmallVectorImpl<SDValue> &OutVals,
523                                 const SDLoc &DL, SelectionDAG &DAG) const {
524  // CCValAssign - represent the assignment of the return value to a location
525  SmallVector<CCValAssign, 16> RVLocs;
526
527  // CCState - Info about the registers and stack slot.
528  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
529                 *DAG.getContext());
530
531  // Analize return values.
532  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
533
534  SDValue Flag;
535  SmallVector<SDValue, 4> RetOps(1, Chain);
536
537  // Copy the result values into the output registers.
538  for (unsigned i = 0; i != RVLocs.size(); ++i) {
539    CCValAssign &VA = RVLocs[i];
540    assert(VA.isRegLoc() && "Can only return in registers!");
541
542    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
543
544    // Guarantee that all emitted copies are stuck together with flags.
545    Flag = Chain.getValue(1);
546    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
547  }
548
549  // The Lanai ABI for returning structs by value requires that we copy
550  // the sret argument into rv for the return. We saved the argument into
551  // a virtual register in the entry block, so now we copy the value out
552  // and into rv.
553  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
554    MachineFunction &MF = DAG.getMachineFunction();
555    LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
556    unsigned Reg = LanaiMFI->getSRetReturnReg();
557    assert(Reg &&
558           "SRetReturnReg should have been set in LowerFormalArguments().");
559    SDValue Val =
560        DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
561
562    Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
563    Flag = Chain.getValue(1);
564    RetOps.push_back(
565        DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
566  }
567
568  RetOps[0] = Chain; // Update chain
569
570  unsigned Opc = LanaiISD::RET_FLAG;
571  if (Flag.getNode())
572    RetOps.push_back(Flag);
573
574  // Return Void
575  return DAG.getNode(Opc, DL, MVT::Other,
576                     ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
577}
578
579// LowerCCCCallTo - functions arguments are copied from virtual regs to
580// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
581SDValue LanaiTargetLowering::LowerCCCCallTo(
582    SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
583    bool IsTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
584    const SmallVectorImpl<SDValue> &OutVals,
585    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
586    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
587  // Analyze operands of the call, assigning locations to each operand.
588  SmallVector<CCValAssign, 16> ArgLocs;
589  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
590                 *DAG.getContext());
591  GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
592  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
593
594  NumFixedArgs = 0;
595  if (IsVarArg && G) {
596    const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
597    if (CalleeFn)
598      NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
599  }
600  if (NumFixedArgs)
601    CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
602  else {
603    if (CallConv == CallingConv::Fast)
604      CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
605    else
606      CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
607  }
608
609  // Get a count of how many bytes are to be pushed on the stack.
610  unsigned NumBytes = CCInfo.getNextStackOffset();
611
612  // Create local copies for byval args.
613  SmallVector<SDValue, 8> ByValArgs;
614  for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
615    ISD::ArgFlagsTy Flags = Outs[I].Flags;
616    if (!Flags.isByVal())
617      continue;
618
619    SDValue Arg = OutVals[I];
620    unsigned Size = Flags.getByValSize();
621    unsigned Align = Flags.getByValAlign();
622
623    int FI = MFI->CreateStackObject(Size, Align, false);
624    SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
625    SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
626
627    Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
628                          /*IsVolatile=*/false,
629                          /*AlwaysInline=*/false,
630                          /*IsTailCall=*/false, MachinePointerInfo(),
631                          MachinePointerInfo());
632    ByValArgs.push_back(FIPtr);
633  }
634
635  Chain = DAG.getCALLSEQ_START(
636      Chain,
637      DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
638      DL);
639
640  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
641  SmallVector<SDValue, 12> MemOpChains;
642  SDValue StackPtr;
643
644  // Walk the register/memloc assignments, inserting copies/loads.
645  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
646    CCValAssign &VA = ArgLocs[I];
647    SDValue Arg = OutVals[I];
648    ISD::ArgFlagsTy Flags = Outs[I].Flags;
649
650    // Promote the value if needed.
651    switch (VA.getLocInfo()) {
652    case CCValAssign::Full:
653      break;
654    case CCValAssign::SExt:
655      Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
656      break;
657    case CCValAssign::ZExt:
658      Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
659      break;
660    case CCValAssign::AExt:
661      Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
662      break;
663    default:
664      llvm_unreachable("Unknown loc info!");
665    }
666
667    // Use local copy if it is a byval arg.
668    if (Flags.isByVal())
669      Arg = ByValArgs[J++];
670
671    // Arguments that can be passed on register must be kept at RegsToPass
672    // vector
673    if (VA.isRegLoc()) {
674      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
675    } else {
676      assert(VA.isMemLoc());
677
678      if (StackPtr.getNode() == 0)
679        StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
680                                      getPointerTy(DAG.getDataLayout()));
681
682      SDValue PtrOff =
683          DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
684                      DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
685
686      MemOpChains.push_back(DAG.getStore(
687          Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, false, 0));
688    }
689  }
690
691  // Transform all store nodes into one single node because all store nodes are
692  // independent of each other.
693  if (!MemOpChains.empty())
694    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
695                        ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
696
697  SDValue InFlag;
698
699  // Build a sequence of copy-to-reg nodes chained together with token chain and
700  // flag operands which copy the outgoing args into registers.  The InFlag in
701  // necessary since all emitted instructions must be stuck together.
702  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
703    Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
704                             RegsToPass[I].second, InFlag);
705    InFlag = Chain.getValue(1);
706  }
707
708  // If the callee is a GlobalAddress node (quite common, every direct call is)
709  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
710  // Likewise ExternalSymbol -> TargetExternalSymbol.
711  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
712  if (G) {
713    Callee = DAG.getTargetGlobalAddress(
714        G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
715  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
716    Callee = DAG.getTargetExternalSymbol(
717        E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
718  }
719
720  // Returns a chain & a flag for retval copy to use.
721  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
722  SmallVector<SDValue, 8> Ops;
723  Ops.push_back(Chain);
724  Ops.push_back(Callee);
725
726  // Add a register mask operand representing the call-preserved registers.
727  // TODO: Should return-twice functions be handled?
728  const uint32_t *Mask =
729      TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
730  assert(Mask && "Missing call preserved mask for calling convention");
731  Ops.push_back(DAG.getRegisterMask(Mask));
732
733  // Add argument registers to the end of the list so that they are
734  // known live into the call.
735  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
736    Ops.push_back(DAG.getRegister(RegsToPass[I].first,
737                                  RegsToPass[I].second.getValueType()));
738
739  if (InFlag.getNode())
740    Ops.push_back(InFlag);
741
742  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
743                      ArrayRef<SDValue>(&Ops[0], Ops.size()));
744  InFlag = Chain.getValue(1);
745
746  // Create the CALLSEQ_END node.
747  Chain = DAG.getCALLSEQ_END(
748      Chain,
749      DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
750      DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
751      DL);
752  InFlag = Chain.getValue(1);
753
754  // Handle result values, copying them out of physregs into vregs that we
755  // return.
756  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
757                         InVals);
758}
759
760// LowerCallResult - Lower the result values of a call into the
761// appropriate copies out of appropriate physical registers.
762SDValue LanaiTargetLowering::LowerCallResult(
763    SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
764    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
765    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
766  // Assign locations to each value returned by this call.
767  SmallVector<CCValAssign, 16> RVLocs;
768  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
769                 *DAG.getContext());
770
771  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
772
773  // Copy all of the result registers out of their specified physreg.
774  for (unsigned I = 0; I != RVLocs.size(); ++I) {
775    Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
776                               RVLocs[I].getValVT(), InFlag)
777                .getValue(1);
778    InFlag = Chain.getValue(2);
779    InVals.push_back(Chain.getValue(0));
780  }
781
782  return Chain;
783}
784
785//===----------------------------------------------------------------------===//
786//                      Custom Lowerings
787//===----------------------------------------------------------------------===//
788
789static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL,
790                                        SDValue &LHS, SDValue &RHS,
791                                        SelectionDAG &DAG) {
792  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
793
794  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
795  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
796  // and Lanai only supports integer comparisons, so only provide definitions
797  // for them.
798  switch (SetCCOpcode) {
799  case ISD::SETEQ:
800    return LPCC::ICC_EQ;
801  case ISD::SETGT:
802    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
803      if (RHSC->getZExtValue() == 0xFFFFFFFF) {
804        // X > -1 -> X >= 0 -> is_plus(X)
805        RHS = DAG.getConstant(0, DL, RHS.getValueType());
806        return LPCC::ICC_PL;
807      }
808    return LPCC::ICC_GT;
809  case ISD::SETUGT:
810    return LPCC::ICC_UGT;
811  case ISD::SETLT:
812    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
813      if (RHSC->getZExtValue() == 0)
814        // X < 0 -> is_minus(X)
815        return LPCC::ICC_MI;
816    return LPCC::ICC_LT;
817  case ISD::SETULT:
818    return LPCC::ICC_ULT;
819  case ISD::SETLE:
820    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
821      if (RHSC->getZExtValue() == 0xFFFFFFFF) {
822        // X <= -1 -> X < 0 -> is_minus(X)
823        RHS = DAG.getConstant(0, DL, RHS.getValueType());
824        return LPCC::ICC_MI;
825      }
826    return LPCC::ICC_LE;
827  case ISD::SETULE:
828    return LPCC::ICC_ULE;
829  case ISD::SETGE:
830    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
831      if (RHSC->getZExtValue() == 0)
832        // X >= 0 -> is_plus(X)
833        return LPCC::ICC_PL;
834    return LPCC::ICC_GE;
835  case ISD::SETUGE:
836    return LPCC::ICC_UGE;
837  case ISD::SETNE:
838    return LPCC::ICC_NE;
839  case ISD::SETONE:
840  case ISD::SETUNE:
841  case ISD::SETOGE:
842  case ISD::SETOLE:
843  case ISD::SETOLT:
844  case ISD::SETOGT:
845  case ISD::SETOEQ:
846  case ISD::SETUEQ:
847  case ISD::SETO:
848  case ISD::SETUO:
849    llvm_unreachable("Unsupported comparison.");
850  default:
851    llvm_unreachable("Unknown integer condition code!");
852  }
853}
854
855SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
856  SDValue Chain = Op.getOperand(0);
857  SDValue Cond = Op.getOperand(1);
858  SDValue LHS = Op.getOperand(2);
859  SDValue RHS = Op.getOperand(3);
860  SDValue Dest = Op.getOperand(4);
861  SDLoc DL(Op);
862
863  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
864  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
865  SDValue Flag =
866      DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
867
868  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
869                     TargetCC, Flag);
870}
871
872SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
873  EVT VT = Op->getValueType(0);
874  if (VT != MVT::i32)
875    return SDValue();
876
877  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
878  if (!C)
879    return SDValue();
880
881  int64_t MulAmt = C->getSExtValue();
882  int32_t HighestOne = -1;
883  uint32_t NonzeroEntries = 0;
884  int SignedDigit[32] = {0};
885
886  // Convert to non-adjacent form (NAF) signed-digit representation.
887  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
888  // minimal Hamming weight representation of a number (on average 1/3 of the
889  // digits will be non-zero vs 1/2 for regular binary representation). And as
890  // the non-zero digits will be the only digits contributing to the instruction
891  // count, this is desirable. The next loop converts it to NAF (following the
892  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
893  // choosing the non-zero coefficients such that the resulting quotient is
894  // divisible by 2 which will cause the next coefficient to be zero.
895  int64_t E = std::abs(MulAmt);
896  int S = (MulAmt < 0 ? -1 : 1);
897  int I = 0;
898  while (E > 0) {
899    int ZI = 0;
900    if (E % 2 == 1) {
901      ZI = 2 - (E % 4);
902      if (ZI != 0)
903        ++NonzeroEntries;
904    }
905    SignedDigit[I] = S * ZI;
906    if (SignedDigit[I] == 1)
907      HighestOne = I;
908    E = (E - ZI) / 2;
909    ++I;
910  }
911
912  // Compute number of instructions required. Due to differences in lowering
913  // between the different processors this count is not exact.
914  // Start by assuming a shift and a add/sub for every non-zero entry (hence
915  // every non-zero entry requires 1 shift and 1 add/sub except for the first
916  // entry).
917  int32_t InstrRequired = 2 * NonzeroEntries - 1;
918  // Correct possible over-adding due to shift by 0 (which is not emitted).
919  if (std::abs(MulAmt) % 2 == 1)
920    --InstrRequired;
921  // Return if the form generated would exceed the instruction threshold.
922  if (InstrRequired > LanaiLowerConstantMulThreshold)
923    return SDValue();
924
925  SDValue Res;
926  SDLoc DL(Op);
927  SDValue V = Op->getOperand(0);
928
929  // Initialize the running sum. Set the running sum to the maximal shifted
930  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
931  // term NAF).
932  if (HighestOne == -1)
933    Res = DAG.getConstant(0, DL, MVT::i32);
934  else {
935    Res = DAG.getNode(ISD::SHL, DL, VT, V,
936                      DAG.getConstant(HighestOne, DL, MVT::i32));
937    SignedDigit[HighestOne] = 0;
938  }
939
940  // Assemble multiplication from shift, add, sub using NAF form and running
941  // sum.
942  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
943       ++I) {
944    if (SignedDigit[I] == 0)
945      continue;
946
947    // Shifted multiplicand (v<<i).
948    SDValue Op =
949        DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
950    if (SignedDigit[I] == 1)
951      Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
952    else if (SignedDigit[I] == -1)
953      Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
954  }
955  return Res;
956}
957
958SDValue LanaiTargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
959  SDValue LHS = Op.getOperand(0);
960  SDValue RHS = Op.getOperand(1);
961  SDValue Carry = Op.getOperand(2);
962  SDValue Cond = Op.getOperand(3);
963  SDLoc DL(Op);
964
965  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
966  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
967  SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
968  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
969}
970
971SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
972  SDValue LHS = Op.getOperand(0);
973  SDValue RHS = Op.getOperand(1);
974  SDValue Cond = Op.getOperand(2);
975  SDLoc DL(Op);
976
977  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
978  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
979  SDValue Flag =
980      DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
981
982  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
983}
984
985SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
986                                            SelectionDAG &DAG) const {
987  SDValue LHS = Op.getOperand(0);
988  SDValue RHS = Op.getOperand(1);
989  SDValue TrueV = Op.getOperand(2);
990  SDValue FalseV = Op.getOperand(3);
991  SDValue Cond = Op.getOperand(4);
992  SDLoc DL(Op);
993
994  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
995  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
996  SDValue Flag =
997      DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
998
999  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1000  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1001                     Flag);
1002}
1003
1004SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1005  MachineFunction &MF = DAG.getMachineFunction();
1006  LanaiMachineFunctionInfo *FuncInfo = MF.getInfo<LanaiMachineFunctionInfo>();
1007
1008  SDLoc DL(Op);
1009  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1010                                 getPointerTy(DAG.getDataLayout()));
1011
1012  // vastart just stores the address of the VarArgsFrameIndex slot into the
1013  // memory location argument.
1014  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1015  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1016                      MachinePointerInfo(SV), false, false, 0);
1017}
1018
1019SDValue LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1020                                                     SelectionDAG &DAG) const {
1021  SDValue Chain = Op.getOperand(0);
1022  SDValue Size = Op.getOperand(1);
1023  SDLoc DL(Op);
1024
1025  unsigned SPReg = getStackPointerRegisterToSaveRestore();
1026
1027  // Get a reference to the stack pointer.
1028  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1029
1030  // Subtract the dynamic size from the actual stack size to
1031  // obtain the new stack size.
1032  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1033
1034  // For Lanai, the outgoing memory arguments area should be on top of the
1035  // alloca area on the stack i.e., the outgoing memory arguments should be
1036  // at a lower address than the alloca area. Move the alloca area down the
1037  // stack by adding back the space reserved for outgoing arguments to SP
1038  // here.
1039  //
1040  // We do not know what the size of the outgoing args is at this point.
1041  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1042  // stack pointer. We replace this instruction with on that has the correct,
1043  // known offset in emitPrologue().
1044  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1045
1046  // The Sub result contains the new stack start address, so it
1047  // must be placed in the stack pointer register.
1048  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1049
1050  SDValue Ops[2] = {ArgAdjust, CopyChain};
1051  return DAG.getMergeValues(Ops, DL);
1052}
1053
1054SDValue LanaiTargetLowering::LowerRETURNADDR(SDValue Op,
1055                                             SelectionDAG &DAG) const {
1056  MachineFunction &MF = DAG.getMachineFunction();
1057  MachineFrameInfo *MFI = MF.getFrameInfo();
1058  MFI->setReturnAddressIsTaken(true);
1059
1060  EVT VT = Op.getValueType();
1061  SDLoc DL(Op);
1062  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1063  if (Depth) {
1064    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1065    const unsigned Offset = -4;
1066    SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1067                              DAG.getIntPtrConstant(Offset, DL));
1068    return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1069                       false, false, false, 0);
1070  }
1071
1072  // Return the link register, which contains the return address.
1073  // Mark it an implicit live-in.
1074  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1075  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1076}
1077
1078SDValue LanaiTargetLowering::LowerFRAMEADDR(SDValue Op,
1079                                            SelectionDAG &DAG) const {
1080  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1081  MFI->setFrameAddressIsTaken(true);
1082
1083  EVT VT = Op.getValueType();
1084  SDLoc DL(Op);
1085  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1086  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1087  while (Depth--) {
1088    const unsigned Offset = -8;
1089    SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1090                              DAG.getIntPtrConstant(Offset, DL));
1091    FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr,
1092                            MachinePointerInfo(), false, false, false, 0);
1093  }
1094  return FrameAddr;
1095}
1096
1097const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1098  switch (Opcode) {
1099  case LanaiISD::ADJDYNALLOC:
1100    return "LanaiISD::ADJDYNALLOC";
1101  case LanaiISD::RET_FLAG:
1102    return "LanaiISD::RET_FLAG";
1103  case LanaiISD::CALL:
1104    return "LanaiISD::CALL";
1105  case LanaiISD::SELECT_CC:
1106    return "LanaiISD::SELECT_CC";
1107  case LanaiISD::SETCC:
1108    return "LanaiISD::SETCC";
1109  case LanaiISD::SUBBF:
1110    return "LanaiISD::SUBBF";
1111  case LanaiISD::SET_FLAG:
1112    return "LanaiISD::SET_FLAG";
1113  case LanaiISD::BR_CC:
1114    return "LanaiISD::BR_CC";
1115  case LanaiISD::Wrapper:
1116    return "LanaiISD::Wrapper";
1117  case LanaiISD::HI:
1118    return "LanaiISD::HI";
1119  case LanaiISD::LO:
1120    return "LanaiISD::LO";
1121  case LanaiISD::SMALL:
1122    return "LanaiISD::SMALL";
1123  default:
1124    return NULL;
1125  }
1126}
1127
1128SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op,
1129                                               SelectionDAG &DAG) const {
1130  SDLoc DL(Op);
1131  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1132  const Constant *C = N->getConstVal();
1133  const LanaiTargetObjectFile *TLOF =
1134      static_cast<const LanaiTargetObjectFile *>(
1135          getTargetMachine().getObjFileLowering());
1136
1137  // If the code model is small or constant will be placed in the small section,
1138  // then assume address will fit in 21-bits.
1139  if (getTargetMachine().getCodeModel() == CodeModel::Small ||
1140      TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1141    SDValue Small = DAG.getTargetConstantPool(
1142        C, MVT::i32, N->getAlignment(), N->getOffset(), LanaiII::MO_NO_FLAG);
1143    return DAG.getNode(ISD::OR, DL, MVT::i32,
1144                       DAG.getRegister(Lanai::R0, MVT::i32),
1145                       DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1146  } else {
1147    uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1148    uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1149
1150    SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1151                                           N->getOffset(), OpFlagHi);
1152    SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1153                                           N->getOffset(), OpFlagLo);
1154    Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1155    Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1156    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1157    return Result;
1158  }
1159}
1160
1161SDValue LanaiTargetLowering::LowerGlobalAddress(SDValue Op,
1162                                                SelectionDAG &DAG) const {
1163  SDLoc DL(Op);
1164  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1165  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1166
1167  const LanaiTargetObjectFile *TLOF =
1168      static_cast<const LanaiTargetObjectFile *>(
1169          getTargetMachine().getObjFileLowering());
1170
1171  // If the code model is small or global variable will be placed in the small
1172  // section, then assume address will fit in 21-bits.
1173  if (getTargetMachine().getCodeModel() == CodeModel::Small ||
1174      TLOF->isGlobalInSmallSection(GV, getTargetMachine())) {
1175    SDValue Small = DAG.getTargetGlobalAddress(
1176        GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1177    return DAG.getNode(ISD::OR, DL, MVT::i32,
1178                       DAG.getRegister(Lanai::R0, MVT::i32),
1179                       DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1180  } else {
1181    uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1182    uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1183
1184    // Create the TargetGlobalAddress node, folding in the constant offset.
1185    SDValue Hi = DAG.getTargetGlobalAddress(
1186        GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1187    SDValue Lo = DAG.getTargetGlobalAddress(
1188        GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1189    Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1190    Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1191    return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1192  }
1193}
1194
1195SDValue LanaiTargetLowering::LowerBlockAddress(SDValue Op,
1196                                               SelectionDAG &DAG) const {
1197  SDLoc DL(Op);
1198  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1199
1200  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1201  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1202
1203  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1204  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1205  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1206  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1207  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1208  return Result;
1209}
1210
1211SDValue LanaiTargetLowering::LowerJumpTable(SDValue Op,
1212                                            SelectionDAG &DAG) const {
1213  SDLoc DL(Op);
1214  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1215
1216  // If the code model is small assume address will fit in 21-bits.
1217  if (getTargetMachine().getCodeModel() == CodeModel::Small) {
1218    SDValue Small = DAG.getTargetJumpTable(
1219        JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1220    return DAG.getNode(ISD::OR, DL, MVT::i32,
1221                       DAG.getRegister(Lanai::R0, MVT::i32),
1222                       DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1223  } else {
1224    uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1225    uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1226
1227    SDValue Hi = DAG.getTargetJumpTable(
1228        JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1229    SDValue Lo = DAG.getTargetJumpTable(
1230        JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1231    Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1232    Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1233    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1234    return Result;
1235  }
1236}
1237
1238SDValue LanaiTargetLowering::LowerSRL_PARTS(SDValue Op,
1239                                            SelectionDAG &DAG) const {
1240  MVT VT = Op.getSimpleValueType();
1241  unsigned VTBits = VT.getSizeInBits();
1242  SDLoc dl(Op);
1243  SDValue ShOpLo = Op.getOperand(0);
1244  SDValue ShOpHi = Op.getOperand(1);
1245  SDValue ShAmt = Op.getOperand(2);
1246
1247  // Performs the following for a >> b:
1248  //   unsigned r_high = a_high >> b;
1249  //   r_high = (32 - b <= 0) ? 0 : r_high;
1250  //
1251  //   unsigned r_low = a_low >> b;
1252  //   r_low = (32 - b <= 0) ? r_high : r_low;
1253  //   r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1254  //   return (unsigned long long)r_high << 32 | r_low;
1255  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1256  // mask the shift amount.
1257
1258  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1259  SDValue NegatedPlus32 = DAG.getNode(
1260      ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1261  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1262
1263  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1264  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1265
1266  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1267  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1268  SDValue CarryBits =
1269      DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1270  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1271  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1272                     DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1273
1274  SDValue Ops[2] = {Lo, Hi};
1275  return DAG.getMergeValues(Ops, dl);
1276}
1277
1278// Helper function that checks if N is a null or all ones constant.
1279static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1280  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1281}
1282
1283// Return true if N is conditionally 0 or all ones.
1284// Detects these expressions where cc is an i1 value:
1285//
1286//   (select cc 0, y)   [AllOnes=0]
1287//   (select cc y, 0)   [AllOnes=0]
1288//   (zext cc)          [AllOnes=0]
1289//   (sext cc)          [AllOnes=0/1]
1290//   (select cc -1, y)  [AllOnes=1]
1291//   (select cc y, -1)  [AllOnes=1]
1292//
1293// * AllOnes determines whether to check for an all zero (AllOnes false) or an
1294//   all ones operand (AllOnes true).
1295// * Invert is set when N is the all zero/ones constant when CC is false.
1296// * OtherOp is set to the alternative value of N.
1297//
1298// For example, for (select cc X, Y) and AllOnes = 0 if:
1299// * X = 0, Invert = False and OtherOp = Y
1300// * Y = 0, Invert = True and OtherOp = X
1301static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1302                                       bool &Invert, SDValue &OtherOp,
1303                                       SelectionDAG &DAG) {
1304  switch (N->getOpcode()) {
1305  default:
1306    return false;
1307  case ISD::SELECT: {
1308    CC = N->getOperand(0);
1309    SDValue N1 = N->getOperand(1);
1310    SDValue N2 = N->getOperand(2);
1311    if (isZeroOrAllOnes(N1, AllOnes)) {
1312      Invert = false;
1313      OtherOp = N2;
1314      return true;
1315    }
1316    if (isZeroOrAllOnes(N2, AllOnes)) {
1317      Invert = true;
1318      OtherOp = N1;
1319      return true;
1320    }
1321    return false;
1322  }
1323  case ISD::ZERO_EXTEND: {
1324    // (zext cc) can never be the all ones value.
1325    if (AllOnes)
1326      return false;
1327    CC = N->getOperand(0);
1328    if (CC.getValueType() != MVT::i1)
1329      return false;
1330    SDLoc dl(N);
1331    EVT VT = N->getValueType(0);
1332    OtherOp = DAG.getConstant(1, dl, VT);
1333    Invert = true;
1334    return true;
1335  }
1336  case ISD::SIGN_EXTEND: {
1337    CC = N->getOperand(0);
1338    if (CC.getValueType() != MVT::i1)
1339      return false;
1340    SDLoc dl(N);
1341    EVT VT = N->getValueType(0);
1342    Invert = !AllOnes;
1343    if (AllOnes)
1344      // When looking for an AllOnes constant, N is an sext, and the 'other'
1345      // value is 0.
1346      OtherOp = DAG.getConstant(0, dl, VT);
1347    else
1348      OtherOp =
1349          DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
1350    return true;
1351  }
1352  }
1353}
1354
1355// Combine a constant select operand into its use:
1356//
1357//   (add (select cc, 0, c), x)  -> (select cc, x, (add, x, c))
1358//   (sub x, (select cc, 0, c))  -> (select cc, x, (sub, x, c))
1359//   (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))  [AllOnes=1]
1360//   (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
1361//   (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))
1362//
1363// The transform is rejected if the select doesn't have a constant operand that
1364// is null, or all ones when AllOnes is set.
1365//
1366// Also recognize sext/zext from i1:
1367//
1368//   (add (zext cc), x) -> (select cc (add x, 1), x)
1369//   (add (sext cc), x) -> (select cc (add x, -1), x)
1370//
1371// These transformations eventually create predicated instructions.
1372static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1373                                   TargetLowering::DAGCombinerInfo &DCI,
1374                                   bool AllOnes) {
1375  SelectionDAG &DAG = DCI.DAG;
1376  EVT VT = N->getValueType(0);
1377  SDValue NonConstantVal;
1378  SDValue CCOp;
1379  bool SwapSelectOps;
1380  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1381                                  NonConstantVal, DAG))
1382    return SDValue();
1383
1384  // Slct is now know to be the desired identity constant when CC is true.
1385  SDValue TrueVal = OtherOp;
1386  SDValue FalseVal =
1387      DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1388  // Unless SwapSelectOps says CC should be false.
1389  if (SwapSelectOps)
1390    std::swap(TrueVal, FalseVal);
1391
1392  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1393}
1394
1395// Attempt combineSelectAndUse on each operand of a commutative operator N.
1396static SDValue
1397combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1398                               bool AllOnes) {
1399  SDValue N0 = N->getOperand(0);
1400  SDValue N1 = N->getOperand(1);
1401  if (N0.getNode()->hasOneUse())
1402    if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1403      return Result;
1404  if (N1.getNode()->hasOneUse())
1405    if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1406      return Result;
1407  return SDValue();
1408}
1409
1410// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1411static SDValue PerformSUBCombine(SDNode *N,
1412                                 TargetLowering::DAGCombinerInfo &DCI) {
1413  SDValue N0 = N->getOperand(0);
1414  SDValue N1 = N->getOperand(1);
1415
1416  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1417  if (N1.getNode()->hasOneUse())
1418    if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1419      return Result;
1420
1421  return SDValue();
1422}
1423
1424SDValue LanaiTargetLowering::PerformDAGCombine(SDNode *N,
1425                                               DAGCombinerInfo &DCI) const {
1426  switch (N->getOpcode()) {
1427  default:
1428    break;
1429  case ISD::ADD:
1430  case ISD::OR:
1431  case ISD::XOR:
1432    return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1433  case ISD::AND:
1434    return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1435  case ISD::SUB:
1436    return PerformSUBCombine(N, DCI);
1437  }
1438
1439  return SDValue();
1440}
1441