MipsAsmBackend.cpp revision c5707112e7635d1dd2f2cc9c4f42e79a51302cca 
1//===-- MipsASMBackend.cpp - Mips Asm Backend  ----------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "MipsFixupKinds.h"
16#include "MCTargetDesc/MipsMCTargetDesc.h"
17#include "llvm/ADT/Twine.h"
18#include "llvm/MC/MCAsmBackend.h"
19#include "llvm/MC/MCAssembler.h"
20#include "llvm/MC/MCDirectives.h"
21#include "llvm/MC/MCELFObjectWriter.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCMachObjectWriter.h"
24#include "llvm/MC/MCObjectWriter.h"
25#include "llvm/MC/MCSectionELF.h"
26#include "llvm/MC/MCSectionMachO.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/Object/MachOFormat.h"
29#include "llvm/Support/ELF.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/raw_ostream.h"
32
33using namespace llvm;
34
35// Prepare value for the target space for it
36static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
37
38  // Add/subtract and shift
39  switch (Kind) {
40  default:
41    return 0;
42  case FK_GPRel_4:
43  case FK_Data_4:
44  case Mips::fixup_Mips_LO16:
45    break;
46  case Mips::fixup_Mips_PC16:
47    // So far we are only using this type for branches.
48    // For branches we start 1 instruction after the branch
49    // so the displacement will be one instruction size less.
50    Value -= 4;
51    // The displacement is then divided by 4 to give us an 18 bit
52    // address range.
53    Value >>= 2;
54    break;
55  case Mips::fixup_Mips_26:
56    // So far we are only using this type for jumps.
57    // The displacement is then divided by 4 to give us an 28 bit
58    // address range.
59    Value >>= 2;
60    break;
61  case Mips::fixup_Mips_HI16:
62  case Mips::fixup_Mips_GOT_Local:
63    // Get the higher 16-bits. Also add 1 if bit 15 is 1.
64    Value = (Value >> 16) + ((Value & 0x8000) != 0);
65    break;
66  }
67
68  return Value;
69}
70
71namespace {
72class MipsAsmBackend : public MCAsmBackend {
73public:
74  uint8_t OSABI;
75  MipsAsmBackend(const Target &T, uint8_t OSABI_) :
76    MCAsmBackend(), OSABI(OSABI_) {}
77
78  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
79  /// data fragment, at the offset specified by the fixup and following the
80  /// fixup kind as appropriate.
81  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
82                  uint64_t Value) const {
83    MCFixupKind Kind = Fixup.getKind();
84    Value = adjustFixupValue((unsigned)Kind, Value);
85
86    if (!Value)
87      return; // Doesn't change encoding.
88
89    unsigned Offset = Fixup.getOffset();
90    // FIXME: The below code will not work across endian models
91    // How many bytes/bits are we fixing up?
92    unsigned NumBytes = ((getFixupKindInfo(Kind).TargetSize-1)/8)+1;
93    uint64_t Mask = ((uint64_t)1 << getFixupKindInfo(Kind).TargetSize) - 1;
94
95    // Grab current value, if any, from bits.
96    uint64_t CurVal = 0;
97    for (unsigned i = 0; i != NumBytes; ++i)
98      CurVal |= ((uint8_t)Data[Offset + i]) << (i * 8);
99
100    CurVal = (CurVal & ~Mask) | ((CurVal + Value) & Mask);
101
102    // Write out the bytes back to the code/data bits.
103    // First the unaffected bits and then the fixup.
104    for (unsigned i = 0; i != NumBytes; ++i) {
105      Data[Offset + i] = uint8_t((CurVal >> (i * 8)) & 0xff);
106    }
107}
108
109  unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
110
111  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
112    const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
113      // This table *must* be in same the order of fixup_* kinds in
114      // MipsFixupKinds.h.
115      //
116      // name                    offset  bits  flags
117      { "fixup_Mips_16",           0,     16,   0 },
118      { "fixup_Mips_32",           0,     32,   0 },
119      { "fixup_Mips_REL32",        0,     32,   0 },
120      { "fixup_Mips_26",           0,     26,   0 },
121      { "fixup_Mips_HI16",         0,     16,   0 },
122      { "fixup_Mips_LO16",         0,     16,   0 },
123      { "fixup_Mips_GPREL16",      0,     16,   0 },
124      { "fixup_Mips_LITERAL",      0,     16,   0 },
125      { "fixup_Mips_GOT_Global",   0,     16,   0 },
126      { "fixup_Mips_GOT_Local",    0,     16,   0 },
127      { "fixup_Mips_PC16",         0,     16,  MCFixupKindInfo::FKF_IsPCRel },
128      { "fixup_Mips_CALL16",       0,     16,   0 },
129      { "fixup_Mips_GPREL32",      0,     32,   0 },
130      { "fixup_Mips_SHIFT5",       6,      5,   0 },
131      { "fixup_Mips_SHIFT6",       6,      5,   0 },
132      { "fixup_Mips_64",           0,     64,   0 },
133      { "fixup_Mips_TLSGD",        0,     16,   0 },
134      { "fixup_Mips_GOTTPREL",     0,     16,   0 },
135      { "fixup_Mips_TPREL_HI",     0,     16,   0 },
136      { "fixup_Mips_TPREL_LO",     0,     16,   0 },
137      { "fixup_Mips_TLSLDM",       0,     16,   0 },
138      { "fixup_Mips_DTPREL_HI",    0,     16,   0 },
139      { "fixup_Mips_DTPREL_LO",    0,     16,   0 },
140      { "fixup_Mips_Branch_PCRel", 0,     16,  MCFixupKindInfo::FKF_IsPCRel }
141    };
142
143    if (Kind < FirstTargetFixupKind)
144      return MCAsmBackend::getFixupKindInfo(Kind);
145
146    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
147           "Invalid kind!");
148    return Infos[Kind - FirstTargetFixupKind];
149  }
150
151  /// @name Target Relaxation Interfaces
152  /// @{
153
154  /// MayNeedRelaxation - Check whether the given instruction may need
155  /// relaxation.
156  ///
157  /// \param Inst - The instruction to test.
158  bool mayNeedRelaxation(const MCInst &Inst) const {
159    return false;
160  }
161
162  /// fixupNeedsRelaxation - Target specific predicate for whether a given
163  /// fixup requires the associated instruction to be relaxed.
164  bool fixupNeedsRelaxation(const MCFixup &Fixup,
165                            uint64_t Value,
166                            const MCInstFragment *DF,
167                            const MCAsmLayout &Layout) const {
168    // FIXME.
169    assert(0 && "RelaxInstruction() unimplemented");
170    return false;
171  }
172
173  /// RelaxInstruction - Relax the instruction in the given fragment
174  /// to the next wider instruction.
175  ///
176  /// \param Inst - The instruction to relax, which may be the same
177  /// as the output.
178  /// \parm Res [output] - On return, the relaxed instruction.
179  void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
180  }
181
182  /// @}
183
184  /// WriteNopData - Write an (optimal) nop sequence of Count bytes
185  /// to the given output. If the target cannot generate such a sequence,
186  /// it should return an error.
187  ///
188  /// \return - True on success.
189  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
190    return true;
191  }
192};
193
194class MipsEB_AsmBackend : public MipsAsmBackend {
195public:
196  MipsEB_AsmBackend(const Target &T, uint8_t _OSABI)
197    : MipsAsmBackend(T, _OSABI) {}
198
199  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
200    return createMipsELFObjectWriter(OS, /*IsLittleEndian*/ false, OSABI);
201  }
202};
203
204class MipsEL_AsmBackend : public MipsAsmBackend {
205public:
206  MipsEL_AsmBackend(const Target &T, uint8_t _OSABI)
207    : MipsAsmBackend(T, _OSABI) {}
208
209  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
210    return createMipsELFObjectWriter(OS, /*IsLittleEndian*/ true, OSABI);
211  }
212};
213} // namespace
214
215MCAsmBackend *llvm::createMipsBEAsmBackend(const Target &T, StringRef TT) {
216  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
217  return new MipsEB_AsmBackend(T, OSABI);
218}
219
220MCAsmBackend *llvm::createMipsLEAsmBackend(const Target &T, StringRef TT) {
221  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
222  return new MipsEL_AsmBackend(T, OSABI);
223}
224