1# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s 2 3# This file is checking ARMv7 encodings which are globally invalid, usually due 4# to the constraints of the instructions not being met. For example invalid 5# combinations of registers. 6 7 8#------------------------------------------------------------------------------ 9# Undefined encodings for bfi 10#------------------------------------------------------------------------------ 11 12# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) 13# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14# ------------------------------------------------------------------------------------------------- 15# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| 16# ------------------------------------------------------------------------------------------------- 17# 18# if d == 15 then UNPREDICTABLE; 19[0x16 0xf0 0xcf 0xe7] 20# CHECK: potentially undefined instruction encoding 21# CHECK-NEXT: [0x16 0xf0 0xcf 0xe7] 22 23#------------------------------------------------------------------------------ 24# Undefined encodings for cdp2 25#------------------------------------------------------------------------------ 26 27[0xe0 0x6a 0x0c 0xfe] 28# CHECK: invalid instruction encoding 29# CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe] 30 31 32#------------------------------------------------------------------------------ 33# Undefined encodings for cps* 34#------------------------------------------------------------------------------ 35 36# invalid imod value (0b01) 37[0xc0 0x67 0x4 0xf1] 38# CHECK: invalid instruction encoding 39# CHECK-NEXT: [0xc0 0x67 0x4 0xf1] 40 41# invalid (imod, M, iflags) combination 42[0x93 0x00 0x02 0xf1] 43# CHECK: potentially undefined instruction encoding 44# CHECK-NEXT: [0x93 0x00 0x02 0xf1] 45 46# CPS: various encodings that are ambiguous with other instructions 47[0x9f 0xff 0x4e 0xf1] 48# CHECK: invalid instruction encoding 49# CHECK-NEXT: [0x9f 0xff 0x4e 0xf1] 50 51[0x80 0x80 0x2c 0xf1] 52# CHECK: invalid instruction encoding 53# CHECK-NEXT: [0x80 0x80 0x2c 0xf1] 54 55[0xce 0x3f 0x28 0xf1] 56# CHECK: invalid instruction encoding 57# CHECK-NEXT: [0xce 0x3f 0x28 0xf1] 58 59[0x80 0x00 0x20 0xf1] 60# CHECK: invalid instruction encoding 61# CHECK-NEXT: [0x80 0x00 0x20 0xf1] 62 63[0xa0 0x00 0x00 0xf1] 64# CHECK: invalid instruction encoding 65# CHECK-NEXT: [0xa0 0x00 0x00 0xf1] 66 67 68#------------------------------------------------------------------------------ 69# Undefined encoding space for hint instructions 70#------------------------------------------------------------------------------ 71 72# FIXME: is it "dbg #14" or not???? 73[0xfe 0xf0 0x20 0xe3] 74# CHCK: invalid instruction encoding 75 76 77#------------------------------------------------------------------------------ 78# Undefined encodings for ldc 79#------------------------------------------------------------------------------ 80 81# Opcode=0 Name=PHI Format=(42) 82# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 83# ------------------------------------------------------------------------------------------------- 84# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| 85# ------------------------------------------------------------------------------------------------- 86# 87# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. 88 89[0x92 0xb4 0x1f 0xdc] 90# CHECK: invalid instruction encoding 91# CHECK-NEXT: [0x92 0xb4 0x1f 0xdc] 92 93 94#------------------------------------------------------------------------------ 95# Undefined encodings for ldm 96#------------------------------------------------------------------------------ 97 98# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) 99# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100# ------------------------------------------------------------------------------------------------- 101# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| 102# ------------------------------------------------------------------------------------------------- 103# 104# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction 105# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction 106 107[0x32 0xb1 0x99 0xf8] 108# CHECK: invalid instruction encoding 109# CHECK-NEXT: [0x32 0xb1 0x99 0xf8] 110 111 112#------------------------------------------------------------------------------ 113# Undefined encodings for ldr 114#------------------------------------------------------------------------------ 115 116# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) 117# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 118# ------------------------------------------------------------------------------------------------- 119# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| 120# ------------------------------------------------------------------------------------------------- 121# 122# if m == 15 then UNPREDICTABLE 123 124[0x8f 0x60 0xb7 0xe7] 125# CHECK: potentially undefined instruction encoding 126# CHECK-NEXT: [0x8f 0x60 0xb7 0xe7] 127 128# LDR (register) has encoding Inst{4} = 0. 129[0xba 0xae 0x9f 0x57] 130# CHECK: invalid instruction encoding 131# CHECK-NEXT: [0xba 0xae 0x9f 0x57] 132 133# LDR_PRE/POST has encoding Inst{4} = 0. 134[0xde 0x69 0x18 0x46] 135# CHECK: invalid instruction encoding 136# CHECK-NEXT: [0xde 0x69 0x18 0x46] 137 138# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) 139# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 140# ------------------------------------------------------------------------------------------------- 141# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| 142# ------------------------------------------------------------------------------------------------- 143# 144# if wback && (n == 15 || n == t) then UNPREDICTABLE 145[0x05 0x70 0xd7 0xe6] 146# CHECK: potentially undefined instruction encoding 147# CHECK-NEXT: [0x05 0x70 0xd7 0xe6] 148 149 150 151#------------------------------------------------------------------------------ 152# Undefined encodings for mcr 153#------------------------------------------------------------------------------ 154 155# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) 156# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 157# ------------------------------------------------------------------------------------------------- 158# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 159# ------------------------------------------------------------------------------------------------- 160# 161# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C 162 163[0x1b 0x1b 0xa0 0x2e] 164# CHECK: invalid instruction encoding 165# CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e] 166 167 168#------------------------------------------------------------------------------ 169# Undefined encodings for mov/lsl 170#------------------------------------------------------------------------------ 171 172# Opcode=0 Name=PHI Format=(42) 173# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 174# ------------------------------------------------------------------------------------------------- 175# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 176# ------------------------------------------------------------------------------------------------- 177# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. 178# The instruction is UNPREDICTABLE, and is not a valid instruction. 179# 180# See also 181# A8.6.88 LSL (immediate) 182# A8.6.98 MOV (shifted register), and 183# I.1 Instruction encoding diagrams and pseudocode 184 185[0x2 0xd1 0xbc 0xf1] 186# CHECK: invalid instruction encoding 187# CHECK-NEXT: [0x2 0xd1 0xbc 0xf1] 188 189 190# Opcode=0 Name=PHI Format=(42) 191# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 192# ------------------------------------------------------------------------------------------------- 193# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| 194# ------------------------------------------------------------------------------------------------- 195# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. 196# The instruction is UNPREDICTABLE, and is not a valid instruction. 197# 198# See also 199# A8.6.97 MOV (register) 200 201[0x2 0xd0 0xbc 0xf1] 202# CHECK: invalid instruction encoding 203# CHECK-NEXT: [0x2 0xd0 0xbc 0xf1] 204 205# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) 206# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 207# ------------------------------------------------------------------------------------------------- 208# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| 209# ------------------------------------------------------------------------------------------------- 210# A8.6.89 LSL (register): Inst{7-4} = 0b0001 211[0x93 0x42 0xa0 0xd1] 212# CHECK: invalid instruction encoding 213# CHECK-NEXT: [0x93 0x42 0xa0 0xd1] 214 215# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) 216# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 217# ------------------------------------------------------------------------------------------------- 218# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 219# ------------------------------------------------------------------------------------------------- 220# 221# if d == 15 then UNPREDICTABLE 222[0x00 0xf0 0x41 0xe3] 223# CHECK: potentially undefined instruction encoding 224# CHECK-NEXT: [0x00 0xf0 0x41 0xe3] 225 226 227#------------------------------------------------------------------------------ 228# Undefined encodings for mrrc2 229#------------------------------------------------------------------------------ 230 231[0x00 0x1a 0x50 0xfc] 232# CHECK: invalid instruction encoding 233# CHECK-NEXT: [0x00 0x1a 0x50 0xfc] 234 235 236#------------------------------------------------------------------------------ 237# Undefined encodings for msr (imm) 238#------------------------------------------------------------------------------ 239 240# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) 241# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 242# ------------------------------------------------------------------------------------------------- 243# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| 244# ------------------------------------------------------------------------------------------------- 245# 246# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) 247# The hints instructions have more specific encodings, so if mask == 0, 248# we should reject this as an invalid instruction. 249 250[0xa7 0xf1 0x20 0x3] 251# CHECK: invalid instruction encoding 252# CHECK-NEXT: [0xa7 0xf1 0x20 0x3] 253 254 255#------------------------------------------------------------------------------ 256# Undefined encodings for sbfx 257#------------------------------------------------------------------------------ 258 259# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) 260# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 261# ------------------------------------------------------------------------------------------------- 262# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| 263# ------------------------------------------------------------------------------------------------- 264# 265# if d == 15 || n == 15 then UNPREDICTABLE; 266 267[0x5f 0x54 0xa7 0xe7] 268# CHECK: potentially undefined instruction encoding 269# CHECK-NEXT: [0x5f 0x54 0xa7 0xe7] 270 271#------------------------------------------------------------------------------ 272# Undefined encodings for smlad 273#------------------------------------------------------------------------------ 274 275# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) 276# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 277# ------------------------------------------------------------------------------------------------- 278# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 279# ------------------------------------------------------------------------------------------------- 280# 281# A8.6.167 282# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE 283 284[0x1b 0x68 0xf 0x97] 285# CHECK: potentially undefined instruction encoding 286# CHECK-NEXT: [0x1b 0x68 0xf 0x97] 287 288 289#------------------------------------------------------------------------------ 290# Undefined encodings for srs 291#------------------------------------------------------------------------------ 292 293# Opcode=0 Name=PHI Format=(42) 294# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 295# ------------------------------------------------------------------------------------------------- 296# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| 297# ------------------------------------------------------------------------------------------------- 298# Unknown format 299# 300# B6.1.10 SRS 301# Inst{19-8} = 0xd05 302# Inst{7-5} = 0b000 303 304[0x83 0x1c 0xc5 0xf8] 305# CHECK: invalid instruction encoding 306# CHECK-NEXT: [0x83 0x1c 0xc5 0xf8] 307 308[0x00 0x00 0x20 0xf8] 309# CHECK: invalid instruction encoding 310# CHECK-NEXT: [0x00 0x00 0x20 0xf8] 311 312[0xff 0xff 0xaf 0xf8] 313# CHECK: invalid instruction encoding 314# CHECK-NEXT: [0xff 0xff 0xaf 0xf8] 315 316[0x13 0x00 0xa0 0xf8] 317# CHECK: invalid instruction encoding 318# CHECK-NEXT: [0x13 0x00 0xa0 0xf8] 319 320#------------------------------------------------------------------------------ 321# Undefined encodings for sxtb 322#------------------------------------------------------------------------------ 323 324# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) 325# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 326# ------------------------------------------------------------------------------------------------- 327# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| 328# ------------------------------------------------------------------------------------------------- 329# 330# A8.6.223 SXTB 331# if d == 15 || m == 15 then UNPREDICTABLE; 332 333[0x75 0xf4 0xaf 0xe6] 334# CHECK: potentially undefined instruction encoding 335# CHECK-NEXT: [0x75 0xf4 0xaf 0xe6] 336 337#------------------------------------------------------------------------------ 338# Undefined encodings for NEON umaal 339#------------------------------------------------------------------------------ 340 341# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) 342# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 343# ------------------------------------------------------------------------------------------------- 344# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| 345# ------------------------------------------------------------------------------------------------- 346# 347# A8.6.244 UMAAL 348# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; 349[0x98 0xbf 0x4f 0xf0] 350# CHECK: invalid instruction encoding 351# CHECK-NEXT: [0x98 0xbf 0x4f 0xf0] 352 353#------------------------------------------------------------------------------ 354# Undefined encodings for NEON vcvt (float <-> fixed) 355#------------------------------------------------------------------------------ 356 357# imm6=0b0xxxxx -> UNDEFINED 358[0x1e 0xcf 0x92 0xf3] 359# CHECK: invalid instruction encoding 360# CHECK-NEXT: [0x1e 0xcf 0x92 0xf3] 361 362[0x3e 0xcf 0x92 0xf3] 363# CHECK: invalid instruction encoding 364# CHECK-NEXT: [0x3e 0xcf 0x92 0xf3] 365 366 367#------------------------------------------------------------------------------ 368# Undefined encodings for NEON vext 369#------------------------------------------------------------------------------ 370 371# invalid imm4 value (0b1xxx) 372# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; 373[0x8f 0xf9 0xf7 0xf2] 374# CHECK: invalid instruction encoding 375# CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2] 376 377#------------------------------------------------------------------------------ 378# Undefined encodings for NEON vldmsdb 379#------------------------------------------------------------------------------ 380 381# core registers out of range 382[0xa5 0xba 0x72 0xed] 383# CHECK: potentially undefined instruction encoding 384# CHECK-NEXT: [0xa5 0xba 0x72 0xed] 385 386 387#------------------------------------------------------------------------------ 388# Undefined encodings for NEON vmov 389#------------------------------------------------------------------------------ 390 391# VMOV cmode=0b1111 op=1 is UNDEFINED 392[0x70 0xef 0xc7 0xf3] 393# CHECK: invalid instruction encoding 394# CHECK-NEXT: [0x70 0xef 0xc7 0xf3] 395 396# VMOV cmode=0b1111 op=1 is UNDEFINED 397[0x30 0x0f 0x80 0xf3] 398# CHECK: invalid instruction encoding 399# CHECK-NEXT: [0x30 0x0f 0x80 0xf3] 400 401 402#------------------------------------------------------------------------------ 403# Undefined encodings for NEON vqadd 404#------------------------------------------------------------------------------ 405 406# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) 407# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 408# ------------------------------------------------------------------------------------------------- 409# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| 410# ------------------------------------------------------------------------------------------------- 411# 412# Qm -> bit[0] == 0, otherwise UNDEFINED 413[0xdb 0xe0 0x40 0xf2] 414# CHECK: invalid instruction encoding 415# CHECK-NEXT: [0xdb 0xe0 0x40 0xf2] 416 417 418#------------------------------------------------------------------------------ 419# Undefined encodings for NEON vld/vst 420#------------------------------------------------------------------------------ 421 422# A8.6.393 VST2 (multiple 2-element structures) 423[0xb3 0x09 0x03 0xf4] 424# CHECK: invalid instruction encoding 425# CHECK-NEXT: [0xb3 0x09 0x03 0xf4] 426 427# size == '11' ==> UNDEFINED 428[0xc3 0x08 0x03 0xf4] 429# CHECK: invalid instruction encoding 430# CHECK-NEXT: [0xc3 0x08 0x03 0xf4] 431 432# type == '1000' and align == '11' ==> UNDEFINED 433[0xb3 0x08 0x03 0xf4] 434# CHECK: invalid instruction encoding 435# CHECK-NEXT: [0xb3 0x08 0x03 0xf4] 436 437# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined 438[0xaf 0xb7 0x07 0xf4] 439# CHECK: invalid instruction encoding 440# CHECK-NEXT: [0xaf 0xb7 0x07 0xf4] 441 442# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined 443[0xbf 0xb7 0x07 0xf4] 444# CHECK: invalid instruction encoding 445# CHECK-NEXT: [0xbf 0xb7 0x07 0xf4] 446 447# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined 448[0xbf 0x8a 0x03 0xf4] 449# CHECK: invalid instruction encoding 450# CHECK-NEXT: [0xbf 0x8a 0x03 0xf4] 451 452# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined 453[0xaf 0xb6 0x07 0xf4] 454# CHECK: invalid instruction encoding 455# CHECK-NEXT: [0xaf 0xb6 0x07 0xf4] 456 457# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined 458[0xbf 0xb6 0x07 0xf4] 459# CHECK: invalid instruction encoding 460# CHECK-NEXT: [0xbf 0xb6 0x07 0xf4] 461 462# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined 463[0x4f 0xa8 0x07 0xf7] 464# CHECK: invalid instruction encoding 465# CHECK-NEXT: [0x4f 0xa8 0x07 0xf7] 466 467# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined 468[0x4f 0xa9 0x07 0xf7] 469# CHECK: invalid instruction encoding 470# CHECK-NEXT: [0x4f 0xa9 0x07 0xf7] 471 472# VST3 multi-element, size = 0b11 -> undefined 473[0xbf 0xa4 0x0b 0xf4] 474# CHECK: invalid instruction encoding 475# CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4] 476 477# VST3 multi-element, align = 0b10 -> undefined 478[0x6f 0xa4 0x0b 0xf4] 479# CHECK: invalid instruction encoding 480# CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4] 481 482# VST3 multi-element, align = 0b11 -> undefined 483[0x7f 0xa4 0x0b 0xf4] 484# CHECK: invalid instruction encoding 485# CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4] 486 487# VST4 multi-element, size = 0b11 -> undefined 488[0xcf 0x50 0x03 0xf4] 489# CHECK: invalid instruction encoding 490# CHECK-NEXT: [0xcf 0x50 0x03 0xf4] 491 492 493# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) 494# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 495# ------------------------------------------------------------------------------------------------- 496# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| 497# ------------------------------------------------------------------------------------------------- 498# 499# 'a' == 1 and data_size == 8 is invalid 500[0x3d 0x3c 0xa0 0xf4] 501# CHECK: invalid instruction encoding 502# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4] 503