invalid-armv7.txt revision 38c6ff6c111fcc53debb9e2880f89e2dd0676217
1# RUN: llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s 2 3# This file is checking ARMv7 encodings which are globally invalid, usually due 4# to the constraints of the instructions not being met. For example invalid 5# combinations of registers. 6 7 8#------------------------------------------------------------------------------ 9# Undefined encodings for bfi 10#------------------------------------------------------------------------------ 11 12# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) 13# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14# ------------------------------------------------------------------------------------------------- 15# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| 16# ------------------------------------------------------------------------------------------------- 17# 18# if d == 15 then UNPREDICTABLE; 19[0x16 0xf0 0xcf 0xe7] 20# CHECK: potentially undefined instruction encoding 21# CHECK-NEXT: [0x16 0xf0 0xcf 0xe7] 22 23#------------------------------------------------------------------------------ 24# Undefined encodings for cdp2 25#------------------------------------------------------------------------------ 26 27[0xe0 0x6a 0x0c 0xfe] 28# CHECK: invalid instruction encoding 29# CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe] 30 31 32#------------------------------------------------------------------------------ 33# Undefined encodings for cps* 34#------------------------------------------------------------------------------ 35 36# invalid imod value (0b01) 37[0xc0 0x67 0x4 0xf1] 38# CHECK: invalid instruction encoding 39# CHECK-NEXT: [0xc0 0x67 0x4 0xf1] 40 41# invalid (imod, M, iflags) combination 42[0x93 0x00 0x02 0xf1] 43# CHECK: potentially undefined instruction encoding 44# CHECK-NEXT: [0x93 0x00 0x02 0xf1] 45 46# CPS: various encodings that are ambiguous with other instructions 47[0x9f 0xff 0x4e 0xf1] 48# CHECK: invalid instruction encoding 49# CHECK-NEXT: [0x9f 0xff 0x4e 0xf1] 50 51[0x80 0x80 0x2c 0xf1] 52# CHECK: invalid instruction encoding 53# CHECK-NEXT: [0x80 0x80 0x2c 0xf1] 54 55[0xce 0x3f 0x28 0xf1] 56# CHECK: invalid instruction encoding 57# CHECK-NEXT: [0xce 0x3f 0x28 0xf1] 58 59[0x80 0x00 0x20 0xf1] 60# CHECK: invalid instruction encoding 61# CHECK-NEXT: [0x80 0x00 0x20 0xf1] 62 63[0xa0 0x00 0x00 0xf1] 64# CHECK: invalid instruction encoding 65# CHECK-NEXT: [0xa0 0x00 0x00 0xf1] 66 67 68#------------------------------------------------------------------------------ 69# Undefined encoding space for hint instructions 70#------------------------------------------------------------------------------ 71 72[0x05 0xf0 0x20 0xe3] 73# CHECK: invalid instruction encoding 74# CHECK-NEXT: [0x05 0xf0 0x20 0xe3] 75 76[0x41 0xf0 0x20 0xe3] 77# CHECK: invalid instruction encoding 78# CHECK-NEXT: [0x41 0xf0 0x20 0xe3] 79 80# FIXME: is it "dbg #14" or not???? 81[0xfe 0xf0 0x20 0xe3] 82# CHCK: invalid instruction encoding 83 84 85#------------------------------------------------------------------------------ 86# Undefined encodings for ldc 87#------------------------------------------------------------------------------ 88 89# Opcode=0 Name=PHI Format=(42) 90# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 91# ------------------------------------------------------------------------------------------------- 92# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| 93# ------------------------------------------------------------------------------------------------- 94# 95# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. 96 97[0x92 0xb4 0x1f 0xdc] 98# CHECK: invalid instruction encoding 99# CHECK-NEXT: [0x92 0xb4 0x1f 0xdc] 100 101 102#------------------------------------------------------------------------------ 103# Undefined encodings for ldm 104#------------------------------------------------------------------------------ 105 106# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) 107# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 108# ------------------------------------------------------------------------------------------------- 109# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| 110# ------------------------------------------------------------------------------------------------- 111# 112# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction 113# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction 114 115[0x32 0xb1 0x99 0xf8] 116# CHECK: invalid instruction encoding 117# CHECK-NEXT: [0x32 0xb1 0x99 0xf8] 118 119 120#------------------------------------------------------------------------------ 121# Undefined encodings for ldr 122#------------------------------------------------------------------------------ 123 124# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) 125# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 126# ------------------------------------------------------------------------------------------------- 127# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| 128# ------------------------------------------------------------------------------------------------- 129# 130# if m == 15 then UNPREDICTABLE 131 132[0x8f 0x60 0xb7 0xe7] 133# CHECK: potentially undefined instruction encoding 134# CHECK-NEXT: [0x8f 0x60 0xb7 0xe7] 135 136# LDR (register) has encoding Inst{4} = 0. 137[0xba 0xae 0x9f 0x57] 138# CHECK: invalid instruction encoding 139# CHECK-NEXT: [0xba 0xae 0x9f 0x57] 140 141# LDR_PRE/POST has encoding Inst{4} = 0. 142[0xde 0x69 0x18 0x46] 143# CHECK: invalid instruction encoding 144# CHECK-NEXT: [0xde 0x69 0x18 0x46] 145 146# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) 147# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 148# ------------------------------------------------------------------------------------------------- 149# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| 150# ------------------------------------------------------------------------------------------------- 151# 152# if wback && (n == 15 || n == t) then UNPREDICTABLE 153[0x05 0x70 0xd7 0xe6] 154# CHECK: potentially undefined instruction encoding 155# CHECK-NEXT: [0x05 0x70 0xd7 0xe6] 156 157 158 159#------------------------------------------------------------------------------ 160# Undefined encodings for mcr 161#------------------------------------------------------------------------------ 162 163# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) 164# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 165# ------------------------------------------------------------------------------------------------- 166# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 167# ------------------------------------------------------------------------------------------------- 168# 169# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C 170 171[0x1b 0x1b 0xa0 0x2e] 172# CHECK: invalid instruction encoding 173# CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e] 174 175 176#------------------------------------------------------------------------------ 177# Undefined encodings for mov/lsl 178#------------------------------------------------------------------------------ 179 180# Opcode=0 Name=PHI Format=(42) 181# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 182# ------------------------------------------------------------------------------------------------- 183# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 184# ------------------------------------------------------------------------------------------------- 185# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. 186# The instruction is UNPREDICTABLE, and is not a valid intruction. 187# 188# See also 189# A8.6.88 LSL (immediate) 190# A8.6.98 MOV (shifted register), and 191# I.1 Instruction encoding diagrams and pseudocode 192 193[0x2 0xd1 0xbc 0xf1] 194# CHECK: invalid instruction encoding 195# CHECK-NEXT: [0x2 0xd1 0xbc 0xf1] 196 197 198# Opcode=0 Name=PHI Format=(42) 199# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 200# ------------------------------------------------------------------------------------------------- 201# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| 202# ------------------------------------------------------------------------------------------------- 203# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. 204# The instruction is UNPREDICTABLE, and is not a valid intruction. 205# 206# See also 207# A8.6.97 MOV (register) 208 209[0x2 0xd0 0xbc 0xf1] 210# CHECK: invalid instruction encoding 211# CHECK-NEXT: [0x2 0xd0 0xbc 0xf1] 212 213# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) 214# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 215# ------------------------------------------------------------------------------------------------- 216# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| 217# ------------------------------------------------------------------------------------------------- 218# A8.6.89 LSL (register): Inst{7-4} = 0b0001 219[0x93 0x42 0xa0 0xd1] 220# CHECK: invalid instruction encoding 221# CHECK-NEXT: [0x93 0x42 0xa0 0xd1] 222 223# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) 224# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 225# ------------------------------------------------------------------------------------------------- 226# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 227# ------------------------------------------------------------------------------------------------- 228# 229# if d == 15 then UNPREDICTABLE 230[0x00 0xf0 0x41 0xe3] 231# CHECK: potentially undefined instruction encoding 232# CHECK-NEXT: [0x00 0xf0 0x41 0xe3] 233 234 235#------------------------------------------------------------------------------ 236# Undefined encodings for mrrc2 237#------------------------------------------------------------------------------ 238 239[0x00 0x1a 0x50 0xfc] 240# CHECK: invalid instruction encoding 241# CHECK-NEXT: [0x00 0x1a 0x50 0xfc] 242 243 244#------------------------------------------------------------------------------ 245# Undefined encodings for msr (imm) 246#------------------------------------------------------------------------------ 247 248# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) 249# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 250# ------------------------------------------------------------------------------------------------- 251# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| 252# ------------------------------------------------------------------------------------------------- 253# 254# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) 255# The hints instructions have more specific encodings, so if mask == 0, 256# we should reject this as an invalid instruction. 257 258[0xa7 0xf1 0x20 0x3] 259# CHECK: invalid instruction encoding 260# CHECK-NEXT: [0xa7 0xf1 0x20 0x3] 261 262 263#------------------------------------------------------------------------------ 264# Undefined encodings for sbfx 265#------------------------------------------------------------------------------ 266 267# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) 268# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 269# ------------------------------------------------------------------------------------------------- 270# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| 271# ------------------------------------------------------------------------------------------------- 272# 273# if d == 15 || n == 15 then UNPREDICTABLE; 274 275[0x5f 0x54 0xa7 0xe7] 276# CHECK: potentially undefined instruction encoding 277# CHECK-NEXT: [0x5f 0x54 0xa7 0xe7] 278 279#------------------------------------------------------------------------------ 280# Undefined encodings for smlad 281#------------------------------------------------------------------------------ 282 283# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) 284# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 285# ------------------------------------------------------------------------------------------------- 286# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 287# ------------------------------------------------------------------------------------------------- 288# 289# A8.6.167 290# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE 291 292[0x1b 0x68 0xf 0x97] 293# CHECK: potentially undefined instruction encoding 294# CHECK-NEXT: [0x1b 0x68 0xf 0x97] 295 296 297#------------------------------------------------------------------------------ 298# Undefined encodings for srs 299#------------------------------------------------------------------------------ 300 301# Opcode=0 Name=PHI Format=(42) 302# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 303# ------------------------------------------------------------------------------------------------- 304# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| 305# ------------------------------------------------------------------------------------------------- 306# Unknown format 307# 308# B6.1.10 SRS 309# Inst{19-8} = 0xd05 310# Inst{7-5} = 0b000 311 312[0x83 0x1c 0xc5 0xf8] 313# CHECK: invalid instruction encoding 314# CHECK-NEXT: [0x83 0x1c 0xc5 0xf8] 315 316[0x00 0x00 0x20 0xf8] 317# CHECK: invalid instruction encoding 318# CHECK-NEXT: [0x00 0x00 0x20 0xf8] 319 320[0xff 0xff 0xaf 0xf8] 321# CHECK: invalid instruction encoding 322# CHECK-NEXT: [0xff 0xff 0xaf 0xf8] 323 324[0x13 0x00 0xa0 0xf8] 325# CHECK: invalid instruction encoding 326# CHECK-NEXT: [0x13 0x00 0xa0 0xf8] 327 328#------------------------------------------------------------------------------ 329# Undefined encodings for sxtb 330#------------------------------------------------------------------------------ 331 332# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) 333# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 334# ------------------------------------------------------------------------------------------------- 335# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| 336# ------------------------------------------------------------------------------------------------- 337# 338# A8.6.223 SXTB 339# if d == 15 || m == 15 then UNPREDICTABLE; 340 341[0x75 0xf4 0xaf 0xe6] 342# CHECK: potentially undefined instruction encoding 343# CHECK-NEXT: [0x75 0xf4 0xaf 0xe6] 344 345#------------------------------------------------------------------------------ 346# Undefined encodings for NEON umaal 347#------------------------------------------------------------------------------ 348 349# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) 350# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 351# ------------------------------------------------------------------------------------------------- 352# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| 353# ------------------------------------------------------------------------------------------------- 354# 355# A8.6.244 UMAAL 356# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; 357[0x98 0xbf 0x4f 0xf0] 358# CHECK: invalid instruction encoding 359# CHECK-NEXT: [0x98 0xbf 0x4f 0xf0] 360 361#------------------------------------------------------------------------------ 362# Undefined encodings for NEON vcvt (float <-> fixed) 363#------------------------------------------------------------------------------ 364 365# imm6=0b0xxxxx -> UNDEFINED 366[0x1e 0xcf 0x92 0xf3] 367# CHECK: invalid instruction encoding 368# CHECK-NEXT: [0x1e 0xcf 0x92 0xf3] 369 370[0x3e 0xcf 0x92 0xf3] 371# CHECK: invalid instruction encoding 372# CHECK-NEXT: [0x3e 0xcf 0x92 0xf3] 373 374 375#------------------------------------------------------------------------------ 376# Undefined encodings for NEON vext 377#------------------------------------------------------------------------------ 378 379# invalid imm4 value (0b1xxx) 380# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; 381[0x8f 0xf9 0xf7 0xf2] 382# CHECK: invalid instruction encoding 383# CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2] 384 385#------------------------------------------------------------------------------ 386# Undefined encodings for NEON vldmsdb 387#------------------------------------------------------------------------------ 388 389# core registers out of range 390[0xa5 0xba 0x72 0xed] 391# CHECK: potentially undefined instruction encoding 392# CHECK-NEXT: [0xa5 0xba 0x72 0xed] 393 394 395#------------------------------------------------------------------------------ 396# Undefined encodings for NEON vmov 397#------------------------------------------------------------------------------ 398 399# VMOV cmode=0b1111 op=1 is UNDEFINED 400[0x70 0xef 0xc7 0xf3] 401# CHECK: invalid instruction encoding 402# CHECK-NEXT: [0x70 0xef 0xc7 0xf3] 403 404# VMOV cmode=0b1111 op=1 is UNDEFINED 405[0x30 0x0f 0x80 0xf3] 406# CHECK: invalid instruction encoding 407# CHECK-NEXT: [0x30 0x0f 0x80 0xf3] 408 409 410#------------------------------------------------------------------------------ 411# Undefined encodings for NEON vqadd 412#------------------------------------------------------------------------------ 413 414# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) 415# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 416# ------------------------------------------------------------------------------------------------- 417# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| 418# ------------------------------------------------------------------------------------------------- 419# 420# Qm -> bit[0] == 0, otherwise UNDEFINED 421[0xdb 0xe0 0x40 0xf2] 422# CHECK: invalid instruction encoding 423# CHECK-NEXT: [0xdb 0xe0 0x40 0xf2] 424 425 426#------------------------------------------------------------------------------ 427# Undefined encodings for NEON vld/vst 428#------------------------------------------------------------------------------ 429 430# A8.6.393 VST2 (multiple 2-element structures) 431[0xb3 0x09 0x03 0xf4] 432# CHECK: invalid instruction encoding 433# CHECK-NEXT: [0xb3 0x09 0x03 0xf4] 434 435# size == '11' ==> UNDEFINED 436[0xc3 0x08 0x03 0xf4] 437# CHECK: invalid instruction encoding 438# CHECK-NEXT: [0xc3 0x08 0x03 0xf4] 439 440# type == '1000' and align == '11' ==> UNDEFINED 441[0xb3 0x08 0x03 0xf4] 442# CHECK: invalid instruction encoding 443# CHECK-NEXT: [0xb3 0x08 0x03 0xf4] 444 445# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined 446[0xaf 0xb7 0x07 0xf4] 447# CHECK: invalid instruction encoding 448# CHECK-NEXT: [0xaf 0xb7 0x07 0xf4] 449 450# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined 451[0xbf 0xb7 0x07 0xf4] 452# CHECK: invalid instruction encoding 453# CHECK-NEXT: [0xbf 0xb7 0x07 0xf4] 454 455# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined 456[0xbf 0x8a 0x03 0xf4] 457# CHECK: invalid instruction encoding 458# CHECK-NEXT: [0xbf 0x8a 0x03 0xf4] 459 460# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined 461[0xaf 0xb6 0x07 0xf4] 462# CHECK: invalid instruction encoding 463# CHECK-NEXT: [0xaf 0xb6 0x07 0xf4] 464 465# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined 466[0xbf 0xb6 0x07 0xf4] 467# CHECK: invalid instruction encoding 468# CHECK-NEXT: [0xbf 0xb6 0x07 0xf4] 469 470# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined 471[0x4f 0xa8 0x07 0xf7] 472# CHECK: invalid instruction encoding 473# CHECK-NEXT: [0x4f 0xa8 0x07 0xf7] 474 475# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined 476[0x4f 0xa9 0x07 0xf7] 477# CHECK: invalid instruction encoding 478# CHECK-NEXT: [0x4f 0xa9 0x07 0xf7] 479 480# VST3 multi-element, size = 0b11 -> undefined 481[0xbf 0xa4 0x0b 0xf4] 482# CHECK: invalid instruction encoding 483# CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4] 484 485# VST3 multi-element, align = 0b10 -> undefined 486[0x6f 0xa4 0x0b 0xf4] 487# CHECK: invalid instruction encoding 488# CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4] 489 490# VST3 multi-element, align = 0b11 -> undefined 491[0x7f 0xa4 0x0b 0xf4] 492# CHECK: invalid instruction encoding 493# CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4] 494 495# VST4 multi-element, size = 0b11 -> undefined 496[0xcf 0x50 0x03 0xf4] 497# CHECK: invalid instruction encoding 498# CHECK-NEXT: [0xcf 0x50 0x03 0xf4] 499 500 501# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) 502# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 503# ------------------------------------------------------------------------------------------------- 504# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| 505# ------------------------------------------------------------------------------------------------- 506# 507# 'a' == 1 and data_size == 8 is invalid 508[0x3d 0x3c 0xa0 0xf4] 509# CHECK: invalid instruction encoding 510# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4] 511