1//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend emits code for use by the "fast" instruction
11// selection algorithm. See the comments at the top of
12// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
13//
14// This file scans through the target's tablegen instruction-info files
15// and extracts instructions with obvious-looking patterns, and it emits
16// code to look up these instructions by type and operator.
17//
18//===----------------------------------------------------------------------===//
19
20#include "CodeGenDAGPatterns.h"
21#include "llvm/ADT/StringSwitch.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/TableGen/Error.h"
25#include "llvm/TableGen/Record.h"
26#include "llvm/TableGen/TableGenBackend.h"
27#include <utility>
28using namespace llvm;
29
30
31/// InstructionMemo - This class holds additional information about an
32/// instruction needed to emit code for it.
33///
34namespace {
35struct InstructionMemo {
36  std::string Name;
37  const CodeGenRegisterClass *RC;
38  std::string SubRegNo;
39  std::vector<std::string>* PhysRegs;
40  std::string PredicateCheck;
41};
42} // End anonymous namespace
43
44/// ImmPredicateSet - This uniques predicates (represented as a string) and
45/// gives them unique (small) integer ID's that start at 0.
46namespace {
47class ImmPredicateSet {
48  DenseMap<TreePattern *, unsigned> ImmIDs;
49  std::vector<TreePredicateFn> PredsByName;
50public:
51
52  unsigned getIDFor(TreePredicateFn Pred) {
53    unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
54    if (Entry == 0) {
55      PredsByName.push_back(Pred);
56      Entry = PredsByName.size();
57    }
58    return Entry-1;
59  }
60
61  const TreePredicateFn &getPredicate(unsigned i) {
62    assert(i < PredsByName.size());
63    return PredsByName[i];
64  }
65
66  typedef std::vector<TreePredicateFn>::const_iterator iterator;
67  iterator begin() const { return PredsByName.begin(); }
68  iterator end() const { return PredsByName.end(); }
69
70};
71} // End anonymous namespace
72
73/// OperandsSignature - This class holds a description of a list of operand
74/// types. It has utility methods for emitting text based on the operands.
75///
76namespace {
77struct OperandsSignature {
78  class OpKind {
79    enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
80    char Repr;
81  public:
82
83    OpKind() : Repr(OK_Invalid) {}
84
85    bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
86    bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
87
88    static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
89    static OpKind getFP()  { OpKind K; K.Repr = OK_FP; return K; }
90    static OpKind getImm(unsigned V) {
91      assert((unsigned)OK_Imm+V < 128 &&
92             "Too many integer predicates for the 'Repr' char");
93      OpKind K; K.Repr = OK_Imm+V; return K;
94    }
95
96    bool isReg() const { return Repr == OK_Reg; }
97    bool isFP() const  { return Repr == OK_FP; }
98    bool isImm() const { return Repr >= OK_Imm; }
99
100    unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
101
102    void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
103                             bool StripImmCodes) const {
104      if (isReg())
105        OS << 'r';
106      else if (isFP())
107        OS << 'f';
108      else {
109        OS << 'i';
110        if (!StripImmCodes)
111          if (unsigned Code = getImmCode())
112            OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
113      }
114    }
115  };
116
117
118  SmallVector<OpKind, 3> Operands;
119
120  bool operator<(const OperandsSignature &O) const {
121    return Operands < O.Operands;
122  }
123  bool operator==(const OperandsSignature &O) const {
124    return Operands == O.Operands;
125  }
126
127  bool empty() const { return Operands.empty(); }
128
129  bool hasAnyImmediateCodes() const {
130    for (unsigned i = 0, e = Operands.size(); i != e; ++i)
131      if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
132        return true;
133    return false;
134  }
135
136  /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
137  /// to zero.
138  OperandsSignature getWithoutImmCodes() const {
139    OperandsSignature Result;
140    for (unsigned i = 0, e = Operands.size(); i != e; ++i)
141      if (!Operands[i].isImm())
142        Result.Operands.push_back(Operands[i]);
143      else
144        Result.Operands.push_back(OpKind::getImm(0));
145    return Result;
146  }
147
148  void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
149    bool EmittedAnything = false;
150    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
151      if (!Operands[i].isImm()) continue;
152
153      unsigned Code = Operands[i].getImmCode();
154      if (Code == 0) continue;
155
156      if (EmittedAnything)
157        OS << " &&\n        ";
158
159      TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
160
161      // Emit the type check.
162      OS << "VT == "
163         << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
164         << " && ";
165
166
167      OS << PredFn.getFnName() << "(imm" << i <<')';
168      EmittedAnything = true;
169    }
170  }
171
172  /// initialize - Examine the given pattern and initialize the contents
173  /// of the Operands array accordingly. Return true if all the operands
174  /// are supported, false otherwise.
175  ///
176  bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
177                  MVT::SimpleValueType VT,
178                  ImmPredicateSet &ImmediatePredicates,
179                  const CodeGenRegisterClass *OrigDstRC) {
180    if (InstPatNode->isLeaf())
181      return false;
182
183    if (InstPatNode->getOperator()->getName() == "imm") {
184      Operands.push_back(OpKind::getImm(0));
185      return true;
186    }
187
188    if (InstPatNode->getOperator()->getName() == "fpimm") {
189      Operands.push_back(OpKind::getFP());
190      return true;
191    }
192
193    const CodeGenRegisterClass *DstRC = nullptr;
194
195    for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
196      TreePatternNode *Op = InstPatNode->getChild(i);
197
198      // Handle imm operands specially.
199      if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
200        unsigned PredNo = 0;
201        if (!Op->getPredicateFns().empty()) {
202          TreePredicateFn PredFn = Op->getPredicateFns()[0];
203          // If there is more than one predicate weighing in on this operand
204          // then we don't handle it.  This doesn't typically happen for
205          // immediates anyway.
206          if (Op->getPredicateFns().size() > 1 ||
207              !PredFn.isImmediatePattern())
208            return false;
209          // Ignore any instruction with 'FastIselShouldIgnore', these are
210          // not needed and just bloat the fast instruction selector.  For
211          // example, X86 doesn't need to generate code to match ADD16ri8 since
212          // ADD16ri will do just fine.
213          Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
214          if (Rec->getValueAsBit("FastIselShouldIgnore"))
215            return false;
216
217          PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
218        }
219
220        // Handle unmatched immediate sizes here.
221        //if (Op->getType(0) != VT)
222        //  return false;
223
224        Operands.push_back(OpKind::getImm(PredNo));
225        continue;
226      }
227
228
229      // For now, filter out any operand with a predicate.
230      // For now, filter out any operand with multiple values.
231      if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
232        return false;
233
234      if (!Op->isLeaf()) {
235         if (Op->getOperator()->getName() == "fpimm") {
236          Operands.push_back(OpKind::getFP());
237          continue;
238        }
239        // For now, ignore other non-leaf nodes.
240        return false;
241      }
242
243      assert(Op->hasTypeSet(0) && "Type infererence not done?");
244
245      // For now, all the operands must have the same type (if they aren't
246      // immediates).  Note that this causes us to reject variable sized shifts
247      // on X86.
248      if (Op->getType(0) != VT)
249        return false;
250
251      DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue());
252      if (!OpDI)
253        return false;
254      Record *OpLeafRec = OpDI->getDef();
255
256      // For now, the only other thing we accept is register operands.
257      const CodeGenRegisterClass *RC = nullptr;
258      if (OpLeafRec->isSubClassOf("RegisterOperand"))
259        OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
260      if (OpLeafRec->isSubClassOf("RegisterClass"))
261        RC = &Target.getRegisterClass(OpLeafRec);
262      else if (OpLeafRec->isSubClassOf("Register"))
263        RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
264      else if (OpLeafRec->isSubClassOf("ValueType")) {
265        RC = OrigDstRC;
266      } else
267        return false;
268
269      // For now, this needs to be a register class of some sort.
270      if (!RC)
271        return false;
272
273      // For now, all the operands must have the same register class or be
274      // a strict subclass of the destination.
275      if (DstRC) {
276        if (DstRC != RC && !DstRC->hasSubClass(RC))
277          return false;
278      } else
279        DstRC = RC;
280      Operands.push_back(OpKind::getReg());
281    }
282    return true;
283  }
284
285  void PrintParameters(raw_ostream &OS) const {
286    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
287      if (Operands[i].isReg()) {
288        OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
289      } else if (Operands[i].isImm()) {
290        OS << "uint64_t imm" << i;
291      } else if (Operands[i].isFP()) {
292        OS << "const ConstantFP *f" << i;
293      } else {
294        llvm_unreachable("Unknown operand kind!");
295      }
296      if (i + 1 != e)
297        OS << ", ";
298    }
299  }
300
301  void PrintArguments(raw_ostream &OS,
302                      const std::vector<std::string> &PR) const {
303    assert(PR.size() == Operands.size());
304    bool PrintedArg = false;
305    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
306      if (PR[i] != "")
307        // Implicit physical register operand.
308        continue;
309
310      if (PrintedArg)
311        OS << ", ";
312      if (Operands[i].isReg()) {
313        OS << "Op" << i << ", Op" << i << "IsKill";
314        PrintedArg = true;
315      } else if (Operands[i].isImm()) {
316        OS << "imm" << i;
317        PrintedArg = true;
318      } else if (Operands[i].isFP()) {
319        OS << "f" << i;
320        PrintedArg = true;
321      } else {
322        llvm_unreachable("Unknown operand kind!");
323      }
324    }
325  }
326
327  void PrintArguments(raw_ostream &OS) const {
328    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
329      if (Operands[i].isReg()) {
330        OS << "Op" << i << ", Op" << i << "IsKill";
331      } else if (Operands[i].isImm()) {
332        OS << "imm" << i;
333      } else if (Operands[i].isFP()) {
334        OS << "f" << i;
335      } else {
336        llvm_unreachable("Unknown operand kind!");
337      }
338      if (i + 1 != e)
339        OS << ", ";
340    }
341  }
342
343
344  void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
345                           ImmPredicateSet &ImmPredicates,
346                           bool StripImmCodes = false) const {
347    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
348      if (PR[i] != "")
349        // Implicit physical register operand. e.g. Instruction::Mul expect to
350        // select to a binary op. On x86, mul may take a single operand with
351        // the other operand being implicit. We must emit something that looks
352        // like a binary instruction except for the very inner fastEmitInst_*
353        // call.
354        continue;
355      Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
356    }
357  }
358
359  void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
360                           bool StripImmCodes = false) const {
361    for (unsigned i = 0, e = Operands.size(); i != e; ++i)
362      Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
363  }
364};
365} // End anonymous namespace
366
367namespace {
368class FastISelMap {
369  // A multimap is needed instead of a "plain" map because the key is
370  // the instruction's complexity (an int) and they are not unique.
371  typedef std::multimap<int, InstructionMemo> PredMap;
372  typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
373  typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
374  typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
375  typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
376            OperandsOpcodeTypeRetPredMap;
377
378  OperandsOpcodeTypeRetPredMap SimplePatterns;
379
380  // This is used to check that there are no duplicate predicates
381  typedef std::multimap<std::string, bool> PredCheckMap;
382  typedef std::map<MVT::SimpleValueType, PredCheckMap> RetPredCheckMap;
383  typedef std::map<MVT::SimpleValueType, RetPredCheckMap> TypeRetPredCheckMap;
384  typedef std::map<std::string, TypeRetPredCheckMap> OpcodeTypeRetPredCheckMap;
385  typedef std::map<OperandsSignature, OpcodeTypeRetPredCheckMap>
386            OperandsOpcodeTypeRetPredCheckMap;
387
388  OperandsOpcodeTypeRetPredCheckMap SimplePatternsCheck;
389
390  std::map<OperandsSignature, std::vector<OperandsSignature> >
391    SignaturesWithConstantForms;
392
393  std::string InstNS;
394  ImmPredicateSet ImmediatePredicates;
395public:
396  explicit FastISelMap(std::string InstNS);
397
398  void collectPatterns(CodeGenDAGPatterns &CGP);
399  void printImmediatePredicates(raw_ostream &OS);
400  void printFunctionDefinitions(raw_ostream &OS);
401private:
402  void emitInstructionCode(raw_ostream &OS,
403                           const OperandsSignature &Operands,
404                           const PredMap &PM,
405                           const std::string &RetVTName);
406};
407} // End anonymous namespace
408
409static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
410  return CGP.getSDNodeInfo(Op).getEnumName();
411}
412
413static std::string getLegalCName(std::string OpName) {
414  std::string::size_type pos = OpName.find("::");
415  if (pos != std::string::npos)
416    OpName.replace(pos, 2, "_");
417  return OpName;
418}
419
420FastISelMap::FastISelMap(std::string instns) : InstNS(std::move(instns)) {}
421
422static std::string PhyRegForNode(TreePatternNode *Op,
423                                 const CodeGenTarget &Target) {
424  std::string PhysReg;
425
426  if (!Op->isLeaf())
427    return PhysReg;
428
429  Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef();
430  if (!OpLeafRec->isSubClassOf("Register"))
431    return PhysReg;
432
433  PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
434               ->getValue();
435  PhysReg += "::";
436  PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
437  return PhysReg;
438}
439
440void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
441  const CodeGenTarget &Target = CGP.getTargetInfo();
442
443  // Determine the target's namespace name.
444  InstNS = Target.getInstNamespace() + "::";
445  assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
446
447  // Scan through all the patterns and record the simple ones.
448  for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
449       E = CGP.ptm_end(); I != E; ++I) {
450    const PatternToMatch &Pattern = *I;
451
452    // For now, just look at Instructions, so that we don't have to worry
453    // about emitting multiple instructions for a pattern.
454    TreePatternNode *Dst = Pattern.getDstPattern();
455    if (Dst->isLeaf()) continue;
456    Record *Op = Dst->getOperator();
457    if (!Op->isSubClassOf("Instruction"))
458      continue;
459    CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
460    if (II.Operands.empty())
461      continue;
462
463    // For now, ignore multi-instruction patterns.
464    bool MultiInsts = false;
465    for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
466      TreePatternNode *ChildOp = Dst->getChild(i);
467      if (ChildOp->isLeaf())
468        continue;
469      if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
470        MultiInsts = true;
471        break;
472      }
473    }
474    if (MultiInsts)
475      continue;
476
477    // For now, ignore instructions where the first operand is not an
478    // output register.
479    const CodeGenRegisterClass *DstRC = nullptr;
480    std::string SubRegNo;
481    if (Op->getName() != "EXTRACT_SUBREG") {
482      Record *Op0Rec = II.Operands[0].Rec;
483      if (Op0Rec->isSubClassOf("RegisterOperand"))
484        Op0Rec = Op0Rec->getValueAsDef("RegClass");
485      if (!Op0Rec->isSubClassOf("RegisterClass"))
486        continue;
487      DstRC = &Target.getRegisterClass(Op0Rec);
488      if (!DstRC)
489        continue;
490    } else {
491      // If this isn't a leaf, then continue since the register classes are
492      // a bit too complicated for now.
493      if (!Dst->getChild(1)->isLeaf()) continue;
494
495      DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
496      if (SR)
497        SubRegNo = getQualifiedName(SR->getDef());
498      else
499        SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
500    }
501
502    // Inspect the pattern.
503    TreePatternNode *InstPatNode = Pattern.getSrcPattern();
504    if (!InstPatNode) continue;
505    if (InstPatNode->isLeaf()) continue;
506
507    // Ignore multiple result nodes for now.
508    if (InstPatNode->getNumTypes() > 1) continue;
509
510    Record *InstPatOp = InstPatNode->getOperator();
511    std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
512    MVT::SimpleValueType RetVT = MVT::isVoid;
513    if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
514    MVT::SimpleValueType VT = RetVT;
515    if (InstPatNode->getNumChildren()) {
516      assert(InstPatNode->getChild(0)->getNumTypes() == 1);
517      VT = InstPatNode->getChild(0)->getType(0);
518    }
519
520    // For now, filter out any instructions with predicates.
521    if (!InstPatNode->getPredicateFns().empty())
522      continue;
523
524    // Check all the operands.
525    OperandsSignature Operands;
526    if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates,
527                             DstRC))
528      continue;
529
530    std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
531    if (InstPatNode->getOperator()->getName() == "imm" ||
532        InstPatNode->getOperator()->getName() == "fpimm")
533      PhysRegInputs->push_back("");
534    else {
535      // Compute the PhysRegs used by the given pattern, and check that
536      // the mapping from the src to dst patterns is simple.
537      bool FoundNonSimplePattern = false;
538      unsigned DstIndex = 0;
539      for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
540        std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
541        if (PhysReg.empty()) {
542          if (DstIndex >= Dst->getNumChildren() ||
543              Dst->getChild(DstIndex)->getName() !=
544              InstPatNode->getChild(i)->getName()) {
545            FoundNonSimplePattern = true;
546            break;
547          }
548          ++DstIndex;
549        }
550
551        PhysRegInputs->push_back(PhysReg);
552      }
553
554      if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
555        FoundNonSimplePattern = true;
556
557      if (FoundNonSimplePattern)
558        continue;
559    }
560
561    // Check if the operands match one of the patterns handled by FastISel.
562    std::string ManglingSuffix;
563    raw_string_ostream SuffixOS(ManglingSuffix);
564    Operands.PrintManglingSuffix(SuffixOS, ImmediatePredicates, true);
565    SuffixOS.flush();
566    if (!StringSwitch<bool>(ManglingSuffix)
567        .Cases("", "r", "rr", "ri", "rf", true)
568        .Cases("rri", "i", "f", true)
569        .Default(false))
570      continue;
571
572    // Get the predicate that guards this pattern.
573    std::string PredicateCheck = Pattern.getPredicateCheck();
574
575    // Ok, we found a pattern that we can handle. Remember it.
576    InstructionMemo Memo = {
577      Pattern.getDstPattern()->getOperator()->getName(),
578      DstRC,
579      SubRegNo,
580      PhysRegInputs,
581      PredicateCheck
582    };
583
584    int complexity = Pattern.getPatternComplexity(CGP);
585
586    if (SimplePatternsCheck[Operands][OpcodeName][VT]
587         [RetVT].count(PredicateCheck)) {
588      PrintFatalError(Pattern.getSrcRecord()->getLoc(),
589                    "Duplicate predicate in FastISel table!");
590    }
591    SimplePatternsCheck[Operands][OpcodeName][VT][RetVT].insert(
592            std::make_pair(PredicateCheck, true));
593
594       // Note: Instructions with the same complexity will appear in the order
595          // that they are encountered.
596    SimplePatterns[Operands][OpcodeName][VT][RetVT].insert(
597      std::make_pair(complexity, Memo));
598
599    // If any of the operands were immediates with predicates on them, strip
600    // them down to a signature that doesn't have predicates so that we can
601    // associate them with the stripped predicate version.
602    if (Operands.hasAnyImmediateCodes()) {
603      SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
604        .push_back(Operands);
605    }
606  }
607}
608
609void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
610  if (ImmediatePredicates.begin() == ImmediatePredicates.end())
611    return;
612
613  OS << "\n// FastEmit Immediate Predicate functions.\n";
614  for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
615       E = ImmediatePredicates.end(); I != E; ++I) {
616    OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
617    OS << I->getImmediatePredicateCode() << "\n}\n";
618  }
619
620  OS << "\n\n";
621}
622
623void FastISelMap::emitInstructionCode(raw_ostream &OS,
624                                      const OperandsSignature &Operands,
625                                      const PredMap &PM,
626                                      const std::string &RetVTName) {
627  // Emit code for each possible instruction. There may be
628  // multiple if there are subtarget concerns.  A reverse iterator
629  // is used to produce the ones with highest complexity first.
630
631  bool OneHadNoPredicate = false;
632  for (PredMap::const_reverse_iterator PI = PM.rbegin(), PE = PM.rend();
633       PI != PE; ++PI) {
634    const InstructionMemo &Memo = PI->second;
635    std::string PredicateCheck = Memo.PredicateCheck;
636
637    if (PredicateCheck.empty()) {
638      assert(!OneHadNoPredicate &&
639             "Multiple instructions match and more than one had "
640             "no predicate!");
641      OneHadNoPredicate = true;
642    } else {
643      if (OneHadNoPredicate) {
644        // FIXME: This should be a PrintError once the x86 target
645        // fixes PR21575.
646        PrintWarning("Multiple instructions match and one with no "
647                     "predicate came before one with a predicate!  "
648                     "name:" + Memo.Name + "  predicate: " +
649                     PredicateCheck);
650      }
651      OS << "  if (" + PredicateCheck + ") {\n";
652      OS << "  ";
653    }
654
655    for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
656      if ((*Memo.PhysRegs)[i] != "")
657        OS << "  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
658           << "TII.get(TargetOpcode::COPY), "
659           << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
660    }
661
662    OS << "  return fastEmitInst_";
663    if (Memo.SubRegNo.empty()) {
664      Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
665     ImmediatePredicates, true);
666      OS << "(" << InstNS << Memo.Name << ", ";
667      OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
668      if (!Operands.empty())
669        OS << ", ";
670      Operands.PrintArguments(OS, *Memo.PhysRegs);
671      OS << ");\n";
672    } else {
673      OS << "extractsubreg(" << RetVTName
674         << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
675    }
676
677    if (!PredicateCheck.empty()) {
678      OS << "  }\n";
679    }
680  }
681  // Return 0 if all of the possibilities had predicates but none
682  // were satisfied.
683  if (!OneHadNoPredicate)
684    OS << "  return 0;\n";
685  OS << "}\n";
686  OS << "\n";
687}
688
689
690void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
691  // Now emit code for all the patterns that we collected.
692  for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
693       OE = SimplePatterns.end(); OI != OE; ++OI) {
694    const OperandsSignature &Operands = OI->first;
695    const OpcodeTypeRetPredMap &OTM = OI->second;
696
697    for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
698         I != E; ++I) {
699      const std::string &Opcode = I->first;
700      const TypeRetPredMap &TM = I->second;
701
702      OS << "// FastEmit functions for " << Opcode << ".\n";
703      OS << "\n";
704
705      // Emit one function for each opcode,type pair.
706      for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
707           TI != TE; ++TI) {
708        MVT::SimpleValueType VT = TI->first;
709        const RetPredMap &RM = TI->second;
710        if (RM.size() != 1) {
711          for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
712               RI != RE; ++RI) {
713            MVT::SimpleValueType RetVT = RI->first;
714            const PredMap &PM = RI->second;
715
716            OS << "unsigned fastEmit_"
717               << getLegalCName(Opcode)
718               << "_" << getLegalCName(getName(VT))
719               << "_" << getLegalCName(getName(RetVT)) << "_";
720            Operands.PrintManglingSuffix(OS, ImmediatePredicates);
721            OS << "(";
722            Operands.PrintParameters(OS);
723            OS << ") {\n";
724
725            emitInstructionCode(OS, Operands, PM, getName(RetVT));
726          }
727
728          // Emit one function for the type that demultiplexes on return type.
729          OS << "unsigned fastEmit_"
730             << getLegalCName(Opcode) << "_"
731             << getLegalCName(getName(VT)) << "_";
732          Operands.PrintManglingSuffix(OS, ImmediatePredicates);
733          OS << "(MVT RetVT";
734          if (!Operands.empty())
735            OS << ", ";
736          Operands.PrintParameters(OS);
737          OS << ") {\nswitch (RetVT.SimpleTy) {\n";
738          for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
739               RI != RE; ++RI) {
740            MVT::SimpleValueType RetVT = RI->first;
741            OS << "  case " << getName(RetVT) << ": return fastEmit_"
742               << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
743               << "_" << getLegalCName(getName(RetVT)) << "_";
744            Operands.PrintManglingSuffix(OS, ImmediatePredicates);
745            OS << "(";
746            Operands.PrintArguments(OS);
747            OS << ");\n";
748          }
749          OS << "  default: return 0;\n}\n}\n\n";
750
751        } else {
752          // Non-variadic return type.
753          OS << "unsigned fastEmit_"
754             << getLegalCName(Opcode) << "_"
755             << getLegalCName(getName(VT)) << "_";
756          Operands.PrintManglingSuffix(OS, ImmediatePredicates);
757          OS << "(MVT RetVT";
758          if (!Operands.empty())
759            OS << ", ";
760          Operands.PrintParameters(OS);
761          OS << ") {\n";
762
763          OS << "  if (RetVT.SimpleTy != " << getName(RM.begin()->first)
764             << ")\n    return 0;\n";
765
766          const PredMap &PM = RM.begin()->second;
767
768          emitInstructionCode(OS, Operands, PM, "RetVT");
769        }
770      }
771
772      // Emit one function for the opcode that demultiplexes based on the type.
773      OS << "unsigned fastEmit_"
774         << getLegalCName(Opcode) << "_";
775      Operands.PrintManglingSuffix(OS, ImmediatePredicates);
776      OS << "(MVT VT, MVT RetVT";
777      if (!Operands.empty())
778        OS << ", ";
779      Operands.PrintParameters(OS);
780      OS << ") {\n";
781      OS << "  switch (VT.SimpleTy) {\n";
782      for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
783           TI != TE; ++TI) {
784        MVT::SimpleValueType VT = TI->first;
785        std::string TypeName = getName(VT);
786        OS << "  case " << TypeName << ": return fastEmit_"
787           << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
788        Operands.PrintManglingSuffix(OS, ImmediatePredicates);
789        OS << "(RetVT";
790        if (!Operands.empty())
791          OS << ", ";
792        Operands.PrintArguments(OS);
793        OS << ");\n";
794      }
795      OS << "  default: return 0;\n";
796      OS << "  }\n";
797      OS << "}\n";
798      OS << "\n";
799    }
800
801    OS << "// Top-level FastEmit function.\n";
802    OS << "\n";
803
804    // Emit one function for the operand signature that demultiplexes based
805    // on opcode and type.
806    OS << "unsigned fastEmit_";
807    Operands.PrintManglingSuffix(OS, ImmediatePredicates);
808    OS << "(MVT VT, MVT RetVT, unsigned Opcode";
809    if (!Operands.empty())
810      OS << ", ";
811    Operands.PrintParameters(OS);
812    OS << ") ";
813    if (!Operands.hasAnyImmediateCodes())
814      OS << "override ";
815    OS << "{\n";
816
817    // If there are any forms of this signature available that operate on
818    // constrained forms of the immediate (e.g., 32-bit sext immediate in a
819    // 64-bit operand), check them first.
820
821    std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
822      = SignaturesWithConstantForms.find(Operands);
823    if (MI != SignaturesWithConstantForms.end()) {
824      // Unique any duplicates out of the list.
825      std::sort(MI->second.begin(), MI->second.end());
826      MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
827                       MI->second.end());
828
829      // Check each in order it was seen.  It would be nice to have a good
830      // relative ordering between them, but we're not going for optimality
831      // here.
832      for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
833        OS << "  if (";
834        MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
835        OS << ")\n    if (unsigned Reg = fastEmit_";
836        MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
837        OS << "(VT, RetVT, Opcode";
838        if (!MI->second[i].empty())
839          OS << ", ";
840        MI->second[i].PrintArguments(OS);
841        OS << "))\n      return Reg;\n\n";
842      }
843
844      // Done with this, remove it.
845      SignaturesWithConstantForms.erase(MI);
846    }
847
848    OS << "  switch (Opcode) {\n";
849    for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
850         I != E; ++I) {
851      const std::string &Opcode = I->first;
852
853      OS << "  case " << Opcode << ": return fastEmit_"
854         << getLegalCName(Opcode) << "_";
855      Operands.PrintManglingSuffix(OS, ImmediatePredicates);
856      OS << "(VT, RetVT";
857      if (!Operands.empty())
858        OS << ", ";
859      Operands.PrintArguments(OS);
860      OS << ");\n";
861    }
862    OS << "  default: return 0;\n";
863    OS << "  }\n";
864    OS << "}\n";
865    OS << "\n";
866  }
867
868  // TODO: SignaturesWithConstantForms should be empty here.
869}
870
871namespace llvm {
872
873void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
874  CodeGenDAGPatterns CGP(RK);
875  const CodeGenTarget &Target = CGP.getTargetInfo();
876  emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
877                       Target.getName() + " target", OS);
878
879  // Determine the target's namespace name.
880  std::string InstNS = Target.getInstNamespace() + "::";
881  assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
882
883  FastISelMap F(InstNS);
884  F.collectPatterns(CGP);
885  F.printImmediatePredicates(OS);
886  F.printFunctionDefinitions(OS);
887}
888
889} // End llvm namespace
890