1/*
2 * Copyright © 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27/**
28***************************************************************************************************
29* @file  addrlib.h
30* @brief Contains the AddrLib base class definition.
31***************************************************************************************************
32*/
33
34#ifndef __ADDR_LIB_H__
35#define __ADDR_LIB_H__
36
37
38#include "addrinterface.h"
39#include "addrobject.h"
40#include "addrelemlib.h"
41
42#if BRAHMA_BUILD
43#include "amdgpu_id.h"
44#else
45#include "atiid.h"
46#endif
47
48#ifndef CIASICIDGFXENGINE_R600
49#define CIASICIDGFXENGINE_R600 0x00000006
50#endif
51
52#ifndef CIASICIDGFXENGINE_R800
53#define CIASICIDGFXENGINE_R800 0x00000008
54#endif
55
56#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
57#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
58#endif
59
60#ifndef CIASICIDGFXENGINE_SEAISLAND
61#define CIASICIDGFXENGINE_SEAISLAND 0x0000000B
62#endif
63/**
64***************************************************************************************************
65* @brief Neutral enums that define pipeinterleave
66***************************************************************************************************
67*/
68enum AddrPipeInterleave
69{
70    ADDR_PIPEINTERLEAVE_256B = 256,
71    ADDR_PIPEINTERLEAVE_512B = 512,
72};
73
74/**
75***************************************************************************************************
76* @brief Neutral enums that define DRAM row size
77***************************************************************************************************
78*/
79enum AddrRowSize
80{
81    ADDR_ROWSIZE_1KB = 1024,
82    ADDR_ROWSIZE_2KB = 2048,
83    ADDR_ROWSIZE_4KB = 4096,
84    ADDR_ROWSIZE_8KB = 8192,
85};
86
87/**
88***************************************************************************************************
89* @brief Neutral enums that define bank interleave
90***************************************************************************************************
91*/
92enum AddrBankInterleave
93{
94    ADDR_BANKINTERLEAVE_1 = 1,
95    ADDR_BANKINTERLEAVE_2 = 2,
96    ADDR_BANKINTERLEAVE_4 = 4,
97    ADDR_BANKINTERLEAVE_8 = 8,
98};
99
100/**
101***************************************************************************************************
102* @brief Neutral enums that define MGPU chip tile size
103***************************************************************************************************
104*/
105enum AddrChipTileSize
106{
107    ADDR_CHIPTILESIZE_16 = 16,
108    ADDR_CHIPTILESIZE_32 = 32,
109    ADDR_CHIPTILESIZE_64 = 64,
110    ADDR_CHIPTILESIZE_128 = 128,
111};
112
113/**
114***************************************************************************************************
115* @brief Neutral enums that define shader engine tile size
116***************************************************************************************************
117*/
118enum AddrEngTileSize
119{
120    ADDR_SE_TILESIZE_16 = 16,
121    ADDR_SE_TILESIZE_32 = 32,
122};
123
124/**
125***************************************************************************************************
126* @brief Neutral enums that define bank swap size
127***************************************************************************************************
128*/
129enum AddrBankSwapSize
130{
131    ADDR_BANKSWAP_128B = 128,
132    ADDR_BANKSWAP_256B = 256,
133    ADDR_BANKSWAP_512B = 512,
134    ADDR_BANKSWAP_1KB = 1024,
135};
136
137/**
138***************************************************************************************************
139* @brief Neutral enums that define bank swap size
140***************************************************************************************************
141*/
142enum AddrSampleSplitSize
143{
144    ADDR_SAMPLESPLIT_1KB = 1024,
145    ADDR_SAMPLESPLIT_2KB = 2048,
146    ADDR_SAMPLESPLIT_4KB = 4096,
147    ADDR_SAMPLESPLIT_8KB = 8192,
148};
149
150/**
151***************************************************************************************************
152* @brief Flags for AddrTileMode
153***************************************************************************************************
154*/
155struct AddrTileModeFlags
156{
157    UINT_32 thickness       : 4;
158    UINT_32 isLinear        : 1;
159    UINT_32 isMicro         : 1;
160    UINT_32 isMacro         : 1;
161    UINT_32 isMacro3d       : 1;
162    UINT_32 isPrt           : 1;
163    UINT_32 isPrtNoRotation : 1;
164    UINT_32 isBankSwapped   : 1;
165};
166
167/**
168***************************************************************************************************
169* @brief This class contains asic independent address lib functionalities
170***************************************************************************************************
171*/
172class AddrLib : public AddrObject
173{
174public:
175    virtual ~AddrLib();
176
177    static ADDR_E_RETURNCODE Create(
178        const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
179
180    /// Pair of Create
181    VOID Destroy()
182    {
183        delete this;
184    }
185
186    static AddrLib* GetAddrLib(
187        ADDR_HANDLE hLib);
188
189    /// Returns AddrLib version (from compiled binary instead include file)
190    UINT_32 GetVersion()
191    {
192        return m_version;
193    }
194
195    /// Returns asic chip family name defined by AddrLib
196    AddrChipFamily GetAddrChipFamily()
197    {
198        return m_chipFamily;
199    }
200
201    /// Returns tileIndex support
202    BOOL_32 UseTileIndex(INT_32 index) const
203    {
204        return m_configFlags.useTileIndex && (index != TileIndexInvalid);
205    }
206
207    /// Returns combined swizzle support
208    BOOL_32 UseCombinedSwizzle() const
209    {
210        return m_configFlags.useCombinedSwizzle;
211    }
212
213    //
214    // Interface stubs
215    //
216    ADDR_E_RETURNCODE ComputeSurfaceInfo(
217        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
218        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
219
220    ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
221        const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
222        ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
223
224    ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
225        const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT*  pIn,
226        ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
227
228    ADDR_E_RETURNCODE ComputeSliceTileSwizzle(
229        const ADDR_COMPUTE_SLICESWIZZLE_INPUT*  pIn,
230        ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const;
231
232    ADDR_E_RETURNCODE ExtractBankPipeSwizzle(
233        const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
234        ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
235
236    ADDR_E_RETURNCODE CombineBankPipeSwizzle(
237        const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT*  pIn,
238        ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
239
240    ADDR_E_RETURNCODE ComputeBaseSwizzle(
241        const ADDR_COMPUTE_BASE_SWIZZLE_INPUT*  pIn,
242        ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const;
243
244    ADDR_E_RETURNCODE ComputeFmaskInfo(
245        const ADDR_COMPUTE_FMASK_INFO_INPUT*  pIn,
246        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
247
248    ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
249        const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*  pIn,
250        ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
251
252    ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
253        const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*  pIn,
254        ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
255
256    ADDR_E_RETURNCODE ConvertTileInfoToHW(
257        const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
258        ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
259
260    ADDR_E_RETURNCODE ConvertTileIndex(
261        const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
262        ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
263
264    ADDR_E_RETURNCODE ConvertTileIndex1(
265        const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
266        ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
267
268    ADDR_E_RETURNCODE GetTileIndex(
269        const ADDR_GET_TILEINDEX_INPUT* pIn,
270        ADDR_GET_TILEINDEX_OUTPUT* pOut) const;
271
272    ADDR_E_RETURNCODE ComputeHtileInfo(
273        const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
274        ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
275
276    ADDR_E_RETURNCODE ComputeCmaskInfo(
277        const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
278        ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
279
280    ADDR_E_RETURNCODE ComputeDccInfo(
281        const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
282        ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
283
284    ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
285        const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*  pIn,
286        ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
287
288    ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
289        const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*  pIn,
290        ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
291
292    ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
293        const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT*  pIn,
294        ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
295
296    ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
297        const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT*  pIn,
298        ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
299
300    ADDR_E_RETURNCODE ComputePrtInfo(
301        const ADDR_PRT_INFO_INPUT*  pIn,
302        ADDR_PRT_INFO_OUTPUT*       pOut) const;
303
304    ADDR_E_RETURNCODE Flt32ToDepthPixel(
305        const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
306        ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const;
307
308    ADDR_E_RETURNCODE Flt32ToColorPixel(
309        const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
310        ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const;
311
312    BOOL_32 GetExportNorm(
313        const ELEM_GETEXPORTNORM_INPUT* pIn) const;
314
315protected:
316    AddrLib();  // Constructor is protected
317    AddrLib(const AddrClient* pClient);
318
319    /// Pure Virtual function for Hwl computing surface info
320    virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
321        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
322        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
323
324    /// Pure Virtual function for Hwl computing surface address from coord
325    virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord(
326        const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
327        ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
328
329    /// Pure Virtual function for Hwl computing surface coord from address
330    virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr(
331        const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
332        ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const = 0;
333
334    /// Pure Virtual function for Hwl computing surface tile swizzle
335    virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle(
336        const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
337        ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const = 0;
338
339    /// Pure Virtual function for Hwl extracting bank/pipe swizzle from base256b
340    virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle(
341        const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
342        ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const = 0;
343
344    /// Pure Virtual function for Hwl combining bank/pipe swizzle
345    virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle(
346        UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO*  pTileInfo,
347        UINT_64 baseAddr, UINT_32* pTileSwizzle) const = 0;
348
349    /// Pure Virtual function for Hwl computing base swizzle
350    virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle(
351        const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
352        ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const = 0;
353
354    /// Pure Virtual function for Hwl computing HTILE base align
355    virtual UINT_32 HwlComputeHtileBaseAlign(
356        BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const = 0;
357
358    /// Pure Virtual function for Hwl computing HTILE bpp
359    virtual UINT_32 HwlComputeHtileBpp(
360        BOOL_32 isWidth8, BOOL_32 isHeight8) const = 0;
361
362    /// Pure Virtual function for Hwl computing HTILE bytes
363    virtual UINT_64 HwlComputeHtileBytes(
364        UINT_32 pitch, UINT_32 height, UINT_32 bpp,
365        BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
366
367    /// Pure Virtual function for Hwl computing FMASK info
368    virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
369        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
370        ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut) = 0;
371
372    /// Pure Virtual function for Hwl FMASK address from coord
373    virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord(
374        const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
375        ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
376
377    /// Pure Virtual function for Hwl FMASK coord from address
378    virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr(
379        const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
380        ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const = 0;
381
382    /// Pure Virtual function for Hwl convert tile info from real value to HW value
383    virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
384        const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
385        ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const = 0;
386
387    /// Pure Virtual function for Hwl compute mipmap info
388    virtual BOOL_32 HwlComputeMipLevel(
389        ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
390
391    /// Pure Virtual function for Hwl compute max cmask blockMax value
392    virtual BOOL_32 HwlGetMaxCmaskBlockMax() const = 0;
393
394    /// Pure Virtual function for Hwl compute fmask bits
395    virtual UINT_32 HwlComputeFmaskBits(
396        const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
397        UINT_32* pNumSamples) const = 0;
398
399    /// Virtual function to get index (not pure then no need to implement this in all hwls
400    virtual ADDR_E_RETURNCODE HwlGetTileIndex(
401        const ADDR_GET_TILEINDEX_INPUT* pIn,
402        ADDR_GET_TILEINDEX_OUTPUT*      pOut) const
403    {
404        return ADDR_NOTSUPPORTED;
405    }
406
407    /// Virtual function for Hwl to compute Dcc info
408    virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
409        const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
410        ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const
411    {
412        return ADDR_NOTSUPPORTED;
413    }
414
415    /// Virtual function to get cmask address for tc compatible cmask
416    virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
417        const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
418        ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
419    {
420        return ADDR_NOTSUPPORTED;
421    }
422    // Compute attributes
423
424    // HTILE
425    UINT_32    ComputeHtileInfo(
426        ADDR_HTILE_FLAGS flags,
427        UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices,
428        BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
429        ADDR_TILEINFO*  pTileInfo,
430        UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pHtileBytes,
431        UINT_32* pMacroWidth = NULL, UINT_32* pMacroHeight = NULL,
432        UINT_64* pSliceSize = NULL, UINT_32* pBaseAlign = NULL) const;
433
434    // CMASK
435    ADDR_E_RETURNCODE ComputeCmaskInfo(
436        ADDR_CMASK_FLAGS flags,
437        UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices, BOOL_32 isLinear,
438        ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pCmaskBytes,
439        UINT_32* pMacroWidth, UINT_32* pMacroHeight, UINT_64* pSliceSize = NULL,
440        UINT_32* pBaseAlign = NULL, UINT_32* pBlockMax = NULL) const;
441
442    virtual VOID HwlComputeTileDataWidthAndHeightLinear(
443        UINT_32* pMacroWidth, UINT_32* pMacroHeight,
444        UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
445
446    // CMASK & HTILE addressing
447    virtual UINT_64 HwlComputeXmaskAddrFromCoord(
448        UINT_32 pitch, UINT_32 height, UINT_32 x, UINT_32 y, UINT_32 slice,
449        UINT_32 numSlices, UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8,
450        BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo,
451        UINT_32* bitPosition) const;
452
453    virtual VOID HwlComputeXmaskCoordFromAddr(
454        UINT_64 addr, UINT_32 bitPosition, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
455        UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
456        ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
457
458    // Surface mipmap
459    VOID    ComputeMipLevel(
460        ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
461
462    /// Pure Virtual function for Hwl checking degrade for base level
463    virtual BOOL_32 HwlDegradeBaseLevel(
464        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
465
466    virtual BOOL_32 HwlOverrideTileMode(
467        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
468        AddrTileMode* pTileMode,
469        AddrTileType* pTileType) const
470    {
471        // not supported in hwl layer, FALSE for not-overrided
472        return FALSE;
473    }
474
475    AddrTileMode DegradeLargeThickTile(AddrTileMode tileMode, UINT_32 bpp) const;
476
477    VOID PadDimensions(
478        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
479        UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
480        UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
481        UINT_32* pSlices, UINT_32 sliceAlign) const;
482
483    virtual VOID HwlPadDimensions(
484        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
485        UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
486        UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
487        UINT_32* pSlices, UINT_32 sliceAlign) const
488    {
489    }
490
491    //
492    // Addressing shared for linear/1D tiling
493    //
494    UINT_64 ComputeSurfaceAddrFromCoordLinear(
495        UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
496        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
497        UINT_32* pBitPosition) const;
498
499    VOID    ComputeSurfaceCoordFromAddrLinear(
500        UINT_64 addr, UINT_32 bitPosition, UINT_32 bpp,
501        UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
502        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const;
503
504    VOID    ComputeSurfaceCoordFromAddrMicroTiled(
505        UINT_64 addr, UINT_32 bitPosition,
506        UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
507        AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
508        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
509        AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const;
510
511    UINT_32 ComputePixelIndexWithinMicroTile(
512        UINT_32 x, UINT_32 y, UINT_32 z,
513        UINT_32 bpp, AddrTileMode tileMode, AddrTileType microTileType) const;
514
515    /// Pure Virtual function for Hwl computing coord from offset inside micro tile
516    virtual VOID HwlComputePixelCoordFromOffset(
517        UINT_32 offset, UINT_32 bpp, UINT_32 numSamples,
518        AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
519        UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
520        AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const = 0;
521
522    //
523    // Addressing shared by all
524    //
525    virtual UINT_32 HwlGetPipes(
526        const ADDR_TILEINFO* pTileInfo) const;
527
528    UINT_32 ComputePipeFromAddr(
529        UINT_64 addr, UINT_32 numPipes) const;
530
531    /// Pure Virtual function for Hwl computing pipe from coord
532    virtual UINT_32 ComputePipeFromCoord(
533        UINT_32 x, UINT_32 y, UINT_32 slice, AddrTileMode tileMode,
534        UINT_32 pipeSwizzle, BOOL_32 flags, ADDR_TILEINFO* pTileInfo) const = 0;
535
536    /// Pure Virtual function for Hwl computing coord Y for 8 pipe cmask/htile
537    virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
538        UINT_32 pipe, UINT_32 x) const = 0;
539
540    //
541    // Initialization
542    //
543    /// Pure Virtual function for Hwl computing internal global parameters from h/w registers
544    virtual BOOL_32 HwlInitGlobalParams(
545        const ADDR_CREATE_INPUT* pCreateIn) = 0;
546
547    /// Pure Virtual function for Hwl converting chip family
548    virtual AddrChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
549
550    //
551    // Misc helper
552    //
553    static const AddrTileModeFlags m_modeFlags[ADDR_TM_COUNT];
554
555    static UINT_32 ComputeSurfaceThickness(
556        AddrTileMode tileMode);
557
558    // Checking tile mode
559    static BOOL_32 IsMacroTiled(AddrTileMode tileMode);
560    static BOOL_32 IsMacro3dTiled(AddrTileMode tileMode);
561    static BOOL_32 IsLinear(AddrTileMode tileMode);
562    static BOOL_32 IsMicroTiled(AddrTileMode tileMode);
563    static BOOL_32 IsPrtTileMode(AddrTileMode tileMode);
564    static BOOL_32 IsPrtNoRotationTileMode(AddrTileMode tileMode);
565
566    static UINT_32 Bits2Number(UINT_32 bitNum,...);
567
568    static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
569    {
570        return numFrags != 0 ? numFrags : Max(1u, numSamples);
571    }
572
573    /// Returns pointer of AddrElemLib
574    AddrElemLib* GetElemLib() const
575    {
576        return m_pElemLib;
577    }
578
579    /// Return TRUE if tile info is needed
580    BOOL_32 UseTileInfo() const
581    {
582        return !m_configFlags.ignoreTileInfo;
583    }
584
585    /// Returns fillSizeFields flag
586    UINT_32 GetFillSizeFieldsFlags() const
587    {
588        return m_configFlags.fillSizeFields;
589    }
590
591    /// Adjusts pitch alignment for flipping surface
592    VOID    AdjustPitchAlignment(
593        ADDR_SURFACE_FLAGS flags, UINT_32* pPitchAlign) const;
594
595    /// Overwrite tile config according to tile index
596    virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
597        INT_32 index, INT_32 macroModeIndex,
598        ADDR_TILEINFO* pInfo, AddrTileMode* mode = NULL, AddrTileType* type = NULL) const;
599
600    /// Overwrite macro tile config according to tile index
601    virtual INT_32 HwlComputeMacroModeIndex(
602        INT_32 index, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
603        ADDR_TILEINFO* pTileInfo, AddrTileMode *pTileMode = NULL, AddrTileType *pTileType = NULL
604        ) const
605    {
606        return TileIndexNoMacroIndex;
607    }
608
609    /// Pre-handler of 3x pitch (96 bit) adjustment
610    virtual UINT_32 HwlPreHandleBaseLvl3xPitch(
611        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
612    /// Post-handler of 3x pitch adjustment
613    virtual UINT_32 HwlPostHandleBaseLvl3xPitch(
614        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
615    /// Check miplevel after surface adjustment
616    ADDR_E_RETURNCODE PostComputeMipLevel(
617        ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
618        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
619
620    /// Quad buffer stereo support, has its implementation in ind. layer
621    virtual BOOL_32 ComputeQbStereoInfo(
622        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
623
624    /// Pure virutual function to compute stereo bank swizzle for right eye
625    virtual UINT_32 HwlComputeQbStereoRightSwizzle(
626        ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
627
628private:
629    // Disallow the copy constructor
630    AddrLib(const AddrLib& a);
631
632    // Disallow the assignment operator
633    AddrLib& operator=(const AddrLib& a);
634
635    VOID SetAddrChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
636
637    UINT_32 ComputeCmaskBaseAlign(
638        ADDR_CMASK_FLAGS flags, ADDR_TILEINFO*  pTileInfo) const;
639
640    UINT_64 ComputeCmaskBytes(
641        UINT_32 pitch, UINT_32 height, UINT_32 numSlices) const;
642
643    //
644    // CMASK/HTILE shared methods
645    //
646    VOID    ComputeTileDataWidthAndHeight(
647        UINT_32 bpp, UINT_32 cacheBits, ADDR_TILEINFO* pTileInfo,
648        UINT_32* pMacroWidth, UINT_32* pMacroHeight) const;
649
650    UINT_32 ComputeXmaskCoordYFromPipe(
651        UINT_32 pipe, UINT_32 x) const;
652
653    VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
654
655    BOOL_32 DegradeBaseLevel(
656        const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, AddrTileMode* pTileMode) const;
657
658protected:
659    AddrLibClass        m_class;        ///< Store class type (HWL type)
660
661    AddrChipFamily      m_chipFamily;   ///< Chip family translated from the one in atiid.h
662
663    UINT_32             m_chipRevision; ///< Revision id from xxx_id.h
664
665    UINT_32             m_version;      ///< Current version
666
667    //
668    // Global parameters
669    //
670    ADDR_CONFIG_FLAGS   m_configFlags;  ///< Global configuration flags. Note this is setup by
671                                        ///  AddrLib instead of Client except forceLinearAligned
672
673    UINT_32             m_pipes;        ///< Number of pipes
674    UINT_32             m_banks;        ///< Number of banks
675                                        ///  For r800 this is MC_ARB_RAMCFG.NOOFBANK
676                                        ///  Keep it here to do default parameter calculation
677
678    UINT_32             m_pipeInterleaveBytes;
679                                        ///< Specifies the size of contiguous address space
680                                        ///  within each tiling pipe when making linear
681                                        ///  accesses. (Formerly Group Size)
682
683    UINT_32             m_rowSize;      ///< DRAM row size, in bytes
684
685    UINT_32             m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
686    UINT_32             m_maxSamples;   ///< Max numSamples
687private:
688    AddrElemLib*        m_pElemLib;     ///< Element Lib pointer
689};
690
691AddrLib* AddrSIHwlInit  (const AddrClient* pClient);
692AddrLib* AddrCIHwlInit  (const AddrClient* pClient);
693
694#endif
695
696