1/************************************************************************** 2 * 3 * Copyright 2013 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28/* 29 * Authors: 30 * Christian König <christian.koenig@amd.com> 31 * 32 */ 33 34#include <stdio.h> 35 36#include "pipe/p_video_codec.h" 37 38#include "util/u_video.h" 39#include "util/u_memory.h" 40 41#include "vl/vl_video_buffer.h" 42 43#include "r600_pipe_common.h" 44#include "radeon_video.h" 45#include "radeon_vce.h" 46 47#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8)) 48#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8)) 49#define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8)) 50#define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8)) 51#define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8)) 52#define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8)) 53#define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8)) 54#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8)) 55 56/** 57 * flush commands to the hardware 58 */ 59static void flush(struct rvce_encoder *enc) 60{ 61 enc->ws->cs_flush(enc->cs, RADEON_FLUSH_ASYNC, NULL); 62 enc->task_info_idx = 0; 63 enc->bs_idx = 0; 64} 65 66#if 0 67static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb) 68{ 69 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE); 70 unsigned i = 0; 71 fprintf(stderr, "\n"); 72 fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]); 73 fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]); 74 fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]); 75 fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]); 76 fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]); 77 fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]); 78 fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]); 79 fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]); 80 fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]); 81 fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]); 82 fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]); 83 fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]); 84 fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]); 85 fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]); 86 fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]); 87 fprintf(stderr, "\n"); 88 enc->ws->buffer_unmap(fb->res->buf); 89} 90#endif 91 92/** 93 * reset the CPB handling 94 */ 95static void reset_cpb(struct rvce_encoder *enc) 96{ 97 unsigned i; 98 99 LIST_INITHEAD(&enc->cpb_slots); 100 for (i = 0; i < enc->cpb_num; ++i) { 101 struct rvce_cpb_slot *slot = &enc->cpb_array[i]; 102 slot->index = i; 103 slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP; 104 slot->frame_num = 0; 105 slot->pic_order_cnt = 0; 106 LIST_ADDTAIL(&slot->list, &enc->cpb_slots); 107 } 108} 109 110/** 111 * sort l0 and l1 to the top of the list 112 */ 113static void sort_cpb(struct rvce_encoder *enc) 114{ 115 struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL; 116 117 LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) { 118 if (i->frame_num == enc->pic.ref_idx_l0) 119 l0 = i; 120 121 if (i->frame_num == enc->pic.ref_idx_l1) 122 l1 = i; 123 124 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0) 125 break; 126 127 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B && 128 l0 && l1) 129 break; 130 } 131 132 if (l1) { 133 LIST_DEL(&l1->list); 134 LIST_ADD(&l1->list, &enc->cpb_slots); 135 } 136 137 if (l0) { 138 LIST_DEL(&l0->list); 139 LIST_ADD(&l0->list, &enc->cpb_slots); 140 } 141} 142 143/** 144 * get number of cpbs based on dpb 145 */ 146static unsigned get_cpb_num(struct rvce_encoder *enc) 147{ 148 unsigned w = align(enc->base.width, 16) / 16; 149 unsigned h = align(enc->base.height, 16) / 16; 150 unsigned dpb; 151 152 switch (enc->base.level) { 153 case 10: 154 dpb = 396; 155 break; 156 case 11: 157 dpb = 900; 158 break; 159 case 12: 160 case 13: 161 case 20: 162 dpb = 2376; 163 break; 164 case 21: 165 dpb = 4752; 166 break; 167 case 22: 168 case 30: 169 dpb = 8100; 170 break; 171 case 31: 172 dpb = 18000; 173 break; 174 case 32: 175 dpb = 20480; 176 break; 177 case 40: 178 case 41: 179 dpb = 32768; 180 break; 181 case 42: 182 dpb = 34816; 183 break; 184 case 50: 185 dpb = 110400; 186 break; 187 default: 188 case 51: 189 case 52: 190 dpb = 184320; 191 break; 192 } 193 194 return MIN2(dpb / (w * h), 16); 195} 196 197/** 198 * Get the slot for the currently encoded frame 199 */ 200struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc) 201{ 202 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list); 203} 204 205/** 206 * Get the slot for L0 207 */ 208struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc) 209{ 210 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list); 211} 212 213/** 214 * Get the slot for L1 215 */ 216struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc) 217{ 218 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list); 219} 220 221/** 222 * Calculate the offsets into the CPB 223 */ 224void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot, 225 signed *luma_offset, signed *chroma_offset) 226{ 227 unsigned pitch = align(enc->luma->level[0].nblk_x * enc->luma->bpe, 128); 228 unsigned vpitch = align(enc->luma->level[0].nblk_y, 16); 229 unsigned fsize = pitch * (vpitch + vpitch / 2); 230 231 *luma_offset = slot->index * fsize; 232 *chroma_offset = *luma_offset + pitch * vpitch; 233} 234 235/** 236 * destroy this video encoder 237 */ 238static void rvce_destroy(struct pipe_video_codec *encoder) 239{ 240 struct rvce_encoder *enc = (struct rvce_encoder*)encoder; 241 if (enc->stream_handle) { 242 struct rvid_buffer fb; 243 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING); 244 enc->fb = &fb; 245 enc->session(enc); 246 enc->feedback(enc); 247 enc->destroy(enc); 248 flush(enc); 249 rvid_destroy_buffer(&fb); 250 } 251 rvid_destroy_buffer(&enc->cpb); 252 enc->ws->cs_destroy(enc->cs); 253 FREE(enc->cpb_array); 254 FREE(enc); 255} 256 257static void rvce_begin_frame(struct pipe_video_codec *encoder, 258 struct pipe_video_buffer *source, 259 struct pipe_picture_desc *picture) 260{ 261 struct rvce_encoder *enc = (struct rvce_encoder*)encoder; 262 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source; 263 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture; 264 265 bool need_rate_control = 266 enc->pic.rate_ctrl.rate_ctrl_method != pic->rate_ctrl.rate_ctrl_method || 267 enc->pic.quant_i_frames != pic->quant_i_frames || 268 enc->pic.quant_p_frames != pic->quant_p_frames || 269 enc->pic.quant_b_frames != pic->quant_b_frames; 270 271 enc->pic = *pic; 272 get_pic_param(enc, pic); 273 274 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma); 275 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma); 276 277 if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR) 278 reset_cpb(enc); 279 else if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_P || 280 pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) 281 sort_cpb(enc); 282 283 if (!enc->stream_handle) { 284 struct rvid_buffer fb; 285 enc->stream_handle = rvid_alloc_stream_handle(); 286 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING); 287 enc->fb = &fb; 288 enc->session(enc); 289 enc->create(enc); 290 enc->config(enc); 291 enc->feedback(enc); 292 flush(enc); 293 //dump_feedback(enc, &fb); 294 rvid_destroy_buffer(&fb); 295 need_rate_control = false; 296 } 297 298 if (need_rate_control) { 299 enc->session(enc); 300 enc->config(enc); 301 flush(enc); 302 } 303} 304 305static void rvce_encode_bitstream(struct pipe_video_codec *encoder, 306 struct pipe_video_buffer *source, 307 struct pipe_resource *destination, 308 void **fb) 309{ 310 struct rvce_encoder *enc = (struct rvce_encoder*)encoder; 311 enc->get_buffer(destination, &enc->bs_handle, NULL); 312 enc->bs_size = destination->width0; 313 314 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer); 315 if (!rvid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) { 316 RVID_ERR("Can't create feedback buffer.\n"); 317 return; 318 } 319 if (!radeon_emitted(enc->cs, 0)) 320 enc->session(enc); 321 enc->encode(enc); 322 enc->feedback(enc); 323} 324 325static void rvce_end_frame(struct pipe_video_codec *encoder, 326 struct pipe_video_buffer *source, 327 struct pipe_picture_desc *picture) 328{ 329 struct rvce_encoder *enc = (struct rvce_encoder*)encoder; 330 struct rvce_cpb_slot *slot = LIST_ENTRY( 331 struct rvce_cpb_slot, enc->cpb_slots.prev, list); 332 333 if (!enc->dual_inst || enc->bs_idx > 1) 334 flush(enc); 335 336 /* update the CPB backtrack with the just encoded frame */ 337 slot->picture_type = enc->pic.picture_type; 338 slot->frame_num = enc->pic.frame_num; 339 slot->pic_order_cnt = enc->pic.pic_order_cnt; 340 if (!enc->pic.not_referenced) { 341 LIST_DEL(&slot->list); 342 LIST_ADD(&slot->list, &enc->cpb_slots); 343 } 344} 345 346static void rvce_get_feedback(struct pipe_video_codec *encoder, 347 void *feedback, unsigned *size) 348{ 349 struct rvce_encoder *enc = (struct rvce_encoder*)encoder; 350 struct rvid_buffer *fb = feedback; 351 352 if (size) { 353 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE); 354 355 if (ptr[1]) { 356 *size = ptr[4] - ptr[9]; 357 } else { 358 *size = 0; 359 } 360 361 enc->ws->buffer_unmap(fb->res->buf); 362 } 363 //dump_feedback(enc, fb); 364 rvid_destroy_buffer(fb); 365 FREE(fb); 366} 367 368/** 369 * flush any outstanding command buffers to the hardware 370 */ 371static void rvce_flush(struct pipe_video_codec *encoder) 372{ 373 struct rvce_encoder *enc = (struct rvce_encoder*)encoder; 374 375 flush(enc); 376} 377 378static void rvce_cs_flush(void *ctx, unsigned flags, 379 struct pipe_fence_handle **fence) 380{ 381 // just ignored 382} 383 384struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context, 385 const struct pipe_video_codec *templ, 386 struct radeon_winsys* ws, 387 rvce_get_buffer get_buffer) 388{ 389 struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen; 390 struct r600_common_context *rctx = (struct r600_common_context*)context; 391 struct rvce_encoder *enc; 392 struct pipe_video_buffer *tmp_buf, templat = {}; 393 struct radeon_surf *tmp_surf; 394 unsigned cpb_size; 395 396 if (!rscreen->info.vce_fw_version) { 397 RVID_ERR("Kernel doesn't supports VCE!\n"); 398 return NULL; 399 400 } else if (!rvce_is_fw_version_supported(rscreen)) { 401 RVID_ERR("Unsupported VCE fw version loaded!\n"); 402 return NULL; 403 } 404 405 enc = CALLOC_STRUCT(rvce_encoder); 406 if (!enc) 407 return NULL; 408 409 if (rscreen->info.drm_major == 3) 410 enc->use_vm = true; 411 if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) || 412 rscreen->info.drm_major == 3) 413 enc->use_vui = true; 414 if (rscreen->info.family >= CHIP_TONGA && 415 rscreen->info.family != CHIP_STONEY && 416 rscreen->info.family != CHIP_POLARIS11 && 417 rscreen->info.family != CHIP_POLARIS12) 418 enc->dual_pipe = true; 419 /* TODO enable B frame with dual instance */ 420 if ((rscreen->info.family >= CHIP_TONGA) && 421 (templ->max_references == 1) && 422 (rscreen->info.vce_harvest_config == 0)) 423 enc->dual_inst = true; 424 425 enc->base = *templ; 426 enc->base.context = context; 427 428 enc->base.destroy = rvce_destroy; 429 enc->base.begin_frame = rvce_begin_frame; 430 enc->base.encode_bitstream = rvce_encode_bitstream; 431 enc->base.end_frame = rvce_end_frame; 432 enc->base.flush = rvce_flush; 433 enc->base.get_feedback = rvce_get_feedback; 434 enc->get_buffer = get_buffer; 435 436 enc->screen = context->screen; 437 enc->ws = ws; 438 enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc); 439 if (!enc->cs) { 440 RVID_ERR("Can't get command submission context.\n"); 441 goto error; 442 } 443 444 templat.buffer_format = PIPE_FORMAT_NV12; 445 templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420; 446 templat.width = enc->base.width; 447 templat.height = enc->base.height; 448 templat.interlaced = false; 449 if (!(tmp_buf = context->create_video_buffer(context, &templat))) { 450 RVID_ERR("Can't create video buffer.\n"); 451 goto error; 452 } 453 454 enc->cpb_num = get_cpb_num(enc); 455 if (!enc->cpb_num) 456 goto error; 457 458 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf); 459 cpb_size = align(tmp_surf->level[0].nblk_x * tmp_surf->bpe, 128); 460 cpb_size = cpb_size * align(tmp_surf->level[0].nblk_y, 32); 461 cpb_size = cpb_size * 3 / 2; 462 cpb_size = cpb_size * enc->cpb_num; 463 if (enc->dual_pipe) 464 cpb_size += RVCE_MAX_AUX_BUFFER_NUM * 465 RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2; 466 tmp_buf->destroy(tmp_buf); 467 if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { 468 RVID_ERR("Can't create CPB buffer.\n"); 469 goto error; 470 } 471 472 enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot)); 473 if (!enc->cpb_array) 474 goto error; 475 476 reset_cpb(enc); 477 478 switch (rscreen->info.vce_fw_version) { 479 case FW_40_2_2: 480 radeon_vce_40_2_2_init(enc); 481 get_pic_param = radeon_vce_40_2_2_get_param; 482 break; 483 484 case FW_50_0_1: 485 case FW_50_1_2: 486 case FW_50_10_2: 487 case FW_50_17_3: 488 radeon_vce_50_init(enc); 489 get_pic_param = radeon_vce_50_get_param; 490 break; 491 492 case FW_52_0_3: 493 case FW_52_4_3: 494 case FW_52_8_3: 495 radeon_vce_52_init(enc); 496 get_pic_param = radeon_vce_52_get_param; 497 break; 498 499 default: 500 goto error; 501 } 502 503 return &enc->base; 504 505error: 506 if (enc->cs) 507 enc->ws->cs_destroy(enc->cs); 508 509 rvid_destroy_buffer(&enc->cpb); 510 511 FREE(enc->cpb_array); 512 FREE(enc); 513 return NULL; 514} 515 516/** 517 * check if kernel has the right fw version loaded 518 */ 519bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen) 520{ 521 switch (rscreen->info.vce_fw_version) { 522 case FW_40_2_2: 523 case FW_50_0_1: 524 case FW_50_1_2: 525 case FW_50_10_2: 526 case FW_50_17_3: 527 case FW_52_0_3: 528 case FW_52_4_3: 529 case FW_52_8_3: 530 return true; 531 default: 532 return false; 533 } 534} 535 536/** 537 * Add the buffer as relocation to the current command submission 538 */ 539void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, 540 enum radeon_bo_usage usage, enum radeon_bo_domain domain, 541 signed offset) 542{ 543 int reloc_idx; 544 545 reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, 546 domain, RADEON_PRIO_VCE); 547 if (enc->use_vm) { 548 uint64_t addr; 549 addr = enc->ws->buffer_get_virtual_address(buf); 550 addr = addr + offset; 551 RVCE_CS(addr >> 32); 552 RVCE_CS(addr); 553 } else { 554 offset += enc->ws->buffer_get_reloc_offset(buf); 555 RVCE_CS(reloc_idx * 4); 556 RVCE_CS(offset); 557 } 558} 559