1/************************************************************************** 2 * 3 * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#ifndef __VMWGFX_DRM_H__ 29#define __VMWGFX_DRM_H__ 30 31#ifndef __KERNEL__ 32#include <drm.h> 33#endif 34 35#define DRM_VMW_MAX_SURFACE_FACES 6 36#define DRM_VMW_MAX_MIP_LEVELS 24 37 38 39#define DRM_VMW_GET_PARAM 0 40#define DRM_VMW_ALLOC_DMABUF 1 41#define DRM_VMW_UNREF_DMABUF 2 42#define DRM_VMW_CURSOR_BYPASS 3 43/* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/ 44#define DRM_VMW_CONTROL_STREAM 4 45#define DRM_VMW_CLAIM_STREAM 5 46#define DRM_VMW_UNREF_STREAM 6 47/* guarded by DRM_VMW_PARAM_3D == 1 */ 48#define DRM_VMW_CREATE_CONTEXT 7 49#define DRM_VMW_UNREF_CONTEXT 8 50#define DRM_VMW_CREATE_SURFACE 9 51#define DRM_VMW_UNREF_SURFACE 10 52#define DRM_VMW_REF_SURFACE 11 53#define DRM_VMW_EXECBUF 12 54#define DRM_VMW_GET_3D_CAP 13 55#define DRM_VMW_FENCE_WAIT 14 56#define DRM_VMW_FENCE_SIGNALED 15 57#define DRM_VMW_FENCE_UNREF 16 58#define DRM_VMW_FENCE_EVENT 17 59#define DRM_VMW_PRESENT 18 60#define DRM_VMW_PRESENT_READBACK 19 61#define DRM_VMW_UPDATE_LAYOUT 20 62#define DRM_VMW_CREATE_SHADER 21 63#define DRM_VMW_UNREF_SHADER 22 64#define DRM_VMW_GB_SURFACE_CREATE 23 65#define DRM_VMW_GB_SURFACE_REF 24 66#define DRM_VMW_SYNCCPU 25 67#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 68 69/*************************************************************************/ 70/** 71 * DRM_VMW_GET_PARAM - get device information. 72 * 73 * DRM_VMW_PARAM_FIFO_OFFSET: 74 * Offset to use to map the first page of the FIFO read-only. 75 * The fifo is mapped using the mmap() system call on the drm device. 76 * 77 * DRM_VMW_PARAM_OVERLAY_IOCTL: 78 * Does the driver support the overlay ioctl. 79 */ 80 81#define DRM_VMW_PARAM_NUM_STREAMS 0 82#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 83#define DRM_VMW_PARAM_3D 2 84#define DRM_VMW_PARAM_HW_CAPS 3 85#define DRM_VMW_PARAM_FIFO_CAPS 4 86#define DRM_VMW_PARAM_MAX_FB_SIZE 5 87#define DRM_VMW_PARAM_FIFO_HW_VERSION 6 88#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 89#define DRM_VMW_PARAM_3D_CAPS_SIZE 8 90#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 91#define DRM_VMW_PARAM_MAX_MOB_SIZE 10 92#define DRM_VMW_PARAM_SCREEN_TARGET 11 93#define DRM_VMW_PARAM_VGPU10 12 94 95/** 96 * enum drm_vmw_handle_type - handle type for ref ioctls 97 * 98 */ 99enum drm_vmw_handle_type { 100 DRM_VMW_HANDLE_LEGACY = 0, 101 DRM_VMW_HANDLE_PRIME = 1 102}; 103 104/** 105 * struct drm_vmw_getparam_arg 106 * 107 * @value: Returned value. //Out 108 * @param: Parameter to query. //In. 109 * 110 * Argument to the DRM_VMW_GET_PARAM Ioctl. 111 */ 112 113struct drm_vmw_getparam_arg { 114 uint64_t value; 115 uint32_t param; 116 uint32_t pad64; 117}; 118 119/*************************************************************************/ 120/** 121 * DRM_VMW_CREATE_CONTEXT - Create a host context. 122 * 123 * Allocates a device unique context id, and queues a create context command 124 * for the host. Does not wait for host completion. 125 */ 126 127/** 128 * struct drm_vmw_context_arg 129 * 130 * @cid: Device unique context ID. 131 * 132 * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. 133 * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. 134 */ 135 136struct drm_vmw_context_arg { 137 int32_t cid; 138 uint32_t pad64; 139}; 140 141/*************************************************************************/ 142/** 143 * DRM_VMW_UNREF_CONTEXT - Create a host context. 144 * 145 * Frees a global context id, and queues a destroy host command for the host. 146 * Does not wait for host completion. The context ID can be used directly 147 * in the command stream and shows up as the same context ID on the host. 148 */ 149 150/*************************************************************************/ 151/** 152 * DRM_VMW_CREATE_SURFACE - Create a host suface. 153 * 154 * Allocates a device unique surface id, and queues a create surface command 155 * for the host. Does not wait for host completion. The surface ID can be 156 * used directly in the command stream and shows up as the same surface 157 * ID on the host. 158 */ 159 160/** 161 * struct drm_wmv_surface_create_req 162 * 163 * @flags: Surface flags as understood by the host. 164 * @format: Surface format as understood by the host. 165 * @mip_levels: Number of mip levels for each face. 166 * An unused face should have 0 encoded. 167 * @size_addr: Address of a user-space array of sruct drm_vmw_size 168 * cast to an uint64_t for 32-64 bit compatibility. 169 * The size of the array should equal the total number of mipmap levels. 170 * @shareable: Boolean whether other clients (as identified by file descriptors) 171 * may reference this surface. 172 * @scanout: Boolean whether the surface is intended to be used as a 173 * scanout. 174 * 175 * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. 176 * Output data from the DRM_VMW_REF_SURFACE Ioctl. 177 */ 178 179struct drm_vmw_surface_create_req { 180 uint32_t flags; 181 uint32_t format; 182 uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; 183 uint64_t size_addr; 184 int32_t shareable; 185 int32_t scanout; 186}; 187 188/** 189 * struct drm_wmv_surface_arg 190 * 191 * @sid: Surface id of created surface or surface to destroy or reference. 192 * @handle_type: Handle type for DRM_VMW_REF_SURFACE Ioctl. 193 * 194 * Output data from the DRM_VMW_CREATE_SURFACE Ioctl. 195 * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl. 196 * Input argument to the DRM_VMW_REF_SURFACE Ioctl. 197 */ 198 199struct drm_vmw_surface_arg { 200 int32_t sid; 201 enum drm_vmw_handle_type handle_type; 202}; 203 204/** 205 * struct drm_vmw_size ioctl. 206 * 207 * @width - mip level width 208 * @height - mip level height 209 * @depth - mip level depth 210 * 211 * Description of a mip level. 212 * Input data to the DRM_WMW_CREATE_SURFACE Ioctl. 213 */ 214 215struct drm_vmw_size { 216 uint32_t width; 217 uint32_t height; 218 uint32_t depth; 219 uint32_t pad64; 220}; 221 222/** 223 * union drm_vmw_surface_create_arg 224 * 225 * @rep: Output data as described above. 226 * @req: Input data as described above. 227 * 228 * Argument to the DRM_VMW_CREATE_SURFACE Ioctl. 229 */ 230 231union drm_vmw_surface_create_arg { 232 struct drm_vmw_surface_arg rep; 233 struct drm_vmw_surface_create_req req; 234}; 235 236/*************************************************************************/ 237/** 238 * DRM_VMW_REF_SURFACE - Reference a host surface. 239 * 240 * Puts a reference on a host surface with a give sid, as previously 241 * returned by the DRM_VMW_CREATE_SURFACE ioctl. 242 * A reference will make sure the surface isn't destroyed while we hold 243 * it and will allow the calling client to use the surface ID in the command 244 * stream. 245 * 246 * On successful return, the Ioctl returns the surface information given 247 * in the DRM_VMW_CREATE_SURFACE ioctl. 248 */ 249 250/** 251 * union drm_vmw_surface_reference_arg 252 * 253 * @rep: Output data as described above. 254 * @req: Input data as described above. 255 * 256 * Argument to the DRM_VMW_REF_SURFACE Ioctl. 257 */ 258 259union drm_vmw_surface_reference_arg { 260 struct drm_vmw_surface_create_req rep; 261 struct drm_vmw_surface_arg req; 262}; 263 264/*************************************************************************/ 265/** 266 * DRM_VMW_UNREF_SURFACE - Unreference a host surface. 267 * 268 * Clear a reference previously put on a host surface. 269 * When all references are gone, including the one implicitly placed 270 * on creation, 271 * a destroy surface command will be queued for the host. 272 * Does not wait for completion. 273 */ 274 275/*************************************************************************/ 276/** 277 * DRM_VMW_EXECBUF 278 * 279 * Submit a command buffer for execution on the host, and return a 280 * fence seqno that when signaled, indicates that the command buffer has 281 * executed. 282 */ 283 284/** 285 * struct drm_vmw_execbuf_arg 286 * 287 * @commands: User-space address of a command buffer cast to an uint64_t. 288 * @command-size: Size in bytes of the command buffer. 289 * @throttle-us: Sleep until software is less than @throttle_us 290 * microseconds ahead of hardware. The driver may round this value 291 * to the nearest kernel tick. 292 * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an 293 * uint64_t. 294 * @version: Allows expanding the execbuf ioctl parameters without breaking 295 * backwards compatibility, since user-space will always tell the kernel 296 * which version it uses. 297 * @flags: Execbuf flags. None currently. 298 * 299 * Argument to the DRM_VMW_EXECBUF Ioctl. 300 */ 301 302#define DRM_VMW_EXECBUF_VERSION 2 303 304struct drm_vmw_execbuf_arg { 305 uint64_t commands; 306 uint32_t command_size; 307 uint32_t throttle_us; 308 uint64_t fence_rep; 309 uint32_t version; 310 uint32_t flags; 311 uint32_t context_handle; 312 uint32_t pad64; 313}; 314 315/** 316 * struct drm_vmw_fence_rep 317 * 318 * @handle: Fence object handle for fence associated with a command submission. 319 * @mask: Fence flags relevant for this fence object. 320 * @seqno: Fence sequence number in fifo. A fence object with a lower 321 * seqno will signal the EXEC flag before a fence object with a higher 322 * seqno. This can be used by user-space to avoid kernel calls to determine 323 * whether a fence has signaled the EXEC flag. Note that @seqno will 324 * wrap at 32-bit. 325 * @passed_seqno: The highest seqno number processed by the hardware 326 * so far. This can be used to mark user-space fence objects as signaled, and 327 * to determine whether a fence seqno might be stale. 328 * @error: This member should've been set to -EFAULT on submission. 329 * The following actions should be take on completion: 330 * error == -EFAULT: Fence communication failed. The host is synchronized. 331 * Use the last fence id read from the FIFO fence register. 332 * error != 0 && error != -EFAULT: 333 * Fence submission failed. The host is synchronized. Use the fence_seq member. 334 * error == 0: All is OK, The host may not be synchronized. 335 * Use the fence_seq member. 336 * 337 * Input / Output data to the DRM_VMW_EXECBUF Ioctl. 338 */ 339 340struct drm_vmw_fence_rep { 341 uint32_t handle; 342 uint32_t mask; 343 uint32_t seqno; 344 uint32_t passed_seqno; 345 uint32_t pad64; 346 int32_t error; 347}; 348 349/*************************************************************************/ 350/** 351 * DRM_VMW_ALLOC_DMABUF 352 * 353 * Allocate a DMA buffer that is visible also to the host. 354 * NOTE: The buffer is 355 * identified by a handle and an offset, which are private to the guest, but 356 * useable in the command stream. The guest kernel may translate these 357 * and patch up the command stream accordingly. In the future, the offset may 358 * be zero at all times, or it may disappear from the interface before it is 359 * fixed. 360 * 361 * The DMA buffer may stay user-space mapped in the guest at all times, 362 * and is thus suitable for sub-allocation. 363 * 364 * DMA buffers are mapped using the mmap() syscall on the drm device. 365 */ 366 367/** 368 * struct drm_vmw_alloc_dmabuf_req 369 * 370 * @size: Required minimum size of the buffer. 371 * 372 * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl. 373 */ 374 375struct drm_vmw_alloc_dmabuf_req { 376 uint32_t size; 377 uint32_t pad64; 378}; 379 380/** 381 * struct drm_vmw_dmabuf_rep 382 * 383 * @map_handle: Offset to use in the mmap() call used to map the buffer. 384 * @handle: Handle unique to this buffer. Used for unreferencing. 385 * @cur_gmr_id: GMR id to use in the command stream when this buffer is 386 * referenced. See not above. 387 * @cur_gmr_offset: Offset to use in the command stream when this buffer is 388 * referenced. See note above. 389 * 390 * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl. 391 */ 392 393struct drm_vmw_dmabuf_rep { 394 uint64_t map_handle; 395 uint32_t handle; 396 uint32_t cur_gmr_id; 397 uint32_t cur_gmr_offset; 398 uint32_t pad64; 399}; 400 401/** 402 * union drm_vmw_dmabuf_arg 403 * 404 * @req: Input data as described above. 405 * @rep: Output data as described above. 406 * 407 * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl. 408 */ 409 410union drm_vmw_alloc_dmabuf_arg { 411 struct drm_vmw_alloc_dmabuf_req req; 412 struct drm_vmw_dmabuf_rep rep; 413}; 414 415/*************************************************************************/ 416/** 417 * DRM_VMW_UNREF_DMABUF - Free a DMA buffer. 418 * 419 */ 420 421/** 422 * struct drm_vmw_unref_dmabuf_arg 423 * 424 * @handle: Handle indicating what buffer to free. Obtained from the 425 * DRM_VMW_ALLOC_DMABUF Ioctl. 426 * 427 * Argument to the DRM_VMW_UNREF_DMABUF Ioctl. 428 */ 429 430struct drm_vmw_unref_dmabuf_arg { 431 uint32_t handle; 432 uint32_t pad64; 433}; 434 435/*************************************************************************/ 436/** 437 * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams. 438 * 439 * This IOCTL controls the overlay units of the svga device. 440 * The SVGA overlay units does not work like regular hardware units in 441 * that they do not automaticaly read back the contents of the given dma 442 * buffer. But instead only read back for each call to this ioctl, and 443 * at any point between this call being made and a following call that 444 * either changes the buffer or disables the stream. 445 */ 446 447/** 448 * struct drm_vmw_rect 449 * 450 * Defines a rectangle. Used in the overlay ioctl to define 451 * source and destination rectangle. 452 */ 453 454struct drm_vmw_rect { 455 int32_t x; 456 int32_t y; 457 uint32_t w; 458 uint32_t h; 459}; 460 461/** 462 * struct drm_vmw_control_stream_arg 463 * 464 * @stream_id: Stearm to control 465 * @enabled: If false all following arguments are ignored. 466 * @handle: Handle to buffer for getting data from. 467 * @format: Format of the overlay as understood by the host. 468 * @width: Width of the overlay. 469 * @height: Height of the overlay. 470 * @size: Size of the overlay in bytes. 471 * @pitch: Array of pitches, the two last are only used for YUV12 formats. 472 * @offset: Offset from start of dma buffer to overlay. 473 * @src: Source rect, must be within the defined area above. 474 * @dst: Destination rect, x and y may be negative. 475 * 476 * Argument to the DRM_VMW_CONTROL_STREAM Ioctl. 477 */ 478 479struct drm_vmw_control_stream_arg { 480 uint32_t stream_id; 481 uint32_t enabled; 482 483 uint32_t flags; 484 uint32_t color_key; 485 486 uint32_t handle; 487 uint32_t offset; 488 int32_t format; 489 uint32_t size; 490 uint32_t width; 491 uint32_t height; 492 uint32_t pitch[3]; 493 494 uint32_t pad64; 495 struct drm_vmw_rect src; 496 struct drm_vmw_rect dst; 497}; 498 499/*************************************************************************/ 500/** 501 * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass. 502 * 503 */ 504 505#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) 506#define DRM_VMW_CURSOR_BYPASS_FLAGS (1) 507 508/** 509 * struct drm_vmw_cursor_bypass_arg 510 * 511 * @flags: Flags. 512 * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed. 513 * @xpos: X position of cursor. 514 * @ypos: Y position of cursor. 515 * @xhot: X hotspot. 516 * @yhot: Y hotspot. 517 * 518 * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl. 519 */ 520 521struct drm_vmw_cursor_bypass_arg { 522 uint32_t flags; 523 uint32_t crtc_id; 524 int32_t xpos; 525 int32_t ypos; 526 int32_t xhot; 527 int32_t yhot; 528}; 529 530/*************************************************************************/ 531/** 532 * DRM_VMW_CLAIM_STREAM - Claim a single stream. 533 */ 534 535/** 536 * struct drm_vmw_context_arg 537 * 538 * @stream_id: Device unique context ID. 539 * 540 * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. 541 * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. 542 */ 543 544struct drm_vmw_stream_arg { 545 uint32_t stream_id; 546 uint32_t pad64; 547}; 548 549/*************************************************************************/ 550/** 551 * DRM_VMW_UNREF_STREAM - Unclaim a stream. 552 * 553 * Return a single stream that was claimed by this process. Also makes 554 * sure that the stream has been stopped. 555 */ 556 557/*************************************************************************/ 558/** 559 * DRM_VMW_GET_3D_CAP 560 * 561 * Read 3D capabilities from the FIFO 562 * 563 */ 564 565/** 566 * struct drm_vmw_get_3d_cap_arg 567 * 568 * @buffer: Pointer to a buffer for capability data, cast to an uint64_t 569 * @size: Max size to copy 570 * 571 * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL 572 * ioctls. 573 */ 574 575struct drm_vmw_get_3d_cap_arg { 576 uint64_t buffer; 577 uint32_t max_size; 578 uint32_t pad64; 579}; 580 581 582/*************************************************************************/ 583/** 584 * DRM_VMW_FENCE_WAIT 585 * 586 * Waits for a fence object to signal. The wait is interruptible, so that 587 * signals may be delivered during the interrupt. The wait may timeout, 588 * in which case the calls returns -EBUSY. If the wait is restarted, 589 * that is restarting without resetting @cookie_valid to zero, 590 * the timeout is computed from the first call. 591 * 592 * The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait 593 * on: 594 * DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command 595 * stream 596 * have executed. 597 * DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish 598 * commands 599 * in the buffer given to the EXECBUF ioctl returning the fence object handle 600 * are available to user-space. 601 * 602 * DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the 603 * fenc wait ioctl returns 0, the fence object has been unreferenced after 604 * the wait. 605 */ 606 607#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) 608#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) 609 610#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) 611 612/** 613 * struct drm_vmw_fence_wait_arg 614 * 615 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. 616 * @cookie_valid: Must be reset to 0 on first call. Left alone on restart. 617 * @kernel_cookie: Set to 0 on first call. Left alone on restart. 618 * @timeout_us: Wait timeout in microseconds. 0 for indefinite timeout. 619 * @lazy: Set to 1 if timing is not critical. Allow more than a kernel tick 620 * before returning. 621 * @flags: Fence flags to wait on. 622 * @wait_options: Options that control the behaviour of the wait ioctl. 623 * 624 * Input argument to the DRM_VMW_FENCE_WAIT ioctl. 625 */ 626 627struct drm_vmw_fence_wait_arg { 628 uint32_t handle; 629 int32_t cookie_valid; 630 uint64_t kernel_cookie; 631 uint64_t timeout_us; 632 int32_t lazy; 633 int32_t flags; 634 int32_t wait_options; 635 int32_t pad64; 636}; 637 638/*************************************************************************/ 639/** 640 * DRM_VMW_FENCE_SIGNALED 641 * 642 * Checks if a fence object is signaled.. 643 */ 644 645/** 646 * struct drm_vmw_fence_signaled_arg 647 * 648 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. 649 * @flags: Fence object flags input to DRM_VMW_FENCE_SIGNALED ioctl 650 * @signaled: Out: Flags signaled. 651 * @sequence: Out: Highest sequence passed so far. Can be used to signal the 652 * EXEC flag of user-space fence objects. 653 * 654 * Input/Output argument to the DRM_VMW_FENCE_SIGNALED and DRM_VMW_FENCE_UNREF 655 * ioctls. 656 */ 657 658struct drm_vmw_fence_signaled_arg { 659 uint32_t handle; 660 uint32_t flags; 661 int32_t signaled; 662 uint32_t passed_seqno; 663 uint32_t signaled_flags; 664 uint32_t pad64; 665}; 666 667/*************************************************************************/ 668/** 669 * DRM_VMW_FENCE_UNREF 670 * 671 * Unreferences a fence object, and causes it to be destroyed if there are no 672 * other references to it. 673 * 674 */ 675 676/** 677 * struct drm_vmw_fence_arg 678 * 679 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. 680 * 681 * Input/Output argument to the DRM_VMW_FENCE_UNREF ioctl.. 682 */ 683 684struct drm_vmw_fence_arg { 685 uint32_t handle; 686 uint32_t pad64; 687}; 688 689 690/*************************************************************************/ 691/** 692 * DRM_VMW_FENCE_EVENT 693 * 694 * Queues an event on a fence to be delivered on the drm character device 695 * when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag. 696 * Optionally the approximate time when the fence signaled is 697 * given by the event. 698 */ 699 700/* 701 * The event type 702 */ 703#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 704 705struct drm_vmw_event_fence { 706 struct drm_event base; 707 uint64_t user_data; 708 uint32_t tv_sec; 709 uint32_t tv_usec; 710}; 711 712/* 713 * Flags that may be given to the command. 714 */ 715/* Request fence signaled time on the event. */ 716#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) 717 718/** 719 * struct drm_vmw_fence_event_arg 720 * 721 * @fence_rep: Pointer to fence_rep structure cast to uint64_t or 0 if 722 * the fence is not supposed to be referenced by user-space. 723 * @user_info: Info to be delivered with the event. 724 * @handle: Attach the event to this fence only. 725 * @flags: A set of flags as defined above. 726 */ 727struct drm_vmw_fence_event_arg { 728 uint64_t fence_rep; 729 uint64_t user_data; 730 uint32_t handle; 731 uint32_t flags; 732}; 733 734 735/*************************************************************************/ 736/** 737 * DRM_VMW_PRESENT 738 * 739 * Executes an SVGA present on a given fb for a given surface. The surface 740 * is placed on the framebuffer. Cliprects are given relative to the given 741 * point (the point disignated by dest_{x|y}). 742 * 743 */ 744 745/** 746 * struct drm_vmw_present_arg 747 * @fb_id: framebuffer id to present / read back from. 748 * @sid: Surface id to present from. 749 * @dest_x: X placement coordinate for surface. 750 * @dest_y: Y placement coordinate for surface. 751 * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. 752 * @num_clips: Number of cliprects given relative to the framebuffer origin, 753 * in the same coordinate space as the frame buffer. 754 * @pad64: Unused 64-bit padding. 755 * 756 * Input argument to the DRM_VMW_PRESENT ioctl. 757 */ 758 759struct drm_vmw_present_arg { 760 uint32_t fb_id; 761 uint32_t sid; 762 int32_t dest_x; 763 int32_t dest_y; 764 uint64_t clips_ptr; 765 uint32_t num_clips; 766 uint32_t pad64; 767}; 768 769 770/*************************************************************************/ 771/** 772 * DRM_VMW_PRESENT_READBACK 773 * 774 * Executes an SVGA present readback from a given fb to the dma buffer 775 * currently bound as the fb. If there is no dma buffer bound to the fb, 776 * an error will be returned. 777 * 778 */ 779 780/** 781 * struct drm_vmw_present_arg 782 * @fb_id: fb_id to present / read back from. 783 * @num_clips: Number of cliprects. 784 * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. 785 * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an uint64_t. 786 * If this member is NULL, then the ioctl should not return a fence. 787 */ 788 789struct drm_vmw_present_readback_arg { 790 uint32_t fb_id; 791 uint32_t num_clips; 792 uint64_t clips_ptr; 793 uint64_t fence_rep; 794}; 795 796/*************************************************************************/ 797/** 798 * DRM_VMW_UPDATE_LAYOUT - Update layout 799 * 800 * Updates the preferred modes and connection status for connectors. The 801 * command consists of one drm_vmw_update_layout_arg pointing to an array 802 * of num_outputs drm_vmw_rect's. 803 */ 804 805/** 806 * struct drm_vmw_update_layout_arg 807 * 808 * @num_outputs: number of active connectors 809 * @rects: pointer to array of drm_vmw_rect cast to an uint64_t 810 * 811 * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. 812 */ 813struct drm_vmw_update_layout_arg { 814 uint32_t num_outputs; 815 uint32_t pad64; 816 uint64_t rects; 817}; 818 819 820/*************************************************************************/ 821/** 822 * DRM_VMW_CREATE_SHADER - Create shader 823 * 824 * Creates a shader and optionally binds it to a dma buffer containing 825 * the shader byte-code. 826 */ 827 828/** 829 * enum drm_vmw_shader_type - Shader types 830 */ 831enum drm_vmw_shader_type { 832 drm_vmw_shader_type_vs = 0, 833 drm_vmw_shader_type_ps, 834}; 835 836 837/** 838 * struct drm_vmw_shader_create_arg 839 * 840 * @shader_type: Shader type of the shader to create. 841 * @size: Size of the byte-code in bytes. 842 * where the shader byte-code starts 843 * @buffer_handle: Buffer handle identifying the buffer containing the 844 * shader byte-code 845 * @shader_handle: On successful completion contains a handle that 846 * can be used to subsequently identify the shader. 847 * @offset: Offset in bytes into the buffer given by @buffer_handle, 848 * 849 * Input / Output argument to the DRM_VMW_CREATE_SHADER Ioctl. 850 */ 851struct drm_vmw_shader_create_arg { 852 enum drm_vmw_shader_type shader_type; 853 uint32_t size; 854 uint32_t buffer_handle; 855 uint32_t shader_handle; 856 uint64_t offset; 857}; 858 859/*************************************************************************/ 860/** 861 * DRM_VMW_UNREF_SHADER - Unreferences a shader 862 * 863 * Destroys a user-space reference to a shader, optionally destroying 864 * it. 865 */ 866 867/** 868 * struct drm_vmw_shader_arg 869 * 870 * @handle: Handle identifying the shader to destroy. 871 * 872 * Input argument to the DRM_VMW_UNREF_SHADER ioctl. 873 */ 874struct drm_vmw_shader_arg { 875 uint32_t handle; 876 uint32_t pad64; 877}; 878 879/*************************************************************************/ 880/** 881 * DRM_VMW_GB_SURFACE_CREATE - Create a host guest-backed surface. 882 * 883 * Allocates a surface handle and queues a create surface command 884 * for the host on the first use of the surface. The surface ID can 885 * be used as the surface ID in commands referencing the surface. 886 */ 887 888/** 889 * enum drm_vmw_surface_flags 890 * 891 * @drm_vmw_surface_flag_shareable: Whether the surface is shareable 892 * @drm_vmw_surface_flag_scanout: Whether the surface is a scanout 893 * surface. 894 * @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is 895 * given. 896 */ 897enum drm_vmw_surface_flags { 898 drm_vmw_surface_flag_shareable = (1 << 0), 899 drm_vmw_surface_flag_scanout = (1 << 1), 900 drm_vmw_surface_flag_create_buffer = (1 << 2) 901}; 902 903/** 904 * struct drm_vmw_gb_surface_create_req 905 * 906 * @svga3d_flags: SVGA3d surface flags for the device. 907 * @format: SVGA3d format. 908 * @mip_level: Number of mip levels for all faces. 909 * @drm_surface_flags Flags as described above. 910 * @multisample_count Future use. Set to 0. 911 * @autogen_filter Future use. Set to 0. 912 * @buffer_handle Buffer handle of backup buffer. SVGA3D_INVALID_ID 913 * if none. 914 * @base_size Size of the base mip level for all faces. 915 * @array_size Must be zero for non-vgpu10 hardware, and if non-zero 916 * svga3d_flags must have proper bind flags setup. 917 * 918 * Input argument to the DRM_VMW_GB_SURFACE_CREATE Ioctl. 919 * Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl. 920 */ 921struct drm_vmw_gb_surface_create_req { 922 uint32_t svga3d_flags; 923 uint32_t format; 924 uint32_t mip_levels; 925 enum drm_vmw_surface_flags drm_surface_flags; 926 uint32_t multisample_count; 927 uint32_t autogen_filter; 928 uint32_t buffer_handle; 929 uint32_t array_size; 930 struct drm_vmw_size base_size; 931}; 932 933/** 934 * struct drm_vmw_gb_surface_create_rep 935 * 936 * @handle: Surface handle. 937 * @backup_size: Size of backup buffers for this surface. 938 * @buffer_handle: Handle of backup buffer. SVGA3D_INVALID_ID if none. 939 * @buffer_size: Actual size of the buffer identified by 940 * @buffer_handle 941 * @buffer_map_handle: Offset into device address space for the buffer 942 * identified by @buffer_handle. 943 * 944 * Part of output argument for the DRM_VMW_GB_SURFACE_REF ioctl. 945 * Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl. 946 */ 947struct drm_vmw_gb_surface_create_rep { 948 uint32_t handle; 949 uint32_t backup_size; 950 uint32_t buffer_handle; 951 uint32_t buffer_size; 952 uint64_t buffer_map_handle; 953}; 954 955/** 956 * union drm_vmw_gb_surface_create_arg 957 * 958 * @req: Input argument as described above. 959 * @rep: Output argument as described above. 960 * 961 * Argument to the DRM_VMW_GB_SURFACE_CREATE ioctl. 962 */ 963union drm_vmw_gb_surface_create_arg { 964 struct drm_vmw_gb_surface_create_rep rep; 965 struct drm_vmw_gb_surface_create_req req; 966}; 967 968/*************************************************************************/ 969/** 970 * DRM_VMW_GB_SURFACE_REF - Reference a host surface. 971 * 972 * Puts a reference on a host surface with a given handle, as previously 973 * returned by the DRM_VMW_GB_SURFACE_CREATE ioctl. 974 * A reference will make sure the surface isn't destroyed while we hold 975 * it and will allow the calling client to use the surface handle in 976 * the command stream. 977 * 978 * On successful return, the Ioctl returns the surface information given 979 * to and returned from the DRM_VMW_GB_SURFACE_CREATE ioctl. 980 */ 981 982/** 983 * struct drm_vmw_gb_surface_reference_arg 984 * 985 * @creq: The data used as input when the surface was created, as described 986 * above at "struct drm_vmw_gb_surface_create_req" 987 * @crep: Additional data output when the surface was created, as described 988 * above at "struct drm_vmw_gb_surface_create_rep" 989 * 990 * Output Argument to the DRM_VMW_GB_SURFACE_REF ioctl. 991 */ 992struct drm_vmw_gb_surface_ref_rep { 993 struct drm_vmw_gb_surface_create_req creq; 994 struct drm_vmw_gb_surface_create_rep crep; 995}; 996 997/** 998 * union drm_vmw_gb_surface_reference_arg 999 * 1000 * @req: Input data as described above at "struct drm_vmw_surface_arg" 1001 * @rep: Output data as described above at "struct drm_vmw_gb_surface_ref_rep" 1002 * 1003 * Argument to the DRM_VMW_GB_SURFACE_REF Ioctl. 1004 */ 1005union drm_vmw_gb_surface_reference_arg { 1006 struct drm_vmw_gb_surface_ref_rep rep; 1007 struct drm_vmw_surface_arg req; 1008}; 1009 1010 1011/*************************************************************************/ 1012/** 1013 * DRM_VMW_SYNCCPU - Sync a DMA buffer / MOB for CPU access. 1014 * 1015 * Idles any previously submitted GPU operations on the buffer and 1016 * by default blocks command submissions that reference the buffer. 1017 * If the file descriptor used to grab a blocking CPU sync is closed, the 1018 * cpu sync is released. 1019 * The flags argument indicates how the grab / release operation should be 1020 * performed: 1021 */ 1022 1023/** 1024 * enum drm_vmw_synccpu_flags - Synccpu flags: 1025 * 1026 * @drm_vmw_synccpu_read: Sync for read. If sync is done for read only, it's a 1027 * hint to the kernel to allow command submissions that references the buffer 1028 * for read-only. 1029 * @drm_vmw_synccpu_write: Sync for write. Block all command submissions 1030 * referencing this buffer. 1031 * @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return 1032 * -EBUSY should the buffer be busy. 1033 * @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer 1034 * while the buffer is synced for CPU. This is similar to the GEM bo idle 1035 * behavior. 1036 */ 1037enum drm_vmw_synccpu_flags { 1038 drm_vmw_synccpu_read = (1 << 0), 1039 drm_vmw_synccpu_write = (1 << 1), 1040 drm_vmw_synccpu_dontblock = (1 << 2), 1041 drm_vmw_synccpu_allow_cs = (1 << 3) 1042}; 1043 1044/** 1045 * enum drm_vmw_synccpu_op - Synccpu operations: 1046 * 1047 * @drm_vmw_synccpu_grab: Grab the buffer for CPU operations 1048 * @drm_vmw_synccpu_release: Release a previous grab. 1049 */ 1050enum drm_vmw_synccpu_op { 1051 drm_vmw_synccpu_grab, 1052 drm_vmw_synccpu_release 1053}; 1054 1055/** 1056 * struct drm_vmw_synccpu_arg 1057 * 1058 * @op: The synccpu operation as described above. 1059 * @handle: Handle identifying the buffer object. 1060 * @flags: Flags as described above. 1061 */ 1062struct drm_vmw_synccpu_arg { 1063 enum drm_vmw_synccpu_op op; 1064 enum drm_vmw_synccpu_flags flags; 1065 uint32_t handle; 1066 uint32_t pad64; 1067}; 1068 1069/*************************************************************************/ 1070/** 1071 * DRM_VMW_CREATE_EXTENDED_CONTEXT - Create a host context. 1072 * 1073 * Allocates a device unique context id, and queues a create context command 1074 * for the host. Does not wait for host completion. 1075 */ 1076enum drm_vmw_extended_context { 1077 drm_vmw_context_legacy, 1078 drm_vmw_context_vgpu10 1079}; 1080 1081/** 1082 * union drm_vmw_extended_context_arg 1083 * 1084 * @req: Context type. 1085 * @rep: Context identifier. 1086 * 1087 * Argument to the DRM_VMW_CREATE_EXTENDED_CONTEXT Ioctl. 1088 */ 1089union drm_vmw_extended_context_arg { 1090 enum drm_vmw_extended_context req; 1091 struct drm_vmw_context_arg rep; 1092}; 1093#endif 1094