brw_shader.h revision 6980372010ad5929c0b4b0a0370d281cbd6f8b2e 
1/*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include <stdint.h>
25#include "brw_reg.h"
26#include "brw_defines.h"
27#include "brw_context.h"
28#include "main/compiler.h"
29#include "glsl/ir.h"
30#include "program/prog_parameter.h"
31
32#ifdef __cplusplus
33#include "brw_ir_allocator.h"
34#endif
35
36#pragma once
37
38#define MAX_SAMPLER_MESSAGE_SIZE 11
39#define MAX_VGRF_SIZE 16
40
41enum PACKED register_file {
42   BAD_FILE,
43   GRF,
44   MRF,
45   IMM,
46   HW_REG, /* a struct brw_reg */
47   ATTR,
48   UNIFORM, /* prog_data->params[reg] */
49};
50
51struct backend_reg
52{
53#ifdef __cplusplus
54   bool is_zero() const;
55   bool is_one() const;
56   bool is_negative_one() const;
57   bool is_null() const;
58   bool is_accumulator() const;
59   bool in_range(const backend_reg &r, unsigned n) const;
60#endif
61
62   enum register_file file; /**< Register file: GRF, MRF, IMM. */
63   enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
64
65   /**
66    * Register number.
67    *
68    * For GRF, it's a virtual register number until register allocation.
69    *
70    * For MRF, it's the hardware register.
71    */
72   uint16_t reg;
73
74   /**
75    * Offset within the virtual register.
76    *
77    * In the scalar backend, this is in units of a float per pixel for pre-
78    * register allocation registers (i.e., one register in SIMD8 mode and two
79    * registers in SIMD16 mode).
80    *
81    * For uniforms, this is in units of 1 float.
82    */
83   uint16_t reg_offset;
84
85   struct brw_reg fixed_hw_reg;
86
87   bool negate;
88   bool abs;
89};
90
91struct cfg_t;
92struct bblock_t;
93
94#ifdef __cplusplus
95struct backend_instruction : public exec_node {
96   bool is_3src() const;
97   bool is_tex() const;
98   bool is_math() const;
99   bool is_control_flow() const;
100   bool is_commutative() const;
101   bool can_do_source_mods() const;
102   bool can_do_saturate() const;
103   bool can_do_cmod() const;
104   bool reads_accumulator_implicitly() const;
105   bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
106
107   void remove(bblock_t *block);
108   void insert_after(bblock_t *block, backend_instruction *inst);
109   void insert_before(bblock_t *block, backend_instruction *inst);
110   void insert_before(bblock_t *block, exec_list *list);
111
112   /**
113    * True if the instruction has side effects other than writing to
114    * its destination registers.  You are expected not to reorder or
115    * optimize these out unless you know what you are doing.
116    */
117   bool has_side_effects() const;
118#else
119struct backend_instruction {
120   struct exec_node link;
121#endif
122   /** @{
123    * Annotation for the generated IR.  One of the two can be set.
124    */
125   const void *ir;
126   const char *annotation;
127   /** @} */
128
129   uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
130   uint8_t mlen; /**< SEND message length */
131   int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
132   uint8_t target; /**< MRT target. */
133   uint8_t regs_written; /**< Number of registers written by the instruction. */
134
135   enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
136   enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
137   enum brw_predicate predicate;
138   bool predicate_inverse:1;
139   bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
140   bool force_writemask_all:1;
141   bool no_dd_clear:1;
142   bool no_dd_check:1;
143   bool saturate:1;
144   bool shadow_compare:1;
145
146   /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
147    * mod and predication.
148    */
149   unsigned flag_subreg:1;
150
151   /** The number of hardware registers used for a message header. */
152   uint8_t header_size;
153};
154
155#ifdef __cplusplus
156
157enum instruction_scheduler_mode {
158   SCHEDULE_PRE,
159   SCHEDULE_PRE_NON_LIFO,
160   SCHEDULE_PRE_LIFO,
161   SCHEDULE_POST,
162};
163
164struct backend_shader {
165protected:
166
167   backend_shader(const struct brw_compiler *compiler,
168                  void *log_data,
169                  void *mem_ctx,
170                  const nir_shader *shader,
171                  struct brw_stage_prog_data *stage_prog_data);
172
173public:
174
175   const struct brw_compiler *compiler;
176   void *log_data; /* Passed to compiler->*_log functions */
177
178   const struct brw_device_info * const devinfo;
179   const nir_shader *nir;
180   struct brw_stage_prog_data * const stage_prog_data;
181
182   /** ralloc context for temporary data used during compile */
183   void *mem_ctx;
184
185   /**
186    * List of either fs_inst or vec4_instruction (inheriting from
187    * backend_instruction)
188    */
189   exec_list instructions;
190
191   cfg_t *cfg;
192
193   gl_shader_stage stage;
194   bool debug_enabled;
195   const char *stage_name;
196   const char *stage_abbrev;
197
198   brw::simple_allocator alloc;
199
200   virtual void dump_instruction(backend_instruction *inst) = 0;
201   virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
202   virtual void dump_instructions();
203   virtual void dump_instructions(const char *name);
204
205   void calculate_cfg();
206   void invalidate_cfg();
207
208   virtual void invalidate_live_intervals() = 0;
209};
210
211uint32_t brw_texture_offset(int *offsets, unsigned num_components);
212
213void brw_setup_image_uniform_values(gl_shader_stage stage,
214                                    struct brw_stage_prog_data *stage_prog_data,
215                                    unsigned param_start_index,
216                                    const gl_uniform_storage *storage);
217
218#else
219struct backend_shader;
220#endif /* __cplusplus */
221
222enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
223enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
224uint32_t brw_math_function(enum opcode op);
225const char *brw_instruction_name(enum opcode op);
226bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
227bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
228bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
229
230bool opt_predicated_break(struct backend_shader *s);
231
232#ifdef __cplusplus
233extern "C" {
234#endif
235
236struct brw_compiler *
237brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
238
239void
240brw_assign_common_binding_table_offsets(gl_shader_stage stage,
241                                        const struct brw_device_info *devinfo,
242                                        const struct gl_shader_program *shader_prog,
243                                        const struct gl_program *prog,
244                                        struct brw_stage_prog_data *stage_prog_data,
245                                        uint32_t next_binding_table_offset);
246
247bool brw_vs_precompile(struct gl_context *ctx,
248                       struct gl_shader_program *shader_prog,
249                       struct gl_program *prog);
250bool brw_gs_precompile(struct gl_context *ctx,
251                       struct gl_shader_program *shader_prog,
252                       struct gl_program *prog);
253bool brw_fs_precompile(struct gl_context *ctx,
254                       struct gl_shader_program *shader_prog,
255                       struct gl_program *prog);
256bool brw_cs_precompile(struct gl_context *ctx,
257                       struct gl_shader_program *shader_prog,
258                       struct gl_program *prog);
259
260int type_size_scalar(const struct glsl_type *type);
261int type_size_vec4(const struct glsl_type *type);
262
263bool is_scalar_shader_stage(const struct brw_compiler *compiler, int stage);
264
265#ifdef __cplusplus
266}
267#endif
268