| e6ae19944d977dc91bc45adff679337182c20683 |
|
24-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework gl_TessLevel*[] handling to use NIR compact arrays.
Treating everything as scalar arrays allows us to drop a bunch of
special case input/output munging all throughout the backend.
Instead, we just need to remap the TessLevel components to the
appropriate patch URB header locations in remap_patch_urb_offsets().
We also switch to treating the TES input versions of these as ordinary
shader inputs rather than system values, as remap_patch_urb_offsets()
just makes everything work out without special handling.
This regresses one Piglit test:
arb_tessellation_shader-large-uniforms/GL_TESS_CONTROL_SHADER-array-at-limit
The compiler starts promoting the constant arrays assigned to gl_TessLevel*
to uniform arrays. Since the shader also has a uniform array that uses
the maximum number of uniform components, this puts it over the uniform
component limit enforced by the linker. This is arguably a bug in the
constant array promotion code (it should avoid pushing us over limits),
but is unlikely to penalize any real application.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 6e3f6097c995a74d4ce52f542413b01ff819c203 |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: stop passing gl_shader_program to the precompile and codegen functions
We no longer need it.
While we are at it we mark the vs, gs, and wm codegen functions as static.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 9ca14f583c2613643671c1d5a8bd2b98745f4c7c |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: stop passing gl_shader_program to brw_assign_common_binding_table_offsets()
We now get everything we need directly from gl_program so there is
no need for this.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 945269ab7280b772807e573dfefc0b4f967ec522 |
|
25-Aug-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: move the group field from fs_inst to backend_instruction.
Just like the exec_size, we are going to need this in the vec4 backend
when we implement a simd splitting pass.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 9527a50da06f03885aad9e0f6d5693ced6c22bd4 |
|
25-Aug-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: move exec_size from fs_instruction to backend_instruction
We are going to need this in the vec4 backend too.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 4f2d1d6ea713df8f8d816b48b9e99c7117cf36d7 |
|
28-Nov-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
i965: support constant gather offsets larger than 4 bits
Offsets that don't fit into 4 bits need to force gather_po to be
selected. Adjust the logic so that this happens.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 3d2011cb33317b0fe9b8fe989916efc1841c6ce0 |
|
30-Jun-2016 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Refactor emission of atomic counter operations
This will make it easier to add more operations.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| fcd9d1badcd97486eea5d87bf701a3b0a16b4ba9 |
|
02-Sep-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/vec4: Drop backend_reg::in_range() in favor of regions_overlap().
This makes sure that overlap checks are done correctly throughout the
back-end when the '*this' register starts before the register/size
pair provided as argument, and is actually less annoying to use than
in_range() at this point since regions_overlap() takes its size
arguments in bytes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 27cb6b081eaffcf786686136f7961c4d78cc5586 |
|
04-Sep-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/ir: Drop backend_instruction::regs_written field.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 69570bbad876bb9da609c3b651aacda28cecc542 |
|
07-Sep-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/fs: Replace fs_inst::regs_written with ::size_written field in bytes.
The previous regs_written field can be recovered by rewriting each
rvalue reference of regs_written like 'x = i.regs_written' to 'x =
DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference
like 'i.regs_written = x' to 'i.size_written = x * reg_unit'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 9a523dd051fc06bfd89f32fcd85535d268472820 |
|
01-Sep-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/ir: Remove backend_reg::reg_offset.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 86944e063ad40cac0860bfd85a3cc4e9a9805aa3 |
|
01-Sep-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/fs: Replace fs_reg::reg_offset with fs_reg::offset expressed in bytes.
The fs_reg::offset field in byte units introduced in this patch is a
more straightforward alternative to the current register offset
representation split between fs_reg::reg_offset and ::subreg_offset.
The split representation makes it too easy to forget about one of the
offsets while dealing with the other, which has led to multiple
back-end bugs in the past. To make the matter worse the unit
reg_offset was expressed in was rather inconsistent, for uniforms it
would be expressed in either 4B or 16B units depending on the
back-end, and for most other things it would be expressed in 32B
units.
This encodes reg_offset as a new offset field expressed consistently
in byte units. Each rvalue reference of reg_offset in existing code
like 'x = r.reg_offset' is rewritten to 'x = r.offset / reg_unit', and
each lvalue reference like 'r.reg_offset = x' is rewritten to
'r.offset = r.offset % reg_unit + x * reg_unit'.
Because the change affects a lot of places and is rather non-trivial
to verify due to the inconsistent value of reg_unit, I've tried to
avoid making any additional changes other than applying the rewrite
rule above in order to keep the patch as simple as possible, sometimes
at the cost of introducing obvious stupidity (e.g. algebraic
expressions that could be simplified given some knowledge of the
context) -- I'll clean those up later on in a second pass.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 527f37199929932300acc1688d8160e1f3b1d753 |
|
23-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: s/brw_device_info/gen_device_info/
Generated by:
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 555b22a446362a2b0f9bae3c57cdaa330be89edb |
|
19-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move the type_size function declartaions to brw_nir.h
Signed-of-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 08705badfe136e1782e10472104323d861185357 |
|
01-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Allocate space in the binding table for non-coherent FB fetch.
Unfortunately due to the inconsistent meaning of some surface state
structure fields, we cannot re-use the same binding table entries for
sampling from and rendering into the same set of render buffers, so we
need to allocate a separate binding table block specifically for
render target reads if the non-coherent path is in use.
The slight noise is due to the change of
brw_assign_common_binding_table_offsets to return the next available
binding table index rather than void.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 09e46f99ad465ab253de3fc321f39062cfbe1984 |
|
19-Jul-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: bring back type_size_vec4_times_4()
We will use this for output varyings. To make component
packing simpler we will just treat all varyings as vec4s.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 1fb8c6df884c2a17cf980c4ea32db4c214903b55 |
|
30-Jun-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
glsl/mesa: split gl_shader in two
There are two distinctly different uses of this struct. The first
is to store GL shader objects. The second is to store information
about a shader stage thats been linked.
The two uses actually share few fields and there is clearly confusion
about their use. For example the linked shaders map one to one with
a program so can simply be destroyed along with the program. However
previously we were calling reference counting on the linked shaders.
We were also creating linked shaders with a name even though it
is always 0 and called the driver version of the _mesa_new_shader()
function unnecessarily for GL shader objects.
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 31dee99e052902bc08ddbb1009748dc982ac3211 |
|
05-Jun-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
mesa/glsl: stop using GL shader type internally
Instead use the internal gl_shader_stage enum everywhere. This
makes things more consistent and gets rid of unnecessary
conversions.
Ideally it would be nice to remove the Type field from gl_shader
altogether but currently it is used to differentiate between
gl_shader and gl_shader_program in the ShaderObjects hash table.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| a8a9d1bf41c00123cefb6e757f3509c62e880a15 |
|
14-Jun-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: remove type_size_vec4_times_4()
type_size_vec4_times_4() was introduced as a fix in 8dcf807cb43383
however since 3810c1561 we can just use type_size_scalar() and
get the actual number of outputs we need.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| e79aa19d88b4d6dbd26c23287292e6bf9f41ce33 |
|
20-May-2016 |
Juan A. Suarez Romero <jasuarez@igalia.com> |
i965: fix double-precision vertex inputs measurement
For double-precision vertex inputs we need to measure them in dvec4
terms, and for single-precision vertex inputs we need to measure them in
vec4 terms.
For the later case, we use type_size_vec4() function. For the former
case, we had a wrong implementation based on type_size_vec4().
This commit introduces a proper type_size_dvec4() function, that we use
to measure vertex inputs.
Measuring double-precision vertex inputs as dvec4 is required because
ARB_vertex_attrib_64bit states that these uses the same number of
locations than the single-precision version. That is, two consecutives
dvec4 would be located in location "x" and location "x+1", not "x+2".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| d6281a9d955ad97f993927bc214e4b641cfbe359 |
|
15-Apr-2016 |
Juan A. Suarez Romero <jasuarez@igalia.com> |
i965: take care of doubles when lowering VS inputs
Input attributes can require 2 vec4 or 1 vec4 depending on whether they
are double-precision or not.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 5310bca024f77da40ea6f4c275455f9cb0528f9e |
|
12-Nov-2015 |
Connor Abbott <connor.w.abbott@intel.com> |
i965: add brw_imm_df
v2 (Iago)
- Fixup accessibility in backend_reg
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| a808ba59657b3e5c6399e51fa1f4ebe9cad201a9 |
|
03-May-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework passthrough TCS checks.
According to Timothy, using program_string_id == 0 to identify the
passthrough TCS is going to be problematic for his shader cache work.
So, change it to strcmp() the name at visitor creation time.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 1cc7573162a7f0e8346d7abab50890c58a0dce9a |
|
28-Apr-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Pass devinfo pointer to is_3src() helpers.
This is not strictly required for the following changes because none
of the three-source opcodes we support at the moment in the compiler
back-end has been removed or redefined, but that's likely to change in
the future. In any case having hardware instructions specified as a
pair of hardware device and opcode number explicitly in all cases will
simplify the opcode look-up interface introduced in a subsequent
commit, since the opcode number alone is in general ambiguous.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| c55dc77ab13420a9fe0177ccd21a6b0a950d9113 |
|
28-Apr-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Pass devinfo pointer to brw_instruction_name().
A future series will implement support for an instruction that happens
to have the same opcode number as another instruction we support
already on a disjoint set of hardware generations. In order to
disambiguate which instruction it is brw_instruction_name() will need
some way to find out which device we are generating code for.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 501bedffa650c7d340d8f716736f6333c1317b34 |
|
11-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make a few tessellation related functions non-static.
Also, move them to brw_shader.cpp so they're in a location for code
used by both the vec4 and fs worlds.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 63250d8178dcbcf619423025e363c4f02f3bb6f9 |
|
09-Mar-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Remove useless IR self-destruct backend_shader method.
From the point it's constructed the CFG contains the only existing
copy of the program IR, and it never becomes invalid. Calling
backend_shader::invalidate_cfg would have destroyed the program
structure irrecoverably -- We weren't calling it at all for a good
reason.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 252d497d4c51f51c62283a4d6b9cf1dfab671219 |
|
21-Jan-2016 |
Matt Turner <mattst88@gmail.com> |
i965: Move brw_compiler_create() to new brw_compiler.c.
A future patch will want to use designated initalizers, which aren't
available in C++, but this is C.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 24be658d13b13fdb8a1977208038b4ba43bce4ac |
|
17-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation control shaders.
The TCS is the first tessellation shader stage, and the most
complicated. It has access to each of the control points in the input
patch, and computes a new output patch. There is one logical invocation
per output control point; all invocations run in parallel, and can
communicate by reading and writing output variables.
One of the main responsibilities of the TCS is to write the special
gl_TessLevelOuter[] and gl_TessLevelInner[] output variables which
control how much new geometry the hardware tessellation engine will
produce. Otherwise, it simply writes outputs that are passed along
to the TES.
We run in SIMD4x2 mode, handling two logical invocations per EU thread.
The hardware doesn't properly manage the dispatch mask for us; it always
initializes it to 0xFF. We wrap the whole program in an IF..ENDIF block
to handle an odd number of invocations, essentially falling back to
SIMD4x1 on the last thread.
v2: Update comments (requested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| a5038427c3624e559f954124d77304f9ae9b884c |
|
10-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation evaluation shaders
The TES is essentially a post-tessellator VS, which has access to the
entire TCS output patch, and a special gl_TessCoord input. Otherwise,
they're very straightforward.
This patch implements SIMD8 tessellation evaluation shaders for Gen8+.
The tessellator can generate a lot of geometry, so operating in SIMD8
mode (8 vertices per thread) is more efficient than SIMD4x2 mode (only
2 vertices per thread). I have another patch which implements SIMD4x2
mode for older hardware (or via an environment variable override).
We currently handle all inputs via the pull model.
v2: Improve comments (suggested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| f36993b46962eab4446bc1964eb47149751aee26 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Clean up #includes in the compiler.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 1eb11e64b3d0a0bc3f75e878f017aac4e826acf2 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Move brw_new_shader and brw_link_shader prototypes from brw_wm.h.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 2d8c5299032d229c8f6e936db5644cd53716e6c1 |
|
20-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Prevent implicit upcasts to brw_reg.
Now that backend_reg inherits from brw_reg, we have to be careful to
avoid the object slicing problem.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| f093c842e65b251e24ea3a2d6daaa91326a4f862 |
|
21-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Use implicit backend_reg copy-constructor.
In order to do this, we have to change the signature of the
backend_reg(brw_reg) constructor to take a reference to a brw_reg in
order to avoid unresolvable ambiguity about which constructor is
actually being called in the other modifications in this patch.
As far as I understand it, the rule in C++ is that if multiple
constructors are available for parent classes, the one closest to you in
the class heirarchy is closen, but if one of them didn't take a
reference, that screws things up.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 309a44d63c75a7d688157486b094e555f49c907d |
|
22-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Add and use backend_reg::equals().
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 44d6c0c805d2911cc5dfe853e5bc5a505f87775f |
|
12-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert scalar_* flags to a scalar_stage array.
I was going to add scalar_tcs and scalar_tes flags, and then thought
better of it and decided to convert this to an array. Simpler.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 49b3215d7076db8b9afe8998b01ef250795b5892 |
|
27-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Combine register file field.
The first four values (2-bits) are hardware values, and VGRF, ATTR, and
UNIFORM remain values used in the IR.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| b3315a6f56fb93f2884168cbf9358b2606641db5 |
|
27-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Replace HW_REG with ARF/FIXED_GRF.
HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to
look at different fields for type, abs, negate, writemask, swizzle, and
a second file. They also caused annoying problems like immediate sources
being considered scheduling barriers (commit 6148e94e2) and other such
nonsense.
Instead use ARF/FIXED_GRF/MRF for fixed registers in those files.
After a sufficient amount of time has passed since "GRF" was used, we
can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| b163aa01487ab5f9b22c48b7badc5d65999c4985 |
|
27-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Rename GRF to VGRF.
The 2-bit hardware register file field is ARF, GRF, MRF, IMM.
Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to
mean an assigned general purpose register.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 5a23b31c75556fa0fe9ca53db481bbec18c2baba |
|
30-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Move BAD_FILE from the beginning of enum register_file.
I'm going to begin using brw_reg's file field in backend_reg and its
derivatives, and in order to keep the hardware value for ARF as 0, we
have to do something different.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 7638e75cf99263c1ee8e31c6cc5a319feec2c943 |
|
26-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Use brw_reg's nr field to store register number.
In addition to combining another field, we get replace silliness like
"reg.reg" with something that actually makes sense, "reg.nr"; and no one
will ever wonder again why dst.reg isn't a dst_reg.
Moving the now 16-bit nr field to a 16-bit boundary decreases code size
by about 3k.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 94b1031703b1b5759436fe215323727cffce5f86 |
|
25-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Remove fixed_hw_reg field from backend_reg.
Since backend_reg now inherits brw_reg, we can use it in place of the
fixed_hw_reg field.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 182f137521f9c81f89a473ca5a411e6a7c531e19 |
|
25-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Delete type field from backend_reg.
Switching from an implicitly-sized type field to field with an explicit
bit width is safe because we have fewer than 2^4 types, and gcc will
warn if you attempt to set a value that will not fit.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 433df2e03c9a066bb2975bed28b57d6e2edf0aa9 |
|
24-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Delete abs/negate fields from backend_reg.
Instead use the ones provided by brw_reg. Also allows us to handle
HW_REGs in the negate() functions.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| c7ed5d1d1ca5d0e537cd5eb2cc8d4cae7ae73564 |
|
24-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Make backend_reg inherit from brw_reg.
Some fields (file, type, abs, negate) in brw_reg are shadowed by
backend_reg.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 8dcf807cb43383590ba193c7ff20b8a98e4a9f65 |
|
14-Oct-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix scalar VS float[] and vec2[] output arrays.
The scalar VS backend has never handled float[] and vec2[] outputs
correctly (my original code was broken). Outputs need to be padded
out to vec4 slots.
In fs_visitor::nir_setup_outputs(), we tried to process each vec4 slot
by looping from 0 to ALIGN(type_size_scalar(type), 4) / 4. However,
this is wrong: type_size_scalar() for a float[2] would return 2, or
for vec2[2] it would return 4. This looked like a single slot, even
though in reality each array element would be stored in separate vec4
slots.
Because of this bug, outputs[] and output_components[] would not get
initialized for the second element's VARYING_SLOT, which meant
emit_urb_writes() would skip writing them. Nothing used those values,
and dead code elimination threw a party.
To fix this, we introduce a new type_size_vec4_times_4() function which
pads array elements correctly, but still counts in scalar components,
generating correct indices in store_output intrinsics.
Normally, varying packing avoids this problem by turning varyings into
vec4s. So this doesn't actually fix any Piglit or dEQP tests today.
However, if varying packing is disabled, things would be broken.
Tessellation shaders can't use varying packing, so this fixes various
tcs-input Piglit tests on a branch of mine.
v2: Shorten the implementation of type_size_4x to a single line (caught
by Connor Abbott), and rename it to type_size_vec4_times_4()
(renaming suggested by Jason Ekstrand). Use type_size_vec4
rather than using type_size_vec4_times_4 and then dividing by 4.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 627c15cde46a76e9bce4425646c5caba11788ec4 |
|
20-Oct-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/fs: Disable CSE optimization for untyped & typed surface reads
An untyped surface read is volatile because it might be affected by a
write.
In the ES31-CTS.compute_shader.resources-max test, two back to back
read/modify/writes of an SSBO variable looked something like this:
r1 = untyped_surface_read(ssbo_float)
r2 = r1 + 1
untyped_surface_write(ssbo_float, r2)
r3 = untyped_surface_read(ssbo_float)
r4 = r3 + 1
untyped_surface_write(ssbo_float, r4)
And after CSE, we had:
r1 = untyped_surface_read(ssbo_float)
r2 = r1 + 1
untyped_surface_write(ssbo_float, r2)
r4 = r1 + 1
untyped_surface_write(ssbo_float, r4)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 0e57694745979286cda0cd414cc6d1f4efe5408b |
|
21-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/gs: Do prog_data setup and other calculations in brw_compile_gs
This commit moves the large pile of setup calculations we have to do for
geometry shaders out of brw_gs_emit and into brw_compile_gs. This has a
couple of nice implications. First, it's less work that the caller of
brw_compile_gs has to do. Second, it's consistent with the vertex and
fragment stages. Finally, it allows us to put brw_gs_compile back behind
the API boundary where it belongs.
v2 (Jason Ekstrand):
- Pull the changes to use nir info into a separate patch
- Put brw_gs_compile into brw_shader.h rather than brw_vec4_gs_visitor.h
so that we can use it for scalar GS.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 6980372010ad5929c0b4b0a0370d281cbd6f8b2e |
|
09-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move the entire compiler API into a single file
At this point, the compiler API has been substantially simplified. In the
spirit of Kristian's making a compiler library, this commit makes a single
header file that contains, more-or-less, the entire compiler API.
There's still a bit of cleanup to do particularly in the area of geometry
shaders. However, this gets us much closer to having a separate compiler.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 0ca401327ef9e280b3a8b008f1e41477afec3a35 |
|
06-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use a const nir_shader in backend_shader
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 4f33700f5ab6e69072318622651ea81639845ae9 |
|
05-Oct-2015 |
Kristian Høgsberg Kristensen <krh@bitplanet.net> |
i965: Move brw_link_shader() and friends to new file brw_link.cpp
We want to use the rest of brw_shader.cpp with the rest of the compiler
without pulling in the GLSL linking code.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 5a360dcad1fdb91f9129cb21775b9af60cbf57e4 |
|
03-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Generalize predicated break pass for use in vec4 backend.
instructions in affected programs: 44204 -> 43762 (-1.00%)
helped: 221
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| bf7b6fd3fd6d98305d64ee6224ca9f9e7ba48444 |
|
02-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/shader: Get rid of the shader, prog, and shader_prog fields
Unfortunately, we can't get rid of them entirely. The FS backend still
needs gl_program for handling TEXTURE_RECTANGLE. The GS vec4 backend still
needs gl_shader_program for handling transfom feedback. However, the VS
needs neither and we can substantially reduce the amount they are used.
One day we will be free from their tyranny.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 7926c3ea7d8f455cbee390d20c78dadf5432b9bc |
|
01-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/backend_shader: Add a field to store the NIR shader
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 28709e37d96d6b64753ca4dcce5fbfeb75f5b499 |
|
01-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/shader: Pull assign_common_binding_table_offsets out of backend_shader
This really has nothing to do with the backend compiler and we'd like to
eventually be able to set this up earlier in the compile process.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 3de81508ea513bf01f2c996c25a2cfdb5b3231d0 |
|
30-Sep-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/shader: Get rid of the setup_vec4_uniform_value helper
It's not used by anything anymore
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 58cea0c2b63db236e6efcae930c5fb936181c2a9 |
|
30-Sep-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/shader: Pull setup_image_uniform_values out of backend_shader
I tried to do this once before but Curro pointed out that having it in
backend_shader meant it could use the setup_vec4_uniform_values helper
which did different things in vec4 and fs. Now the setup_uniform_values
function differs only by an assert in the two backends so there's no real
good reason to be using it anymore.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 640c472fd075814972b1276c5b0ed3a769aacda5 |
|
12-Aug-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move type_size() methods out of visitor classes.
I want to use C function pointers to these, and they don't use anything
in the visitor classes anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| c56899f41a904762225267cb9c543a0abd901ad5 |
|
19-Aug-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Make setup_vec4_uniform_value and _image_uniform_values take an offset
This way they don't implicitly increment the uniforms variable and don't
have to be called in-sequence during uniform setup.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 8d8b8f58540abbdb8a006a38830a08346a0edf34 |
|
19-Aug-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Rename setup_vector_uniform_values to setup_vec4_uniform_value
The new name more accurately represents what it does: Set up a single vec4
uniform value.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 4af27145fe2fec6586ce95e80a76cdcbfe933db1 |
|
05-May-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Implement logic to set up and upload an image uniform.
v2: Move the image_params array back to brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| a0c02d2bbb765b0e997ad524d8e51838e529d9c0 |
|
28-Jun-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define the setup_vector_uniform_values() backend_visitor interface.
This cleans up the VEC4 implementation of setup_uniform_values()
somewhat and will avoid duplication of the image uniform upload code
by having a common interface to upload a vector of uniforms on either
back-end.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 40801295d5a3d747661abb1e2ca64d44c0e3dc05 |
|
23-Jun-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Remove the brw_context from the visitors
As of this commit, nothing actually needs the brw_context.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 6e255a3299c9ec5208cb5519b5da2edb0ce2972b |
|
17-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Add compiler options to brw_compiler
This creates the options at screen cration time and then we just copy them
into the context at context creation time. We also move is_scalar to the
brw_compiler structure.
We also end up manually setting some values that the core would have set by
default for us. Fortunately, there are only two non-zero shader compiler
option defaults that we aren't overriding anyway so this isn't a big deal.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 073294d3ef20d0dbeffcc38aff3d69eda624ee75 |
|
23-Jun-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/fs: Plumb compiler debug logging through brw_compiler
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| e639a6f68e701f23b977a49c45d646c164991d36 |
|
16-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Plumb compiler debug logging through a function pointer in brw_compiler
v2 (Ken): Make shader_debug_log a printf-like function.
v3 (Jason): Add a void * to pass the brw_context through
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| ae097580ac49fbfaf184c89c68cb42b755f62939 |
|
22-Jun-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Initialize backend_shader::mem_ctx in its constructor.
We were initializing it in each subclasses' constructors for some
reason.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 8b9ecfff360711cffc41a0a062de5ad810f9cf2b |
|
20-May-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Make fs/vec4_visitor inherit from ir_visitor directly
This is using multiple inheritance in C++. However, ir_visitor is really
just an interface with no data so it shouldn't be so bad.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 99cb4233205edcfa1a1e2967eef7bb16ff19bec4 |
|
20-May-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Rename backend_visitor to backend_shader
The backend_shader class really is a representation of a shader. The fact
that it inherits from ir_visitor is somewhat immaterial.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 76c1086f2dfb37a1edf6d2df6eebbe11ccbfc50b |
|
24-Mar-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Change header_present to header_size in backend_instruction
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 6ec6c1581c2963423917ee1598ffb07cab3f2ddc |
|
14-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Support CS program precompile
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| ae3870df7043861632aa553e12cc9284a9aef827 |
|
16-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Add a brw_compiler structure and store the register sets in it
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 02ccb19495c5804f4ab798c00eeb786ee77aaacc |
|
17-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use device_info instead of the context in instruction scheduling
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 28e9601d0e681411b60a7de8be9f401b0df77d29 |
|
16-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Add a devinfo field to backend_visitor and use it for gen checks
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| ceb6e5eebe13b85f57cf5a7a22371c10170943a3 |
|
14-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Remove the context parameter from brw_texture_offset
It wasn't really being used anyway. We used it to assert that gpu_shader5
is supported in the back-end but that should be caught by the front-end.
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 74c7e5d35181d31e4448c614f6aa62c1e1f60694 |
|
18-Mar-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define method to check whether a backend_reg is inside a given range.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| eb9bd3a1b0d6c518f9a38d81c0729feb38474f5a |
|
19-Mar-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Fix signedness of backend_reg::reg_offset.
And make it 16-bit so it packs nicely with the previous field.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| db095eb43bd02414e71f93e72ff61b463bef0ece |
|
13-Mar-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: De-duplicate is_expression_commutative() functions.
Create a backend_inst::is_commutative() method to replace two static
functions that did the exact same thing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 7e35a812643982bef5d90f4998a4f240b2edfd26 |
|
19-Feb-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Create backend_visitor fields for debugging messages.
We introduce three new fields in backend_visitor:
- debug_enabled: whether or not INTEL_DEBUG & DEBUG_<stage flag>
- stage_name: "vertex", "fragment", etc. for use in messages
- stage_abbrev: "VS", "FS", etc. for use in messages
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| e8a6f2ad65b03eac7c030b2cd4955a162739870b |
|
05-Feb-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Add an is_negative_one() method.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 78e9043475d4bed8b50f7e413963c960fa0935bb |
|
03-Feb-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965/vec4: Add register classes up to MAX_VGRF_SIZE.
In preparation for some send from GRF instructions that will require
larger payloads.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| dfe957c02b753dbb5b372e768a5677f577daf9ef |
|
06-Feb-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Move up fs_inst::flag_subreg to backend_instruction.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 639696aa05df0b7f4bfb9e2e255863cd72effba3 |
|
06-Feb-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Move up fs_inst::regs_written to backend_instruction.
It will also be useful in the VEC4 back-end.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 447879eb88b8df41ad32cf4406cc636b112b72d9 |
|
10-Feb-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Factor out virtual GRF allocation to a separate object.
Right now virtual GRF book-keeping and allocation is performed in each
visitor class separately (among other hundred different things),
leading to duplicated logic in each visitor and preventing layering as
it forces any code that manipulates i965 IR and needs to allocate
virtual registers to depend on the specific visitor that happens to be
used to translate from GLSL IR.
v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor).
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| dbd4c22a37b3605dd51833f3ecf69679b52b7bde |
|
30-Jan-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Add function to take the abs of immediates.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 638beee24ae097633c34261943aeb8b86fd2a5ee |
|
29-Jan-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Add function to negate immediates.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 215b081c2ac5d7a9d1e6a46a52633997f8ae3576 |
|
30-Dec-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add is_3src() to backend_instruction.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 0654ca7d7ea4f18b91783042cd497ab28b26ae69 |
|
24-Aug-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add backend_instruction::can_do_cmod().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 7bc6e455e231076bfac6c678c375ea4aca94ebf0 |
|
21-Dec-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add support for saturating immediates.
I don't feel great about assert(!"unimplemented: ...") but these
cases do only seem possible under some currently impossible circumstances.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| b55777f39d00a0c54023eba012d326ff09fa530b |
|
24-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make precompile functions accessible from C.
Previously, the prototypes for brw_vs/gs/fs_precompile were scattered
between brw_vs.h (C), brw_gs.h (C), and brw_fs.h (C++ only). Also,
brw_fs_precompile had C++ linkage, while the others were C.
This patch moves all the prototypes to a central location (brw_shader.h)
and makes brw_fs_precompile have C linkage.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| d9432af45a1a69d0cd1dcf12edfae920adeb4734 |
|
12-Nov-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Move common fields into backend_instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| bd502139290ea902cbc4b5f535c102f8f98774b1 |
|
12-Nov-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Combine offset/texture_offset fields.
texture_offset was only used by some texturing operations, and offset
was only used by spill/unspill and some URB operations. These fields are
never used at the same time.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| fa212c6b985f494f5609ccca1c260a2aa39c684a |
|
05-Aug-2014 |
Connor Abbott <cwabbott0@gmail.com> |
i965: Make brw_texture_offset() not use ir_texture.
Our new IR won't have ir_texture objects.
Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 444fc0b4a837a669c585f52b1d814300cfc9c999 |
|
03-Sep-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Call insert and remove functions from exec_node directly.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 072ea414d04f1b9a7bf06a00b9011e8ad521c878 |
|
01-Sep-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Remove cfg-invalidating parameter from invalidate_live_intervals.
Everything has been converted to preserve the CFG.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| e0aa45768c6bda947b645ae6962054673937a55f |
|
13-Jul-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add invalidate_cfg parameter to invalidate_live_intervals().
Will let us avoid invalidating the CFG if the optimization pass has
removed instructions using the new basic block methods.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 3d6d4dc6f7f90d65982073294a41afac8397f68a |
|
13-Jul-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add basic-block aware backend_instruction::insert_* methods.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| dc527fbf7da580f256c318756f43af3be59d2a77 |
|
13-Jul-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add a basic-block aware backend_instruction::remove method.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 0f4c5a70c6e759e3a7bddd7f1c2d2b8d219552a4 |
|
03-Aug-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Get rid of backend_instruction::sampler
The generators no longer use this.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 8d2e95bd4b0f652aabddff53cb157eb002d415f0 |
|
22-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Save the gl_shader_stage enum in backend_visitor.
This will be useful for INTEL_DEBUG=optimizer in the vec4 backend, which
needs to know whether it's currently processing a VS or GS. It isn't
worth adding virtual methods for this case.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 680fe0acb3e6569f7b9aab1913e9181d5a7eee2f |
|
12-Jul-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add cfg to backend_visitor.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 1580865a8c576f386c40c3f346636132d720654b |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Move assembly annotation functions to intel_asm_annotation.c.
It's C. Compile it as such.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 423932791d0e4bbae28f3557659f031d3b2ac980 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Rename intel_asm_printer -> intel_asm_annotation.
The #ifndef include guards already said the right thing :)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 6d3e24a5c2e31f0ba95c0c8daf897b749775fea3 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Make backend_instruction usable from C.
With a hack to place an exec_node in the struct in C to be at the same
location as the inherited exec_node in C++.
Acked-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 0db30fcf8935fab2465a63be56fd317e14fdf7c9 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965/cfg: Make cfg_t usable from C.
Acked-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 857c06236cf8086566f05e627856dcf8421e2292 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Repack backend_instruction struct.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| ce706b4a9bd53fbe274687025965333541a0e70d |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Make a brw_predicate enum.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 46e5b2a497216133be656b38ebfcf96da64b7744 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Make a brw_conditional_mod enum.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| ab74a42eef781b05bab2c67acbd37484f0e3aa2f |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Move common fields into backend_instruction.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 3de11cacf0cb307ff3b4130746732d9db73d7583 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use enum brw_reg_type for register types.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 34ef6a7651d6651e0bca77c4d4b890af582ad360 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Move is_zero/one/null/accumulator into backend_reg.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| c019105f3742b39ba6913235f85ddfb327a39d12 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Make a common backend_reg class.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 836f4299e870a7cff04c2f646a37533d0e68ccd7 |
|
15-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Mark backend_instruction and bblock_t as structs.
They have to be marked as structs for C code elsewhere. bblock_t is
already defined as a struct, and all of backend_instruction's fields are
public anyway.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 2c8520c03de135228c37d67c9ff9756e3febb660 |
|
11-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use brw->gen in some generation checks.
Will simplify the automated conversion if we want to allow compiling the
driver for a single generation.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| e9bf1662b048e5927f841e84719a3180650a2b0a |
|
29-May-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Give dump_instructions() a filename argument.
This will allow debugging code to dump the IR after an optimization pass
makes progress (the next patch). Only let it open and write to a file if
the effective user isn't root.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 56d6dcf4f771d57d2759b2a5c5006f24444c696f |
|
29-May-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Give dump_instruction() a FILE* argument.
Use function overloading rather than default arguments, since gdb
doesn't know about default arguments.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| f0f7fb181fc267934a44904da4530f50a698b18d |
|
19-May-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Print disassembly after compaction.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 520dfa4b5c64a09bb34c7e912b102fb99aef7699 |
|
07-May-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Relax accumulator dependency scheduling on Gen < 6
Many instructions implicitly update the accumulator on Gen < 6. The instruction
scheduling code just calls add_barrier_deps() for each accumulator access on
these platforms, but a large class of operations don't actually update the
accumulator -- mostly move and logical instructions. Teaching the scheduling
code about this would allow more flexibility to schedule instructions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77740
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 306ed81b9363721058c568244f9860c5c8c819f4 |
|
04-Apr-2014 |
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> |
i965: Add writes_accumulator flag
Our hardware has an "accumulator" register, which can be used to store
intermediate results across multiple instructions. Many instructions
can implicitly write a value to the accumulator in addition to their
normal destination register. This is enabled by the "AccWrEn" flag.
This patch introduces a new flag, inst->writes_accumulator, which
allows us to express the AccWrEn notion in the IR. It also creates a
n ALU2_ACC macro to easily define emitters for instructions that
implicitly write the accumulator.
Previously, we only supported implicit accumulator writes from the
ADDC, SUBB, and MACH instructions. We always enabled them on those
instructions, and left them disabled for other instructions.
To take advantage of the MAC (multiply-accumulate) instruction, we
need to be able to set AccWrEn on other types of instructions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 6541f1b4d02b52e19c95dcfb07ef5e0e81a57955 |
|
09-Apr-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add reads_accumulator_implicitly() function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 39ecfca121b6ae1ae55ed474d564998ce967682a |
|
28-Feb-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Mark is_tex() and friends as const.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 12d55d5f19368de7697f2e6df7d4ff98929112b1 |
|
18-Feb-2014 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Mark invariants in backend_visitor as constants
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| a290cd039cc07330598a101e74d25289ce70bcee |
|
18-Feb-2014 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Merge resolving of shader program source
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 81494ec6137d133f999a98474d1660b8c87d2276 |
|
14-Feb-2014 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Merge initialisation of backend_visitor
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 7770b026937948e1be3ed55f9ff97e6521c500df |
|
22-Feb-2014 |
Matt Turner <mattst88@gmail.com> |
Revert "i965/fs: Make fs_reg's type an enum for better debugging."
This reverts commit 5ceadd29b0af835d741bcf09b9622c628e549ae6.
I rebased and apparently failed to build test.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75355
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 5ceadd29b0af835d741bcf09b9622c628e549ae6 |
|
20-Feb-2014 |
Matt Turner <mattst88@gmail.com> |
i965/fs: Make fs_reg's type an enum for better debugging.
Since the enum is marked as packed, it'll still take only one byte.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 98e2654880ef57617e82b6a75578d2ac5f2d6c6c |
|
20-Feb-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Mark brw_reg_type and register_file enums as PACKED.
The C99 spec says the type of an enum is implementation defined (but can
be char, signed int, or unsigned int). gcc appears to always give enums
four bytes, even when they can fit in less. It does so because this is
what other compilers seem to do [0] and therefore to maintain ABI
compatibility with them.
gcc has an -fshort-enum flag that tells the compiler to use only as much
space as needed for an enum. Adding __attribute__((__packed__)) to an
enum definition has the same behavior, but on a per-enum basis.
brw_reg_type and register_file are not part of the ABI, so we can safely
mark them as PACKED so that they'll take only a byte, rather than four.
[0] http://gcc.gnu.org/onlinedocs/gcc/Non-bugs.html#index-fshort-enums-3868
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 00c567e897f02e8680a8d628bbca2bb01e69a69b |
|
20-Feb-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Reduce predicate field of backend_instruction to uint8_t.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 39d7ec2c9a1b0213fa64c58fe3e1843119a62904 |
|
12-Dec-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Add can_do_saturate() method to backend_instruction.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 391eaa59bd2b71078a28ff34dd3d4eed470653ee |
|
05-Aug-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Show register pressure in dump_instructions() output.
Dumping the number of live registers at each IP allows us to see
register pressure and identify any local maxima. This should
aid in debugging passes designed to reduce register pressure, as
well as optimizations that suddenly trigger spilling.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 46cf80fb366cb14827724a7fea004e81400cc602 |
|
19-Nov-2013 |
Eric Anholt <eric@anholt.net> |
i965/fs: Make the first pre-allocation heuristic be the post heuristic.
I recently made us try two different things that tried to reduce register
pressure so that we would be more likely to allocate successfully. But
now that we have the logic for trying two, we can make the first thing we
try be the normal, not-prioritizing-register-pressure heuristic.
This means one less scheduling pass in the common case of that heuristic
not producing spills, plus the best schedule we know how to produce, if
that one happens to succeed. This is important, because our register
allocation produces a lot of possibly avoidable dependencies for the
post-register-allocation schedule, despite ra_set_allocate_round_robin().
GLB2.7: 1.04127% +/- 0.732461% fps improvement (n=31)
nexuiz: No difference (n=5)
lightsmark: 0.838512% +/- 0.300147% fps improvement (n=86)
minecraft apitrace: No difference (n=15)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| b63d6aae55c06bf7cb6b9ed1370634bc120ed045 |
|
11-Nov-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Make invalidate_live_intervals() a virtual method of backend_visitor.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| e9daead784921e453906853a4a78a2f3135af2e0 |
|
07-Nov-2013 |
Eric Anholt <eric@anholt.net> |
i965/fs: Try a different pre-scheduling heuristic if the first spills.
Since LIFO fails on some shaders in one particular way, and non-LIFO
systematically fails in another way on different kinds of shaders, try
them both, and pick whichever one successfully register allocates first.
Slightly prefer non-LIFO in case we produce extra dependencies in register
allocation, since it should start out with fewer stalls than LIFO.
This is madness, but I haven't come up with another way to get unigine
tropics to not spill while keeping other programs from not spilling and
retaining the non-unigine performance wins from texture-grf.
total instructions in shared programs: 1626728 -> 1626288 (-0.03%)
instructions in affected programs: 1015 -> 575 (-43.35%)
GAINED: 50
LOST: 0
Improves Unigine Tropics performance by 14.5257% +/- 0.241838% (n=38)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70445
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 34fe051e215107dddbaae71e2edf15f88d839936 |
|
20-Oct-2013 |
Francisco Jerez <currojerez@riseup.net> |
i965: Add a 'has_side_effects' back-end instruction predicate.
This patch fixes the three dead code elimination passes and the
VEC4/FS instruction scheduling passes so they leave instructions with
side effects alone.
At some point it might be interesting to have the instruction
scheduler calculate the exact memory dependencies between atomic ops,
but they're rare enough that it seems unlikely that it will make any
practical difference.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| bdcacaed9c64c49827d325d15ada2c482bfe1578 |
|
08-Oct-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: relax brw_texture_offset assert
Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 705a90e30435490c2de84f4f6741cab335fa7608 |
|
03-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Move the common binding table offset code to brw_shader.cpp.
Now that both vec4 and fs are dynamically assigning offsets, a lot of the
code is the same.
v2: Avoid passing around the next offset through the class. (Review by
Paul)
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 5463b5bbbdf133986ac89fd6afdf2bc9622e3ca6 |
|
03-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Always have the struct gl_program * in the backend visitor.
vec4 already had it, so put it in the FS, too.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| a5ec01fb1bd4ad5418eb16cb05e6f6929d1444e8 |
|
20-Sep-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Don't copy prop source mods into instructions that can't take them.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| b645913ff6c74228d8c05dd236a545ef2e734071 |
|
28-Sep-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Remove the "ARF" register file.
The registers in the architecture register file don't share much in
common, so there's no point in grouping them together. Use the HW_REG
class instead. The vec4 backend already does this.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| e556286802811b4b99c692d1ff5197f8ee1f011b |
|
21-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Make brw_{shader,vec4}.h safe to include from C.
The patch that follows will move the definition of struct
brw_vec4_prog_key from brw_vs.h to brw_vec4.h, making it necessary for
brw_vs.h to include brw_vec4.h (because brw_vs.h defines struct
brw_vs_prog_key, which contains brw_vec4_prog_key as a member). Since
brw_vs.h is included from C source files, that means that brw_vec4.h
will need to be safe to include from C. Same for brw_shader.h, since
it is included by brw_vec4.h.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| ab04f3b2d74af061a0d2ebf3d1a02d8fcf73ff09 |
|
30-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Share the register file enum between the two backends.
I need this so I can look at vec4 and fs registers' files from the same
.cpp file without namespaces. As far as I can tell we never rely on the
particular numerical values of the files, though I thought it sounded like
a good idea when doing the VS (it turns out having 0 be BAD_FILE is nicer).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 63c8155b09bca7917631ec678a0d0db6e7965a1a |
|
29-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make dump_instructions be a virtual method of the visitor.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 5e46482993dfd30b888d5219f6fecf4b4d1f42de |
|
28-Apr-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move is_math/is_tex/is_control_flow() to backend_instruction.
These are entirely based on the opcode, which is available in
backend_instruction. It makes sense to only implement them in one
place.
This changes the VS implementation of is_tex() slightly, which now
accepts FS_OPCODE_TXB and SHADER_OPCODE_LOD. However, since those
aren't generated in the VS anyway, it should be fine.
This also makes is_control_flow() available in the VS.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| fe97f26c86d65b1b0e026c725c7da348a91093d9 |
|
09-Apr-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Rename backend_visitor::prog to shader_prog.
The next patch is going to change the type of vec4_visitor::vp from
struct gl_vertex_program * to struct gl_program *, and rename it. The
sensible name to change it to is vec4_visitor::prog. However, prog is
already used in backend_visitor (which vec4_visitor derives from).
Since backend_visitor::prog is of type struct gl_shader_program *, it
makes sense to rename it to shader_prog.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 20d846ce8b46604ced835eb68079a0dbae2e19dc |
|
12-Mar-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add names for all instructions to dump_instruction() in FS and VS.
I'd previously added the minimum names to understand my dumps, but this
makes dumps in general much easier to read.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 9136723214136a95a3c915d580943c888cd99503 |
|
21-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Move struct brw_compile (p) entirely inside fs_generator.
The brw_compile structure contains the brw_instruction store and the
brw_eu_emit.c state tracking fields. These are only useful for the
final assembly generation pass; the earlier compilation stages doesn't
need them.
This also means that the code generator for future hardware won't have
access to the brw_compile structure, which is extremely desirable
because it prevents accidental generation of Gen4-7 code.
v2: rzalloc p, as suggested by Eric.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 54679fcbcae7a2d41cb439e52e386bd811a291b4 |
|
03-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965: Share the predicate field between FS and VS.
Note that BRW_PREDICATE_NONE is 0 and BRW_PREDICATE_NORMAL is 1, so that's a
lot like the true/false we had in the FS before.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 24aeeb2fdcde7a0c257db6469c6b0f064d53d3cf |
|
03-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make the FS and VS share a few visitor/instruction fields.
This will let us reuse brw_fs_cfg.cpp from brw_vec4_*.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 475d70d6ef5feb94efab3923e5607e625f2aee67 |
|
26-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Factor out texture offset bitfield computation.
We'll want to reuse this for the VS, and it's complex enough that I'd
rather not cut and paste it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| af3c9803d818fd33139f1247a387d64b967b8992 |
|
02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| 6034b9a5124475d300d0678bd2fb6160865fa972 |
|
03-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Create a shared enum for hardware and compiler-internal opcodes.
This should make gdbing more pleasant, and it might be used in sharing
part of the codegen between the VS and FS backends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|
| b7b700aeb0eab2cae26a01d9db42feea969333c7 |
|
26-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move a couple of GLSL IR -> BRW helper functions to brw_shader.cpp.
These will be used by the VS backend as well.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_shader.h
|