brw_shader.h revision 7bc6e455e231076bfac6c678c375ea4aca94ebf0 
1/*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include <stdint.h>
25#include "brw_reg.h"
26#include "brw_defines.h"
27#include "main/compiler.h"
28#include "glsl/ir.h"
29
30#pragma once
31
32enum PACKED register_file {
33   BAD_FILE,
34   GRF,
35   MRF,
36   IMM,
37   HW_REG, /* a struct brw_reg */
38   ATTR,
39   UNIFORM, /* prog_data->params[reg] */
40};
41
42struct backend_reg
43{
44#ifdef __cplusplus
45   bool is_zero() const;
46   bool is_one() const;
47   bool is_null() const;
48   bool is_accumulator() const;
49#endif
50
51   enum register_file file; /**< Register file: GRF, MRF, IMM. */
52   enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
53
54   /**
55    * Register number.
56    *
57    * For GRF, it's a virtual register number until register allocation.
58    *
59    * For MRF, it's the hardware register.
60    */
61   uint16_t reg;
62
63   /**
64    * Offset within the virtual register.
65    *
66    * In the scalar backend, this is in units of a float per pixel for pre-
67    * register allocation registers (i.e., one register in SIMD8 mode and two
68    * registers in SIMD16 mode).
69    *
70    * For uniforms, this is in units of 1 float.
71    */
72   int reg_offset;
73
74   struct brw_reg fixed_hw_reg;
75
76   bool negate;
77   bool abs;
78};
79
80struct cfg_t;
81struct bblock_t;
82
83#ifdef __cplusplus
84struct backend_instruction : public exec_node {
85   bool is_tex() const;
86   bool is_math() const;
87   bool is_control_flow() const;
88   bool can_do_source_mods() const;
89   bool can_do_saturate() const;
90   bool reads_accumulator_implicitly() const;
91   bool writes_accumulator_implicitly(struct brw_context *brw) const;
92
93   void remove(bblock_t *block);
94   void insert_after(bblock_t *block, backend_instruction *inst);
95   void insert_before(bblock_t *block, backend_instruction *inst);
96   void insert_before(bblock_t *block, exec_list *list);
97
98   /**
99    * True if the instruction has side effects other than writing to
100    * its destination registers.  You are expected not to reorder or
101    * optimize these out unless you know what you are doing.
102    */
103   bool has_side_effects() const;
104#else
105struct backend_instruction {
106   struct exec_node link;
107#endif
108   /** @{
109    * Annotation for the generated IR.  One of the two can be set.
110    */
111   const void *ir;
112   const char *annotation;
113   /** @} */
114
115   uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
116   uint8_t mlen; /**< SEND message length */
117   int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
118   uint8_t target; /**< MRT target. */
119
120   enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
121   enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
122   enum brw_predicate predicate;
123   bool predicate_inverse:1;
124   bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
125   bool force_writemask_all:1;
126   bool no_dd_clear:1;
127   bool no_dd_check:1;
128   bool saturate:1;
129   bool shadow_compare:1;
130   bool header_present:1;
131};
132
133#ifdef __cplusplus
134
135enum instruction_scheduler_mode {
136   SCHEDULE_PRE,
137   SCHEDULE_PRE_NON_LIFO,
138   SCHEDULE_PRE_LIFO,
139   SCHEDULE_POST,
140};
141
142class backend_visitor : public ir_visitor {
143protected:
144
145   backend_visitor(struct brw_context *brw,
146                   struct gl_shader_program *shader_prog,
147                   struct gl_program *prog,
148                   struct brw_stage_prog_data *stage_prog_data,
149                   gl_shader_stage stage);
150
151public:
152
153   struct brw_context * const brw;
154   struct gl_context * const ctx;
155   struct brw_shader * const shader;
156   struct gl_shader_program * const shader_prog;
157   struct gl_program * const prog;
158   struct brw_stage_prog_data * const stage_prog_data;
159
160   /** ralloc context for temporary data used during compile */
161   void *mem_ctx;
162
163   /**
164    * List of either fs_inst or vec4_instruction (inheriting from
165    * backend_instruction)
166    */
167   exec_list instructions;
168
169   cfg_t *cfg;
170
171   gl_shader_stage stage;
172
173   virtual void dump_instruction(backend_instruction *inst) = 0;
174   virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
175   virtual void dump_instructions();
176   virtual void dump_instructions(const char *name);
177
178   void calculate_cfg();
179   void invalidate_cfg();
180
181   void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
182
183   virtual void invalidate_live_intervals() = 0;
184};
185
186uint32_t brw_texture_offset(struct gl_context *ctx, int *offsets,
187                            unsigned num_components);
188
189#endif /* __cplusplus */
190
191enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
192enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
193uint32_t brw_math_function(enum opcode op);
194const char *brw_instruction_name(enum opcode op);
195bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
196
197#ifdef __cplusplus
198extern "C" {
199#endif
200
201bool brw_vs_precompile(struct gl_context *ctx,
202                       struct gl_shader_program *shader_prog,
203                       struct gl_program *prog);
204bool brw_gs_precompile(struct gl_context *ctx,
205                       struct gl_shader_program *shader_prog,
206                       struct gl_program *prog);
207bool brw_fs_precompile(struct gl_context *ctx,
208                       struct gl_shader_program *shader_prog,
209                       struct gl_program *prog);
210
211#ifdef __cplusplus
212}
213#endif
214