brw_shader.h revision 8d2e95bd4b0f652aabddff53cb157eb002d415f0 
1/*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include <stdint.h>
25#include "brw_reg.h"
26#include "brw_defines.h"
27#include "main/compiler.h"
28#include "glsl/ir.h"
29
30#pragma once
31
32enum PACKED register_file {
33   BAD_FILE,
34   GRF,
35   MRF,
36   IMM,
37   HW_REG, /* a struct brw_reg */
38   ATTR,
39   UNIFORM, /* prog_data->params[reg] */
40};
41
42struct backend_reg
43{
44#ifdef __cplusplus
45   bool is_zero() const;
46   bool is_one() const;
47   bool is_null() const;
48   bool is_accumulator() const;
49#endif
50
51   enum register_file file; /**< Register file: GRF, MRF, IMM. */
52   enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
53
54   /**
55    * Register number.
56    *
57    * For GRF, it's a virtual register number until register allocation.
58    *
59    * For MRF, it's the hardware register.
60    */
61   uint16_t reg;
62
63   /**
64    * Offset within the virtual register.
65    *
66    * In the scalar backend, this is in units of a float per pixel for pre-
67    * register allocation registers (i.e., one register in SIMD8 mode and two
68    * registers in SIMD16 mode).
69    *
70    * For uniforms, this is in units of 1 float.
71    */
72   int reg_offset;
73
74   struct brw_reg fixed_hw_reg;
75
76   bool negate;
77   bool abs;
78};
79
80struct cfg_t;
81
82#ifdef __cplusplus
83struct backend_instruction : public exec_node {
84   bool is_tex() const;
85   bool is_math() const;
86   bool is_control_flow() const;
87   bool can_do_source_mods() const;
88   bool can_do_saturate() const;
89   bool reads_accumulator_implicitly() const;
90   bool writes_accumulator_implicitly(struct brw_context *brw) const;
91
92   /**
93    * True if the instruction has side effects other than writing to
94    * its destination registers.  You are expected not to reorder or
95    * optimize these out unless you know what you are doing.
96    */
97   bool has_side_effects() const;
98#else
99struct backend_instruction {
100   struct exec_node link;
101#endif
102   /** @{
103    * Annotation for the generated IR.  One of the two can be set.
104    */
105   const void *ir;
106   const char *annotation;
107   /** @} */
108
109   uint32_t texture_offset; /**< Texture offset bitfield */
110   uint32_t offset; /**< spill/unspill offset */
111   uint8_t sampler;
112   uint8_t mlen; /**< SEND message length */
113   int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
114   uint8_t target; /**< MRT target. */
115
116   enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
117   enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
118   enum brw_predicate predicate;
119   bool predicate_inverse:1;
120   bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
121   bool force_writemask_all:1;
122   bool no_dd_clear:1;
123   bool no_dd_check:1;
124   bool saturate:1;
125};
126
127#ifdef __cplusplus
128
129enum instruction_scheduler_mode {
130   SCHEDULE_PRE,
131   SCHEDULE_PRE_NON_LIFO,
132   SCHEDULE_PRE_LIFO,
133   SCHEDULE_POST,
134};
135
136class backend_visitor : public ir_visitor {
137protected:
138
139   backend_visitor(struct brw_context *brw,
140                   struct gl_shader_program *shader_prog,
141                   struct gl_program *prog,
142                   struct brw_stage_prog_data *stage_prog_data,
143                   gl_shader_stage stage);
144
145public:
146
147   struct brw_context * const brw;
148   struct gl_context * const ctx;
149   struct brw_shader * const shader;
150   struct gl_shader_program * const shader_prog;
151   struct gl_program * const prog;
152   struct brw_stage_prog_data * const stage_prog_data;
153
154   /** ralloc context for temporary data used during compile */
155   void *mem_ctx;
156
157   /**
158    * List of either fs_inst or vec4_instruction (inheriting from
159    * backend_instruction)
160    */
161   exec_list instructions;
162
163   cfg_t *cfg;
164
165   gl_shader_stage stage;
166
167   virtual void dump_instruction(backend_instruction *inst) = 0;
168   virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
169   virtual void dump_instructions();
170   virtual void dump_instructions(const char *name);
171
172   void calculate_cfg();
173   void invalidate_cfg();
174
175   void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
176
177   virtual void invalidate_live_intervals() = 0;
178};
179
180uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
181
182#endif /* __cplusplus */
183
184enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
185enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
186uint32_t brw_math_function(enum opcode op);
187const char *brw_instruction_name(enum opcode op);
188