1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implementation of the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15#include "llvm/CodeGen/MachineInstrBuilder.h"
16#include "llvm/Target/TargetInstrInfo.h"
17#include "llvm/Target/TargetMachine.h"
18using namespace llvm;
19
20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
21  : TRI(&TRI), IsSSA(true) {
22  VRegInfo.reserve(256);
23  RegAllocHints.reserve(256);
24  UsedPhysRegs.resize(TRI.getNumRegs());
25
26  // Create the physreg use/def lists.
27  PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28  memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
29}
30
31MachineRegisterInfo::~MachineRegisterInfo() {
32#ifndef NDEBUG
33  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
34    assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
35           "Vreg use list non-empty still?");
36  for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
37    assert(!PhysRegUseDefLists[i] &&
38           "PhysRegUseDefLists has entries after all instructions are deleted");
39#endif
40  delete [] PhysRegUseDefLists;
41}
42
43/// setRegClass - Set the register class of the specified virtual register.
44///
45void
46MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47  VRegInfo[Reg].first = RC;
48}
49
50const TargetRegisterClass *
51MachineRegisterInfo::constrainRegClass(unsigned Reg,
52                                       const TargetRegisterClass *RC,
53                                       unsigned MinNumRegs) {
54  const TargetRegisterClass *OldRC = getRegClass(Reg);
55  if (OldRC == RC)
56    return RC;
57  const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
58  if (!NewRC || NewRC == OldRC)
59    return NewRC;
60  if (NewRC->getNumRegs() < MinNumRegs)
61    return 0;
62  setRegClass(Reg, NewRC);
63  return NewRC;
64}
65
66bool
67MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
68  const TargetInstrInfo *TII = TM.getInstrInfo();
69  const TargetRegisterClass *OldRC = getRegClass(Reg);
70  const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
71
72  // Stop early if there is no room to grow.
73  if (NewRC == OldRC)
74    return false;
75
76  // Accumulate constraints from all uses.
77  for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
78       ++I) {
79    // TRI doesn't have accurate enough information to model this yet.
80    if (I.getOperand().getSubReg())
81      return false;
82    const TargetRegisterClass *OpRC =
83      I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
84    if (OpRC)
85      NewRC = TRI->getCommonSubClass(NewRC, OpRC);
86    if (!NewRC || NewRC == OldRC)
87      return false;
88  }
89  setRegClass(Reg, NewRC);
90  return true;
91}
92
93/// createVirtualRegister - Create and return a new virtual register in the
94/// function with the specified register class.
95///
96unsigned
97MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
98  assert(RegClass && "Cannot create register without RegClass!");
99  assert(RegClass->isAllocatable() &&
100         "Virtual register RegClass must be allocatable.");
101
102  // New virtual register number.
103  unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
104
105  // Add a reg, but keep track of whether the vector reallocated or not.
106  const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
107  void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
108  VRegInfo.grow(Reg);
109  VRegInfo[Reg].first = RegClass;
110  RegAllocHints.grow(Reg);
111
112  if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
113    // The vector reallocated, handle this now.
114    HandleVRegListReallocation();
115  return Reg;
116}
117
118/// HandleVRegListReallocation - We just added a virtual register to the
119/// VRegInfo info list and it reallocated.  Update the use/def lists info
120/// pointers.
121void MachineRegisterInfo::HandleVRegListReallocation() {
122  // The back pointers for the vreg lists point into the previous vector.
123  // Update them to point to their correct slots.
124  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
125    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
126    MachineOperand *List = VRegInfo[Reg].second;
127    if (!List) continue;
128    // Update the back-pointer to be accurate once more.
129    List->Contents.Reg.Prev = &VRegInfo[Reg].second;
130  }
131}
132
133/// replaceRegWith - Replace all instances of FromReg with ToReg in the
134/// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
135/// except that it also changes any definitions of the register as well.
136void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
137  assert(FromReg != ToReg && "Cannot replace a reg with itself");
138
139  // TODO: This could be more efficient by bulk changing the operands.
140  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
141    MachineOperand &O = I.getOperand();
142    ++I;
143    O.setReg(ToReg);
144  }
145}
146
147
148/// getVRegDef - Return the machine instr that defines the specified virtual
149/// register or null if none is found.  This assumes that the code is in SSA
150/// form, so there should only be one definition.
151MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
152  // Since we are in SSA form, we can use the first definition.
153  if (!def_empty(Reg))
154    return &*def_begin(Reg);
155  return 0;
156}
157
158bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
159  use_iterator UI = use_begin(RegNo);
160  if (UI == use_end())
161    return false;
162  return ++UI == use_end();
163}
164
165bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
166  use_nodbg_iterator UI = use_nodbg_begin(RegNo);
167  if (UI == use_nodbg_end())
168    return false;
169  return ++UI == use_nodbg_end();
170}
171
172/// clearKillFlags - Iterate over all the uses of the given register and
173/// clear the kill flag from the MachineOperand. This function is used by
174/// optimization passes which extend register lifetimes and need only
175/// preserve conservative kill flag information.
176void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
177  for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
178    UI.getOperand().setIsKill(false);
179}
180
181bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
182  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
183    if (I->first == Reg || I->second == Reg)
184      return true;
185  return false;
186}
187
188bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
189  for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
190    if (*I == Reg)
191      return true;
192  return false;
193}
194
195/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
196/// corresponding live-in physical register.
197unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
198  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
199    if (I->second == VReg)
200      return I->first;
201  return 0;
202}
203
204/// getLiveInVirtReg - If PReg is a live-in physical register, return the
205/// corresponding live-in physical register.
206unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
207  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
208    if (I->first == PReg)
209      return I->second;
210  return 0;
211}
212
213/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
214/// into the given entry block.
215void
216MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
217                                      const TargetRegisterInfo &TRI,
218                                      const TargetInstrInfo &TII) {
219  // Emit the copies into the top of the block.
220  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
221    if (LiveIns[i].second) {
222      if (use_empty(LiveIns[i].second)) {
223        // The livein has no uses. Drop it.
224        //
225        // It would be preferable to have isel avoid creating live-in
226        // records for unused arguments in the first place, but it's
227        // complicated by the debug info code for arguments.
228        LiveIns.erase(LiveIns.begin() + i);
229        --i; --e;
230      } else {
231        // Emit a copy.
232        BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
233                TII.get(TargetOpcode::COPY), LiveIns[i].second)
234          .addReg(LiveIns[i].first);
235
236        // Add the register to the entry block live-in set.
237        EntryMBB->addLiveIn(LiveIns[i].first);
238      }
239    } else {
240      // Add the register to the entry block live-in set.
241      EntryMBB->addLiveIn(LiveIns[i].first);
242    }
243}
244
245void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
246  for (int i = UsedPhysRegs.find_first(); i >= 0;
247       i = UsedPhysRegs.find_next(i))
248         for (const unsigned *SS = TRI.getSubRegisters(i);
249              unsigned SubReg = *SS; ++SS)
250           if (SubReg > unsigned(i))
251             UsedPhysRegs.set(SubReg);
252}
253
254#ifndef NDEBUG
255void MachineRegisterInfo::dumpUses(unsigned Reg) const {
256  for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
257    I.getOperand().getParent()->dump();
258}
259#endif
260