1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARMMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMFixupKinds.h"
18#include "MCTargetDesc/ARMMCExpr.h"
19#include "MCTargetDesc/ARMMCTargetDesc.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/Support/raw_ostream.h"
29
30using namespace llvm;
31
32STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
34
35namespace {
36class ARMMCCodeEmitter : public MCCodeEmitter {
37  ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38  void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39  const MCInstrInfo &MCII;
40  const MCSubtargetInfo &STI;
41
42public:
43  ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
44                   MCContext &ctx)
45    : MCII(mcii), STI(sti) {
46  }
47
48  ~ARMMCCodeEmitter() {}
49
50  bool isThumb() const {
51    // FIXME: Can tablegen auto-generate this?
52    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53  }
54  bool isThumb2() const {
55    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56  }
57  bool isTargetDarwin() const {
58    Triple TT(STI.getTargetTriple());
59    Triple::OSType OS = TT.getOS();
60    return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
61  }
62
63  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64
65  // getBinaryCodeForInstr - TableGen'erated function for getting the
66  // binary encoding for an instruction.
67  unsigned getBinaryCodeForInstr(const MCInst &MI,
68                                 SmallVectorImpl<MCFixup> &Fixups) const;
69
70  /// getMachineOpValue - Return binary encoding of operand. If the machine
71  /// operand requires relocation, record the relocation and return zero.
72  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                             SmallVectorImpl<MCFixup> &Fixups) const;
74
75  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76  /// the specified operand. This is used for operands with :lower16: and
77  /// :upper16: prefixes.
78  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79                               SmallVectorImpl<MCFixup> &Fixups) const;
80
81  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82                              unsigned &Reg, unsigned &Imm,
83                              SmallVectorImpl<MCFixup> &Fixups) const;
84
85  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
86  /// BL branch target.
87  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88                                   SmallVectorImpl<MCFixup> &Fixups) const;
89
90  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91  /// BLX branch target.
92  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                    SmallVectorImpl<MCFixup> &Fixups) const;
94
95  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                   SmallVectorImpl<MCFixup> &Fixups) const;
98
99  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101                                    SmallVectorImpl<MCFixup> &Fixups) const;
102
103  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                   SmallVectorImpl<MCFixup> &Fixups) const;
106
107  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
108  /// branch target.
109  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110                                  SmallVectorImpl<MCFixup> &Fixups) const;
111
112  /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113  /// immediate Thumb2 direct branch target.
114  uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115                                  SmallVectorImpl<MCFixup> &Fixups) const;
116
117  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
118  /// branch target.
119  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                     SmallVectorImpl<MCFixup> &Fixups) const;
121  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
122                                     SmallVectorImpl<MCFixup> &Fixups) const;
123
124  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
125  /// ADR label target.
126  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127                              SmallVectorImpl<MCFixup> &Fixups) const;
128  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129                              SmallVectorImpl<MCFixup> &Fixups) const;
130  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131                              SmallVectorImpl<MCFixup> &Fixups) const;
132
133
134  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
135  /// operand.
136  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
137                                   SmallVectorImpl<MCFixup> &Fixups) const;
138
139  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
140  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
141                                         SmallVectorImpl<MCFixup> &Fixups)const;
142
143  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
144  /// operand.
145  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
146                                   SmallVectorImpl<MCFixup> &Fixups) const;
147
148  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
149  /// operand.
150  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
151                                   SmallVectorImpl<MCFixup> &Fixups) const;
152
153  /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
154  /// operand.
155  uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
156                              SmallVectorImpl<MCFixup> &Fixups) const;
157
158
159  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
160  /// operand as needed by load/store instructions.
161  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
162                               SmallVectorImpl<MCFixup> &Fixups) const;
163
164  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
165  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
166                               SmallVectorImpl<MCFixup> &Fixups) const {
167    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
168    switch (Mode) {
169    default: assert(0 && "Unknown addressing sub-mode!");
170    case ARM_AM::da: return 0;
171    case ARM_AM::ia: return 1;
172    case ARM_AM::db: return 2;
173    case ARM_AM::ib: return 3;
174    }
175  }
176  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
177  ///
178  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
179    switch (ShOpc) {
180    default: llvm_unreachable("Unknown shift opc!");
181    case ARM_AM::no_shift:
182    case ARM_AM::lsl: return 0;
183    case ARM_AM::lsr: return 1;
184    case ARM_AM::asr: return 2;
185    case ARM_AM::ror:
186    case ARM_AM::rrx: return 3;
187    }
188    return 0;
189  }
190
191  /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
192  uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
193                               SmallVectorImpl<MCFixup> &Fixups) const;
194
195  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
196  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
197                                     SmallVectorImpl<MCFixup> &Fixups) const;
198
199  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
200  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
201                                SmallVectorImpl<MCFixup> &Fixups) const;
202
203  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
204  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
205                                     SmallVectorImpl<MCFixup> &Fixups) const;
206
207  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
208  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
209                               SmallVectorImpl<MCFixup> &Fixups) const;
210
211  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
212  /// operand.
213  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
214                                     SmallVectorImpl<MCFixup> &Fixups) const;
215
216  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
217  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
218                                SmallVectorImpl<MCFixup> &Fixups) const;
219
220  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
221  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
222                                SmallVectorImpl<MCFixup> &Fixups) const;
223
224  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
225  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
226                               SmallVectorImpl<MCFixup> &Fixups) const;
227
228  /// getCCOutOpValue - Return encoding of the 's' bit.
229  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
230                           SmallVectorImpl<MCFixup> &Fixups) const {
231    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
232    // '1' respectively.
233    return MI.getOperand(Op).getReg() == ARM::CPSR;
234  }
235
236  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
237  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
238                           SmallVectorImpl<MCFixup> &Fixups) const {
239    unsigned SoImm = MI.getOperand(Op).getImm();
240    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
241    assert(SoImmVal != -1 && "Not a valid so_imm value!");
242
243    // Encode rotate_imm.
244    unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
245      << ARMII::SoRotImmShift;
246
247    // Encode immed_8.
248    Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
249    return Binary;
250  }
251
252  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
253  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
254                           SmallVectorImpl<MCFixup> &Fixups) const {
255    unsigned SoImm = MI.getOperand(Op).getImm();
256    unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
257    assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
258    return Encoded;
259  }
260
261  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
262    SmallVectorImpl<MCFixup> &Fixups) const;
263  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
264    SmallVectorImpl<MCFixup> &Fixups) const;
265  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
266    SmallVectorImpl<MCFixup> &Fixups) const;
267  unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
268    SmallVectorImpl<MCFixup> &Fixups) const;
269
270  /// getSORegOpValue - Return an encoded so_reg shifted register value.
271  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
272                           SmallVectorImpl<MCFixup> &Fixups) const;
273  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
274                           SmallVectorImpl<MCFixup> &Fixups) const;
275  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
276                             SmallVectorImpl<MCFixup> &Fixups) const;
277
278  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
279                                   SmallVectorImpl<MCFixup> &Fixups) const {
280    return 64 - MI.getOperand(Op).getImm();
281  }
282
283  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
284                                      SmallVectorImpl<MCFixup> &Fixups) const;
285
286  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
287                                  SmallVectorImpl<MCFixup> &Fixups) const;
288  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
289                                      SmallVectorImpl<MCFixup> &Fixups) const;
290  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
291                                        SmallVectorImpl<MCFixup> &Fixups) const;
292  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
293                                        SmallVectorImpl<MCFixup> &Fixups) const;
294  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
295                                     SmallVectorImpl<MCFixup> &Fixups) const;
296
297  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
298                             SmallVectorImpl<MCFixup> &Fixups) const;
299  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
300                              SmallVectorImpl<MCFixup> &Fixups) const;
301  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
302                              SmallVectorImpl<MCFixup> &Fixups) const;
303  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
304                              SmallVectorImpl<MCFixup> &Fixups) const;
305
306  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
307                                 SmallVectorImpl<MCFixup> &Fixups) const;
308
309  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
310                                      unsigned EncodedValue) const;
311  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
312                                          unsigned EncodedValue) const;
313  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
314                                    unsigned EncodedValue) const;
315
316  unsigned VFPThumb2PostEncoder(const MCInst &MI,
317                                unsigned EncodedValue) const;
318
319  void EmitByte(unsigned char C, raw_ostream &OS) const {
320    OS << (char)C;
321  }
322
323  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
324    // Output the constant in little endian byte order.
325    for (unsigned i = 0; i != Size; ++i) {
326      EmitByte(Val & 255, OS);
327      Val >>= 8;
328    }
329  }
330
331  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
332                         SmallVectorImpl<MCFixup> &Fixups) const;
333};
334
335} // end anonymous namespace
336
337MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
338                                            const MCSubtargetInfo &STI,
339                                            MCContext &Ctx) {
340  return new ARMMCCodeEmitter(MCII, STI, Ctx);
341}
342
343/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
344/// instructions, and rewrite them to their Thumb2 form if we are currently in
345/// Thumb2 mode.
346unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
347                                                 unsigned EncodedValue) const {
348  if (isThumb2()) {
349    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
350    // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
351    // set to 1111.
352    unsigned Bit24 = EncodedValue & 0x01000000;
353    unsigned Bit28 = Bit24 << 4;
354    EncodedValue &= 0xEFFFFFFF;
355    EncodedValue |= Bit28;
356    EncodedValue |= 0x0F000000;
357  }
358
359  return EncodedValue;
360}
361
362/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
363/// instructions, and rewrite them to their Thumb2 form if we are currently in
364/// Thumb2 mode.
365unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
366                                                 unsigned EncodedValue) const {
367  if (isThumb2()) {
368    EncodedValue &= 0xF0FFFFFF;
369    EncodedValue |= 0x09000000;
370  }
371
372  return EncodedValue;
373}
374
375/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
376/// instructions, and rewrite them to their Thumb2 form if we are currently in
377/// Thumb2 mode.
378unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
379                                                 unsigned EncodedValue) const {
380  if (isThumb2()) {
381    EncodedValue &= 0x00FFFFFF;
382    EncodedValue |= 0xEE000000;
383  }
384
385  return EncodedValue;
386}
387
388/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
389/// them to their Thumb2 form if we are currently in Thumb2 mode.
390unsigned ARMMCCodeEmitter::
391VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
392  if (isThumb2()) {
393    EncodedValue &= 0x0FFFFFFF;
394    EncodedValue |= 0xE0000000;
395  }
396  return EncodedValue;
397}
398
399/// getMachineOpValue - Return binary encoding of operand. If the machine
400/// operand requires relocation, record the relocation and return zero.
401unsigned ARMMCCodeEmitter::
402getMachineOpValue(const MCInst &MI, const MCOperand &MO,
403                  SmallVectorImpl<MCFixup> &Fixups) const {
404  if (MO.isReg()) {
405    unsigned Reg = MO.getReg();
406    unsigned RegNo = getARMRegisterNumbering(Reg);
407
408    // Q registers are encoded as 2x their register number.
409    switch (Reg) {
410    default:
411      return RegNo;
412    case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
413    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
414    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
415    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
416      return 2 * RegNo;
417    }
418  } else if (MO.isImm()) {
419    return static_cast<unsigned>(MO.getImm());
420  } else if (MO.isFPImm()) {
421    return static_cast<unsigned>(APFloat(MO.getFPImm())
422                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
423  }
424
425  llvm_unreachable("Unable to encode MCOperand!");
426  return 0;
427}
428
429/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
430bool ARMMCCodeEmitter::
431EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
432                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
433  const MCOperand &MO  = MI.getOperand(OpIdx);
434  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
435
436  Reg = getARMRegisterNumbering(MO.getReg());
437
438  int32_t SImm = MO1.getImm();
439  bool isAdd = true;
440
441  // Special value for #-0
442  if (SImm == INT32_MIN) {
443    SImm = 0;
444    isAdd = false;
445  }
446
447  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
448  if (SImm < 0) {
449    SImm = -SImm;
450    isAdd = false;
451  }
452
453  Imm = SImm;
454  return isAdd;
455}
456
457/// getBranchTargetOpValue - Helper function to get the branch target operand,
458/// which is either an immediate or requires a fixup.
459static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
460                                       unsigned FixupKind,
461                                       SmallVectorImpl<MCFixup> &Fixups) {
462  const MCOperand &MO = MI.getOperand(OpIdx);
463
464  // If the destination is an immediate, we have nothing to do.
465  if (MO.isImm()) return MO.getImm();
466  assert(MO.isExpr() && "Unexpected branch target type!");
467  const MCExpr *Expr = MO.getExpr();
468  MCFixupKind Kind = MCFixupKind(FixupKind);
469  Fixups.push_back(MCFixup::Create(0, Expr, Kind));
470
471  // All of the information is in the fixup.
472  return 0;
473}
474
475// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
476// determined by negating them and XOR'ing them with bit 23.
477static int32_t encodeThumbBLOffset(int32_t offset) {
478  offset >>= 1;
479  uint32_t S  = (offset & 0x800000) >> 23;
480  uint32_t J1 = (offset & 0x400000) >> 22;
481  uint32_t J2 = (offset & 0x200000) >> 21;
482  J1 = (~J1 & 0x1);
483  J2 = (~J2 & 0x1);
484  J1 ^= S;
485  J2 ^= S;
486
487  offset &= ~0x600000;
488  offset |= J1 << 22;
489  offset |= J2 << 21;
490
491  return offset;
492}
493
494/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
495uint32_t ARMMCCodeEmitter::
496getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
497                        SmallVectorImpl<MCFixup> &Fixups) const {
498  const MCOperand MO = MI.getOperand(OpIdx);
499  if (MO.isExpr())
500    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
501                                    Fixups);
502  return encodeThumbBLOffset(MO.getImm());
503}
504
505/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
506/// BLX branch target.
507uint32_t ARMMCCodeEmitter::
508getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
509                         SmallVectorImpl<MCFixup> &Fixups) const {
510  const MCOperand MO = MI.getOperand(OpIdx);
511  if (MO.isExpr())
512    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
513                                    Fixups);
514  return encodeThumbBLOffset(MO.getImm());
515}
516
517/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
518uint32_t ARMMCCodeEmitter::
519getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
520                        SmallVectorImpl<MCFixup> &Fixups) const {
521  const MCOperand MO = MI.getOperand(OpIdx);
522  if (MO.isExpr())
523    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
524                                    Fixups);
525  return (MO.getImm() >> 1);
526}
527
528/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
529uint32_t ARMMCCodeEmitter::
530getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
531                         SmallVectorImpl<MCFixup> &Fixups) const {
532  const MCOperand MO = MI.getOperand(OpIdx);
533  if (MO.isExpr())
534    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
535                                    Fixups);
536  return (MO.getImm() >> 1);
537}
538
539/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
540uint32_t ARMMCCodeEmitter::
541getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
542                        SmallVectorImpl<MCFixup> &Fixups) const {
543  const MCOperand MO = MI.getOperand(OpIdx);
544  if (MO.isExpr())
545    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
546  return (MO.getImm() >> 1);
547}
548
549/// Return true if this branch has a non-always predication
550static bool HasConditionalBranch(const MCInst &MI) {
551  int NumOp = MI.getNumOperands();
552  if (NumOp >= 2) {
553    for (int i = 0; i < NumOp-1; ++i) {
554      const MCOperand &MCOp1 = MI.getOperand(i);
555      const MCOperand &MCOp2 = MI.getOperand(i + 1);
556      if (MCOp1.isImm() && MCOp2.isReg() &&
557          (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
558        if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
559          return true;
560      }
561    }
562  }
563  return false;
564}
565
566/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
567/// target.
568uint32_t ARMMCCodeEmitter::
569getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
570                       SmallVectorImpl<MCFixup> &Fixups) const {
571  // FIXME: This really, really shouldn't use TargetMachine. We don't want
572  // coupling between MC and TM anywhere we can help it.
573  if (isThumb2())
574    return
575      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
576  return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
577}
578
579/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
580/// target.
581uint32_t ARMMCCodeEmitter::
582getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
583                          SmallVectorImpl<MCFixup> &Fixups) const {
584  const MCOperand MO = MI.getOperand(OpIdx);
585  if (MO.isExpr()) {
586    if (HasConditionalBranch(MI))
587      return ::getBranchTargetOpValue(MI, OpIdx,
588                                      ARM::fixup_arm_condbranch, Fixups);
589    return ::getBranchTargetOpValue(MI, OpIdx,
590                                    ARM::fixup_arm_uncondbranch, Fixups);
591  }
592
593  return MO.getImm() >> 2;
594}
595
596uint32_t ARMMCCodeEmitter::
597getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
598                          SmallVectorImpl<MCFixup> &Fixups) const {
599  const MCOperand MO = MI.getOperand(OpIdx);
600  if (MO.isExpr()) {
601    if (HasConditionalBranch(MI))
602      return ::getBranchTargetOpValue(MI, OpIdx,
603                                      ARM::fixup_arm_condbranch, Fixups);
604    return ::getBranchTargetOpValue(MI, OpIdx,
605                                    ARM::fixup_arm_uncondbranch, Fixups);
606  }
607
608  return MO.getImm() >> 1;
609}
610
611/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
612/// immediate branch target.
613uint32_t ARMMCCodeEmitter::
614getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
615                       SmallVectorImpl<MCFixup> &Fixups) const {
616  unsigned Val =
617    ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
618  bool I  = (Val & 0x800000);
619  bool J1 = (Val & 0x400000);
620  bool J2 = (Val & 0x200000);
621  if (I ^ J1)
622    Val &= ~0x400000;
623  else
624    Val |= 0x400000;
625
626  if (I ^ J2)
627    Val &= ~0x200000;
628  else
629    Val |= 0x200000;
630
631  return Val;
632}
633
634/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
635/// target.
636uint32_t ARMMCCodeEmitter::
637getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
638                   SmallVectorImpl<MCFixup> &Fixups) const {
639  const MCOperand MO = MI.getOperand(OpIdx);
640  if (MO.isExpr())
641    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
642                                    Fixups);
643  int32_t offset = MO.getImm();
644  uint32_t Val = 0x2000;
645  if (offset < 0) {
646    Val = 0x1000;
647    offset *= -1;
648  }
649  Val |= offset;
650  return Val;
651}
652
653/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
654/// target.
655uint32_t ARMMCCodeEmitter::
656getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
657                   SmallVectorImpl<MCFixup> &Fixups) const {
658  const MCOperand MO = MI.getOperand(OpIdx);
659  if (MO.isExpr())
660    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
661                                    Fixups);
662  int32_t Val = MO.getImm();
663  if (Val < 0) {
664    Val *= -1;
665    Val |= 0x1000;
666  }
667  return Val;
668}
669
670/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
671/// target.
672uint32_t ARMMCCodeEmitter::
673getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
674                   SmallVectorImpl<MCFixup> &Fixups) const {
675  const MCOperand MO = MI.getOperand(OpIdx);
676  if (MO.isExpr())
677    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
678                                    Fixups);
679  return MO.getImm();
680}
681
682/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
683/// operand.
684uint32_t ARMMCCodeEmitter::
685getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
686                              SmallVectorImpl<MCFixup> &) const {
687  // [Rn, Rm]
688  //   {5-3} = Rm
689  //   {2-0} = Rn
690  const MCOperand &MO1 = MI.getOperand(OpIdx);
691  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
692  unsigned Rn = getARMRegisterNumbering(MO1.getReg());
693  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
694  return (Rm << 3) | Rn;
695}
696
697/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
698uint32_t ARMMCCodeEmitter::
699getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
700                        SmallVectorImpl<MCFixup> &Fixups) const {
701  // {17-13} = reg
702  // {12}    = (U)nsigned (add == '1', sub == '0')
703  // {11-0}  = imm12
704  unsigned Reg, Imm12;
705  bool isAdd = true;
706  // If The first operand isn't a register, we have a label reference.
707  const MCOperand &MO = MI.getOperand(OpIdx);
708  if (!MO.isReg()) {
709    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
710    Imm12 = 0;
711    isAdd = false ; // 'U' bit is set as part of the fixup.
712
713    if (MO.isExpr()) {
714      const MCExpr *Expr = MO.getExpr();
715
716      MCFixupKind Kind;
717      if (isThumb2())
718        Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
719      else
720        Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
721      Fixups.push_back(MCFixup::Create(0, Expr, Kind));
722
723      ++MCNumCPRelocations;
724    } else {
725      Reg = ARM::PC;
726      int32_t Offset = MO.getImm();
727      if (Offset < 0) {
728        Offset *= -1;
729        isAdd = false;
730      }
731      Imm12 = Offset;
732    }
733  } else
734    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
735
736  uint32_t Binary = Imm12 & 0xfff;
737  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
738  if (isAdd)
739    Binary |= (1 << 12);
740  Binary |= (Reg << 13);
741  return Binary;
742}
743
744/// getT2Imm8s4OpValue - Return encoding info for
745/// '+/- imm8<<2' operand.
746uint32_t ARMMCCodeEmitter::
747getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
748                   SmallVectorImpl<MCFixup> &Fixups) const {
749  // FIXME: The immediate operand should have already been encoded like this
750  // before ever getting here. The encoder method should just need to combine
751  // the MI operands for the register and the offset into a single
752  // representation for the complex operand in the .td file. This isn't just
753  // style, unfortunately. As-is, we can't represent the distinct encoding
754  // for #-0.
755
756  // {8}    = (U)nsigned (add == '1', sub == '0')
757  // {7-0}  = imm8
758  int32_t Imm8 = MI.getOperand(OpIdx).getImm();
759  bool isAdd = Imm8 >= 0;
760
761  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
762  if (Imm8 < 0)
763    Imm8 = -Imm8;
764
765  // Scaled by 4.
766  Imm8 /= 4;
767
768  uint32_t Binary = Imm8 & 0xff;
769  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
770  if (isAdd)
771    Binary |= (1 << 8);
772  return Binary;
773}
774
775/// getT2AddrModeImm8s4OpValue - Return encoding info for
776/// 'reg +/- imm8<<2' operand.
777uint32_t ARMMCCodeEmitter::
778getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
779                        SmallVectorImpl<MCFixup> &Fixups) const {
780  // {12-9} = reg
781  // {8}    = (U)nsigned (add == '1', sub == '0')
782  // {7-0}  = imm8
783  unsigned Reg, Imm8;
784  bool isAdd = true;
785  // If The first operand isn't a register, we have a label reference.
786  const MCOperand &MO = MI.getOperand(OpIdx);
787  if (!MO.isReg()) {
788    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
789    Imm8 = 0;
790    isAdd = false ; // 'U' bit is set as part of the fixup.
791
792    assert(MO.isExpr() && "Unexpected machine operand type!");
793    const MCExpr *Expr = MO.getExpr();
794    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
795    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
796
797    ++MCNumCPRelocations;
798  } else
799    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
800
801  // FIXME: The immediate operand should have already been encoded like this
802  // before ever getting here. The encoder method should just need to combine
803  // the MI operands for the register and the offset into a single
804  // representation for the complex operand in the .td file. This isn't just
805  // style, unfortunately. As-is, we can't represent the distinct encoding
806  // for #-0.
807  uint32_t Binary = (Imm8 >> 2) & 0xff;
808  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
809  if (isAdd)
810    Binary |= (1 << 8);
811  Binary |= (Reg << 9);
812  return Binary;
813}
814
815/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
816/// 'reg + imm8<<2' operand.
817uint32_t ARMMCCodeEmitter::
818getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
819                        SmallVectorImpl<MCFixup> &Fixups) const {
820  // {11-8} = reg
821  // {7-0}  = imm8
822  const MCOperand &MO = MI.getOperand(OpIdx);
823  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
824  unsigned Reg = getARMRegisterNumbering(MO.getReg());
825  unsigned Imm8 = MO1.getImm();
826  return (Reg << 8) | Imm8;
827}
828
829// FIXME: This routine assumes that a binary
830// expression will always result in a PCRel expression
831// In reality, its only true if one or more subexpressions
832// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
833// but this is good enough for now.
834static bool EvaluateAsPCRel(const MCExpr *Expr) {
835  switch (Expr->getKind()) {
836  default: assert(0 && "Unexpected expression type");
837  case MCExpr::SymbolRef: return false;
838  case MCExpr::Binary: return true;
839  }
840}
841
842uint32_t
843ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
844                                      SmallVectorImpl<MCFixup> &Fixups) const {
845  // {20-16} = imm{15-12}
846  // {11-0}  = imm{11-0}
847  const MCOperand &MO = MI.getOperand(OpIdx);
848  if (MO.isImm())
849    // Hi / lo 16 bits already extracted during earlier passes.
850    return static_cast<unsigned>(MO.getImm());
851
852  // Handle :upper16: and :lower16: assembly prefixes.
853  const MCExpr *E = MO.getExpr();
854  if (E->getKind() == MCExpr::Target) {
855    const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
856    E = ARM16Expr->getSubExpr();
857
858    MCFixupKind Kind;
859    switch (ARM16Expr->getKind()) {
860    default: assert(0 && "Unsupported ARMFixup");
861    case ARMMCExpr::VK_ARM_HI16:
862      if (!isTargetDarwin() && EvaluateAsPCRel(E))
863        Kind = MCFixupKind(isThumb2()
864                           ? ARM::fixup_t2_movt_hi16_pcrel
865                           : ARM::fixup_arm_movt_hi16_pcrel);
866      else
867        Kind = MCFixupKind(isThumb2()
868                           ? ARM::fixup_t2_movt_hi16
869                           : ARM::fixup_arm_movt_hi16);
870      break;
871    case ARMMCExpr::VK_ARM_LO16:
872      if (!isTargetDarwin() && EvaluateAsPCRel(E))
873        Kind = MCFixupKind(isThumb2()
874                           ? ARM::fixup_t2_movw_lo16_pcrel
875                           : ARM::fixup_arm_movw_lo16_pcrel);
876      else
877        Kind = MCFixupKind(isThumb2()
878                           ? ARM::fixup_t2_movw_lo16
879                           : ARM::fixup_arm_movw_lo16);
880      break;
881    }
882    Fixups.push_back(MCFixup::Create(0, E, Kind));
883    return 0;
884  };
885
886  llvm_unreachable("Unsupported MCExpr type in MCOperand!");
887  return 0;
888}
889
890uint32_t ARMMCCodeEmitter::
891getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
892                    SmallVectorImpl<MCFixup> &Fixups) const {
893  const MCOperand &MO = MI.getOperand(OpIdx);
894  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
895  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
896  unsigned Rn = getARMRegisterNumbering(MO.getReg());
897  unsigned Rm = getARMRegisterNumbering(MO1.getReg());
898  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
899  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
900  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
901  unsigned SBits = getShiftOp(ShOp);
902
903  // {16-13} = Rn
904  // {12}    = isAdd
905  // {11-0}  = shifter
906  //  {3-0}  = Rm
907  //  {4}    = 0
908  //  {6-5}  = type
909  //  {11-7} = imm
910  uint32_t Binary = Rm;
911  Binary |= Rn << 13;
912  Binary |= SBits << 5;
913  Binary |= ShImm << 7;
914  if (isAdd)
915    Binary |= 1 << 12;
916  return Binary;
917}
918
919uint32_t ARMMCCodeEmitter::
920getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
921                    SmallVectorImpl<MCFixup> &Fixups) const {
922  // {17-14}  Rn
923  // {13}     1 == imm12, 0 == Rm
924  // {12}     isAdd
925  // {11-0}   imm12/Rm
926  const MCOperand &MO = MI.getOperand(OpIdx);
927  unsigned Rn = getARMRegisterNumbering(MO.getReg());
928  uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
929  Binary |= Rn << 14;
930  return Binary;
931}
932
933uint32_t ARMMCCodeEmitter::
934getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
935                          SmallVectorImpl<MCFixup> &Fixups) const {
936  // {13}     1 == imm12, 0 == Rm
937  // {12}     isAdd
938  // {11-0}   imm12/Rm
939  const MCOperand &MO = MI.getOperand(OpIdx);
940  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
941  unsigned Imm = MO1.getImm();
942  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
943  bool isReg = MO.getReg() != 0;
944  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
945  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
946  if (isReg) {
947    ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
948    Binary <<= 7;                    // Shift amount is bits [11:7]
949    Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
950    Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
951  }
952  return Binary | (isAdd << 12) | (isReg << 13);
953}
954
955uint32_t ARMMCCodeEmitter::
956getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
957                     SmallVectorImpl<MCFixup> &Fixups) const {
958  // {4}      isAdd
959  // {3-0}    Rm
960  const MCOperand &MO = MI.getOperand(OpIdx);
961  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
962  bool isAdd = MO1.getImm() != 0;
963  return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
964}
965
966uint32_t ARMMCCodeEmitter::
967getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
968                          SmallVectorImpl<MCFixup> &Fixups) const {
969  // {9}      1 == imm8, 0 == Rm
970  // {8}      isAdd
971  // {7-4}    imm7_4/zero
972  // {3-0}    imm3_0/Rm
973  const MCOperand &MO = MI.getOperand(OpIdx);
974  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
975  unsigned Imm = MO1.getImm();
976  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
977  bool isImm = MO.getReg() == 0;
978  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
979  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
980  if (!isImm)
981    Imm8 = getARMRegisterNumbering(MO.getReg());
982  return Imm8 | (isAdd << 8) | (isImm << 9);
983}
984
985uint32_t ARMMCCodeEmitter::
986getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
987                    SmallVectorImpl<MCFixup> &Fixups) const {
988  // {13}     1 == imm8, 0 == Rm
989  // {12-9}   Rn
990  // {8}      isAdd
991  // {7-4}    imm7_4/zero
992  // {3-0}    imm3_0/Rm
993  const MCOperand &MO = MI.getOperand(OpIdx);
994  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
995  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
996  unsigned Rn = getARMRegisterNumbering(MO.getReg());
997  unsigned Imm = MO2.getImm();
998  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
999  bool isImm = MO1.getReg() == 0;
1000  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1001  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1002  if (!isImm)
1003    Imm8 = getARMRegisterNumbering(MO1.getReg());
1004  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1005}
1006
1007/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1008uint32_t ARMMCCodeEmitter::
1009getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1010                          SmallVectorImpl<MCFixup> &Fixups) const {
1011  // [SP, #imm]
1012  //   {7-0} = imm8
1013  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1014  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1015         "Unexpected base register!");
1016
1017  // The immediate is already shifted for the implicit zeroes, so no change
1018  // here.
1019  return MO1.getImm() & 0xff;
1020}
1021
1022/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1023uint32_t ARMMCCodeEmitter::
1024getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1025                     SmallVectorImpl<MCFixup> &Fixups) const {
1026  // [Rn, #imm]
1027  //   {7-3} = imm5
1028  //   {2-0} = Rn
1029  const MCOperand &MO = MI.getOperand(OpIdx);
1030  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1031  unsigned Rn = getARMRegisterNumbering(MO.getReg());
1032  unsigned Imm5 = MO1.getImm();
1033  return ((Imm5 & 0x1f) << 3) | Rn;
1034}
1035
1036/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1037uint32_t ARMMCCodeEmitter::
1038getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1039                     SmallVectorImpl<MCFixup> &Fixups) const {
1040  const MCOperand MO = MI.getOperand(OpIdx);
1041  if (MO.isExpr())
1042    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1043  return (MO.getImm() >> 2);
1044}
1045
1046/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1047uint32_t ARMMCCodeEmitter::
1048getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1049                    SmallVectorImpl<MCFixup> &Fixups) const {
1050  // {12-9} = reg
1051  // {8}    = (U)nsigned (add == '1', sub == '0')
1052  // {7-0}  = imm8
1053  unsigned Reg, Imm8;
1054  bool isAdd;
1055  // If The first operand isn't a register, we have a label reference.
1056  const MCOperand &MO = MI.getOperand(OpIdx);
1057  if (!MO.isReg()) {
1058    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
1059    Imm8 = 0;
1060    isAdd = false; // 'U' bit is handled as part of the fixup.
1061
1062    assert(MO.isExpr() && "Unexpected machine operand type!");
1063    const MCExpr *Expr = MO.getExpr();
1064    MCFixupKind Kind;
1065    if (isThumb2())
1066      Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1067    else
1068      Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1069    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
1070
1071    ++MCNumCPRelocations;
1072  } else {
1073    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1074    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1075  }
1076
1077  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1078  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1079  if (isAdd)
1080    Binary |= (1 << 8);
1081  Binary |= (Reg << 9);
1082  return Binary;
1083}
1084
1085unsigned ARMMCCodeEmitter::
1086getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1087                SmallVectorImpl<MCFixup> &Fixups) const {
1088  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1089  // shifted. The second is Rs, the amount to shift by, and the third specifies
1090  // the type of the shift.
1091  //
1092  // {3-0} = Rm.
1093  // {4}   = 1
1094  // {6-5} = type
1095  // {11-8} = Rs
1096  // {7}    = 0
1097
1098  const MCOperand &MO  = MI.getOperand(OpIdx);
1099  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1100  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1101  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1102
1103  // Encode Rm.
1104  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1105
1106  // Encode the shift opcode.
1107  unsigned SBits = 0;
1108  unsigned Rs = MO1.getReg();
1109  if (Rs) {
1110    // Set shift operand (bit[7:4]).
1111    // LSL - 0001
1112    // LSR - 0011
1113    // ASR - 0101
1114    // ROR - 0111
1115    switch (SOpc) {
1116    default: llvm_unreachable("Unknown shift opc!");
1117    case ARM_AM::lsl: SBits = 0x1; break;
1118    case ARM_AM::lsr: SBits = 0x3; break;
1119    case ARM_AM::asr: SBits = 0x5; break;
1120    case ARM_AM::ror: SBits = 0x7; break;
1121    }
1122  }
1123
1124  Binary |= SBits << 4;
1125
1126  // Encode the shift operation Rs.
1127  // Encode Rs bit[11:8].
1128  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1129  return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1130}
1131
1132unsigned ARMMCCodeEmitter::
1133getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1134                SmallVectorImpl<MCFixup> &Fixups) const {
1135  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1136  // shifted. The second is the amount to shift by.
1137  //
1138  // {3-0} = Rm.
1139  // {4}   = 0
1140  // {6-5} = type
1141  // {11-7} = imm
1142
1143  const MCOperand &MO  = MI.getOperand(OpIdx);
1144  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1145  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1146
1147  // Encode Rm.
1148  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1149
1150  // Encode the shift opcode.
1151  unsigned SBits = 0;
1152
1153  // Set shift operand (bit[6:4]).
1154  // LSL - 000
1155  // LSR - 010
1156  // ASR - 100
1157  // ROR - 110
1158  // RRX - 110 and bit[11:8] clear.
1159  switch (SOpc) {
1160  default: llvm_unreachable("Unknown shift opc!");
1161  case ARM_AM::lsl: SBits = 0x0; break;
1162  case ARM_AM::lsr: SBits = 0x2; break;
1163  case ARM_AM::asr: SBits = 0x4; break;
1164  case ARM_AM::ror: SBits = 0x6; break;
1165  case ARM_AM::rrx:
1166    Binary |= 0x60;
1167    return Binary;
1168  }
1169
1170  // Encode shift_imm bit[11:7].
1171  Binary |= SBits << 4;
1172  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1173  assert(Offset && "Offset must be in range 1-32!");
1174  if (Offset == 32) Offset = 0;
1175  return Binary | (Offset << 7);
1176}
1177
1178
1179unsigned ARMMCCodeEmitter::
1180getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1181                SmallVectorImpl<MCFixup> &Fixups) const {
1182  const MCOperand &MO1 = MI.getOperand(OpNum);
1183  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1184  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1185
1186  // Encoded as [Rn, Rm, imm].
1187  // FIXME: Needs fixup support.
1188  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1189  Value <<= 4;
1190  Value |= getARMRegisterNumbering(MO2.getReg());
1191  Value <<= 2;
1192  Value |= MO3.getImm();
1193
1194  return Value;
1195}
1196
1197unsigned ARMMCCodeEmitter::
1198getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1199                         SmallVectorImpl<MCFixup> &Fixups) const {
1200  const MCOperand &MO1 = MI.getOperand(OpNum);
1201  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1202
1203  // FIXME: Needs fixup support.
1204  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1205
1206  // Even though the immediate is 8 bits long, we need 9 bits in order
1207  // to represent the (inverse of the) sign bit.
1208  Value <<= 9;
1209  int32_t tmp = (int32_t)MO2.getImm();
1210  if (tmp < 0)
1211    tmp = abs(tmp);
1212  else
1213    Value |= 256; // Set the ADD bit
1214  Value |= tmp & 255;
1215  return Value;
1216}
1217
1218unsigned ARMMCCodeEmitter::
1219getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1220                         SmallVectorImpl<MCFixup> &Fixups) const {
1221  const MCOperand &MO1 = MI.getOperand(OpNum);
1222
1223  // FIXME: Needs fixup support.
1224  unsigned Value = 0;
1225  int32_t tmp = (int32_t)MO1.getImm();
1226  if (tmp < 0)
1227    tmp = abs(tmp);
1228  else
1229    Value |= 256; // Set the ADD bit
1230  Value |= tmp & 255;
1231  return Value;
1232}
1233
1234unsigned ARMMCCodeEmitter::
1235getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1236                         SmallVectorImpl<MCFixup> &Fixups) const {
1237  const MCOperand &MO1 = MI.getOperand(OpNum);
1238
1239  // FIXME: Needs fixup support.
1240  unsigned Value = 0;
1241  int32_t tmp = (int32_t)MO1.getImm();
1242  if (tmp < 0)
1243    tmp = abs(tmp);
1244  else
1245    Value |= 4096; // Set the ADD bit
1246  Value |= tmp & 4095;
1247  return Value;
1248}
1249
1250unsigned ARMMCCodeEmitter::
1251getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1252                SmallVectorImpl<MCFixup> &Fixups) const {
1253  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1254  // shifted. The second is the amount to shift by.
1255  //
1256  // {3-0} = Rm.
1257  // {4}   = 0
1258  // {6-5} = type
1259  // {11-7} = imm
1260
1261  const MCOperand &MO  = MI.getOperand(OpIdx);
1262  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1263  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1264
1265  // Encode Rm.
1266  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1267
1268  // Encode the shift opcode.
1269  unsigned SBits = 0;
1270  // Set shift operand (bit[6:4]).
1271  // LSL - 000
1272  // LSR - 010
1273  // ASR - 100
1274  // ROR - 110
1275  switch (SOpc) {
1276  default: llvm_unreachable("Unknown shift opc!");
1277  case ARM_AM::lsl: SBits = 0x0; break;
1278  case ARM_AM::lsr: SBits = 0x2; break;
1279  case ARM_AM::asr: SBits = 0x4; break;
1280  case ARM_AM::rrx: // FALLTHROUGH
1281  case ARM_AM::ror: SBits = 0x6; break;
1282  }
1283
1284  Binary |= SBits << 4;
1285  if (SOpc == ARM_AM::rrx)
1286    return Binary;
1287
1288  // Encode shift_imm bit[11:7].
1289  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1290}
1291
1292unsigned ARMMCCodeEmitter::
1293getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1294                               SmallVectorImpl<MCFixup> &Fixups) const {
1295  // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1296  // msb of the mask.
1297  const MCOperand &MO = MI.getOperand(Op);
1298  uint32_t v = ~MO.getImm();
1299  uint32_t lsb = CountTrailingZeros_32(v);
1300  uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1301  assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1302  return lsb | (msb << 5);
1303}
1304
1305unsigned ARMMCCodeEmitter::
1306getRegisterListOpValue(const MCInst &MI, unsigned Op,
1307                       SmallVectorImpl<MCFixup> &Fixups) const {
1308  // VLDM/VSTM:
1309  //   {12-8} = Vd
1310  //   {7-0}  = Number of registers
1311  //
1312  // LDM/STM:
1313  //   {15-0}  = Bitfield of GPRs.
1314  unsigned Reg = MI.getOperand(Op).getReg();
1315  bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1316  bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1317
1318  unsigned Binary = 0;
1319
1320  if (SPRRegs || DPRRegs) {
1321    // VLDM/VSTM
1322    unsigned RegNo = getARMRegisterNumbering(Reg);
1323    unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1324    Binary |= (RegNo & 0x1f) << 8;
1325    if (SPRRegs)
1326      Binary |= NumRegs;
1327    else
1328      Binary |= NumRegs * 2;
1329  } else {
1330    for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1331      unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1332      Binary |= 1 << RegNo;
1333    }
1334  }
1335
1336  return Binary;
1337}
1338
1339/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1340/// with the alignment operand.
1341unsigned ARMMCCodeEmitter::
1342getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1343                           SmallVectorImpl<MCFixup> &Fixups) const {
1344  const MCOperand &Reg = MI.getOperand(Op);
1345  const MCOperand &Imm = MI.getOperand(Op + 1);
1346
1347  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1348  unsigned Align = 0;
1349
1350  switch (Imm.getImm()) {
1351  default: break;
1352  case 2:
1353  case 4:
1354  case 8:  Align = 0x01; break;
1355  case 16: Align = 0x02; break;
1356  case 32: Align = 0x03; break;
1357  }
1358
1359  return RegNo | (Align << 4);
1360}
1361
1362/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1363/// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1364unsigned ARMMCCodeEmitter::
1365getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1366                                    SmallVectorImpl<MCFixup> &Fixups) const {
1367  const MCOperand &Reg = MI.getOperand(Op);
1368  const MCOperand &Imm = MI.getOperand(Op + 1);
1369
1370  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1371  unsigned Align = 0;
1372
1373  switch (Imm.getImm()) {
1374  default: break;
1375  case 2:
1376  case 4:
1377  case 8:
1378  case 16: Align = 0x00; break;
1379  case 32: Align = 0x03; break;
1380  }
1381
1382  return RegNo | (Align << 4);
1383}
1384
1385
1386/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1387/// alignment operand for use in VLD-dup instructions.  This is the same as
1388/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1389/// different for VLD4-dup.
1390unsigned ARMMCCodeEmitter::
1391getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1392                              SmallVectorImpl<MCFixup> &Fixups) const {
1393  const MCOperand &Reg = MI.getOperand(Op);
1394  const MCOperand &Imm = MI.getOperand(Op + 1);
1395
1396  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1397  unsigned Align = 0;
1398
1399  switch (Imm.getImm()) {
1400  default: break;
1401  case 2:
1402  case 4:
1403  case 8:  Align = 0x01; break;
1404  case 16: Align = 0x03; break;
1405  }
1406
1407  return RegNo | (Align << 4);
1408}
1409
1410unsigned ARMMCCodeEmitter::
1411getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1412                          SmallVectorImpl<MCFixup> &Fixups) const {
1413  const MCOperand &MO = MI.getOperand(Op);
1414  if (MO.getReg() == 0) return 0x0D;
1415  return MO.getReg();
1416}
1417
1418unsigned ARMMCCodeEmitter::
1419getShiftRight8Imm(const MCInst &MI, unsigned Op,
1420                  SmallVectorImpl<MCFixup> &Fixups) const {
1421  return 8 - MI.getOperand(Op).getImm();
1422}
1423
1424unsigned ARMMCCodeEmitter::
1425getShiftRight16Imm(const MCInst &MI, unsigned Op,
1426                   SmallVectorImpl<MCFixup> &Fixups) const {
1427  return 16 - MI.getOperand(Op).getImm();
1428}
1429
1430unsigned ARMMCCodeEmitter::
1431getShiftRight32Imm(const MCInst &MI, unsigned Op,
1432                   SmallVectorImpl<MCFixup> &Fixups) const {
1433  return 32 - MI.getOperand(Op).getImm();
1434}
1435
1436unsigned ARMMCCodeEmitter::
1437getShiftRight64Imm(const MCInst &MI, unsigned Op,
1438                   SmallVectorImpl<MCFixup> &Fixups) const {
1439  return 64 - MI.getOperand(Op).getImm();
1440}
1441
1442void ARMMCCodeEmitter::
1443EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1444                  SmallVectorImpl<MCFixup> &Fixups) const {
1445  // Pseudo instructions don't get encoded.
1446  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1447  uint64_t TSFlags = Desc.TSFlags;
1448  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1449    return;
1450
1451  int Size;
1452  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1453    Size = Desc.getSize();
1454  else
1455    llvm_unreachable("Unexpected instruction size!");
1456
1457  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1458  // Thumb 32-bit wide instructions need to emit the high order halfword
1459  // first.
1460  if (isThumb() && Size == 4) {
1461    EmitConstant(Binary >> 16, 2, OS);
1462    EmitConstant(Binary & 0xffff, 2, OS);
1463  } else
1464    EmitConstant(Binary, Size, OS);
1465  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1466}
1467
1468#include "ARMGenMCCodeEmitter.inc"
1469