1//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the interface of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef X86RECOGNIZABLEINSTR_H
18#define X86RECOGNIZABLEINSTR_H
19
20#include "X86DisassemblerTables.h"
21
22#include "CodeGenTarget.h"
23
24#include "llvm/TableGen/Record.h"
25#include "llvm/Support/DataTypes.h"
26#include "llvm/ADT/SmallVector.h"
27
28namespace llvm {
29
30namespace X86Disassembler {
31
32/// RecognizableInstr - Encapsulates all information required to decode a single
33///   instruction, as extracted from the LLVM instruction tables.  Has methods
34///   to interpret the information available in the LLVM tables, and to emit the
35///   instruction into DisassemblerTables.
36class RecognizableInstr {
37private:
38  /// The opcode of the instruction, as used in an MCInst
39  InstrUID UID;
40  /// The record from the .td files corresponding to this instruction
41  const Record* Rec;
42  /// The prefix field from the record
43  uint8_t Prefix;
44  /// The opcode field from the record; this is the opcode used in the Intel
45  /// encoding and therefore distinct from the UID
46  uint8_t Opcode;
47  /// The form field from the record
48  uint8_t Form;
49  /// The segment override field from the record
50  uint8_t SegOvr;
51  /// The hasOpSizePrefix field from the record
52  bool HasOpSizePrefix;
53  /// The hasREX_WPrefix field from the record
54  bool HasREX_WPrefix;
55  /// The hasVEXPrefix field from the record
56  bool HasVEXPrefix;
57  /// The hasVEX_4VPrefix field from the record
58  bool HasVEX_4VPrefix;
59  /// The hasVEX_WPrefix field from the record
60  bool HasVEX_WPrefix;
61  /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
62  bool HasVEX_LPrefix;
63  // The ignoreVEX_L field from the record
64  bool IgnoresVEX_L;
65  /// The hasLockPrefix field from the record
66  bool HasLockPrefix;
67  /// The isCodeGenOnly filed from the record
68  bool IsCodeGenOnly;
69  // Whether the instruction has the predicate "In64BitMode"
70  bool Is64Bit;
71  // Whether the instruction has the predicate "In32BitMode"
72  bool Is32Bit;
73
74  /// The instruction name as listed in the tables
75  std::string Name;
76  /// The AT&T AsmString for the instruction
77  std::string AsmString;
78
79  /// Indicates whether the instruction is SSE
80  bool IsSSE;
81  /// Indicates whether the instruction has FR operands - MOVs with FR operands
82  /// are typically ignored
83  bool HasFROperands;
84  /// Indicates whether the instruction should be emitted into the decode
85  /// tables; regardless, it will be emitted into the instruction info table
86  bool ShouldBeEmitted;
87
88  /// The operands of the instruction, as listed in the CodeGenInstruction.
89  /// They are not one-to-one with operands listed in the MCInst; for example,
90  /// memory operands expand to 5 operands in the MCInst
91  const std::vector<CGIOperandList::OperandInfo>* Operands;
92
93  /// The description of the instruction that is emitted into the instruction
94  /// info table
95  InstructionSpecifier* Spec;
96
97  /// insnContext - Returns the primary context in which the instruction is
98  ///   valid.
99  ///
100  /// @return - The context in which the instruction is valid.
101  InstructionContext insnContext() const;
102
103  enum filter_ret {
104    FILTER_STRONG,    // instruction has no place in the instruction tables
105    FILTER_WEAK,      // instruction may conflict, and should be eliminated if
106                      // it does
107    FILTER_NORMAL     // instruction should have high priority and generate an
108                      // error if it conflcits with any other FILTER_NORMAL
109                      // instruction
110  };
111
112  /// filter - Determines whether the instruction should be decodable.  Some
113  ///   instructions are pure intrinsics and use unencodable operands; many
114  ///   synthetic instructions are duplicates of other instructions; other
115  ///   instructions only differ in the logical way in which they are used, and
116  ///   have the same decoding.  Because these would cause decode conflicts,
117  ///   they must be filtered out.
118  ///
119  /// @return - The degree of filtering to be applied (see filter_ret).
120  filter_ret filter() const;
121
122  /// hasFROperands - Returns true if any operand is a FR operand.
123  bool hasFROperands() const;
124
125  /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.
126  bool has256BitOperands() const;
127
128  /// typeFromString - Translates an operand type from the string provided in
129  ///   the LLVM tables to an OperandType for use in the operand specifier.
130  ///
131  /// @param s              - The string, as extracted by calling Rec->getName()
132  ///                         on a CodeGenInstruction::OperandInfo.
133  /// @param isSSE          - Indicates whether the instruction is an SSE
134  ///                         instruction.  For SSE instructions, immediates are
135  ///                         fixed-size rather than being affected by the
136  ///                         mandatory OpSize prefix.
137  /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
138  ///                         prefix.  If it does, 32-bit register operands stay
139  ///                         32-bit regardless of the operand size.
140  /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
141  ///                         prefix.  If it does not, then 16-bit register
142  ///                         operands stay 16-bit.
143  /// @return               - The operand's type.
144  static OperandType typeFromString(const std::string& s,
145                                    bool isSSE,
146                                    bool hasREX_WPrefix,
147                                    bool hasOpSizePrefix);
148
149  /// immediateEncodingFromString - Translates an immediate encoding from the
150  ///   string provided in the LLVM tables to an OperandEncoding for use in
151  ///   the operand specifier.
152  ///
153  /// @param s                - See typeFromString().
154  /// @param hasOpSizePrefix  - Indicates whether the instruction has an OpSize
155  ///                           prefix.  If it does not, then 16-bit immediate
156  ///                           operands stay 16-bit.
157  /// @return                 - The operand's encoding.
158  static OperandEncoding immediateEncodingFromString(const std::string &s,
159                                                     bool hasOpSizePrefix);
160
161  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
162  ///   handles operands that are in the REG field of the ModR/M byte.
163  static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
164                                                      bool hasOpSizePrefix);
165
166  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
167  ///   handles operands that are in the REG field of the ModR/M byte.
168  static OperandEncoding roRegisterEncodingFromString(const std::string &s,
169                                                      bool hasOpSizePrefix);
170  static OperandEncoding memoryEncodingFromString(const std::string &s,
171                                                  bool hasOpSizePrefix);
172  static OperandEncoding relocationEncodingFromString(const std::string &s,
173                                                      bool hasOpSizePrefix);
174  static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
175                                                          bool hasOpSizePrefix);
176  static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
177                                                        bool HasOpSizePrefix);
178
179  /// handleOperand - Converts a single operand from the LLVM table format to
180  ///   the emitted table format, handling any duplicate operands it encounters
181  ///   and then one non-duplicate.
182  ///
183  /// @param optional             - Determines whether to assert that the
184  ///                               operand exists.
185  /// @param operandIndex         - The index into the generated operand table.
186  ///                               Incremented by this function one or more
187  ///                               times to reflect possible duplicate
188  ///                               operands).
189  /// @param physicalOperandIndex - The index of the current operand into the
190  ///                               set of non-duplicate ('physical') operands.
191  ///                               Incremented by this function once.
192  /// @param numPhysicalOperands  - The number of non-duplicate operands in the
193  ///                               instructions.
194  /// @param operandMapping       - The operand mapping, which has an entry for
195  ///                               each operand that indicates whether it is a
196  ///                               duplicate, and of what.
197  void handleOperand(bool optional,
198                     unsigned &operandIndex,
199                     unsigned &physicalOperandIndex,
200                     unsigned &numPhysicalOperands,
201                     unsigned *operandMapping,
202                     OperandEncoding (*encodingFromString)
203                       (const std::string&,
204                        bool hasOpSizePrefix));
205
206  /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
207  ///   filters out many instructions, at various points in decoding we
208  ///   determine that the instruction should not actually be decodable.  In
209  ///   particular, MMX MOV instructions aren't emitted, but they're only
210  ///   identified during operand parsing.
211  ///
212  /// @return - true if at this point we believe the instruction should be
213  ///   emitted; false if not.  This will return false if filter() returns false
214  ///   once emitInstructionSpecifier() has been called.
215  bool shouldBeEmitted() const {
216    return ShouldBeEmitted;
217  }
218
219  /// emitInstructionSpecifier - Loads the instruction specifier for the current
220  ///   instruction into a DisassemblerTables.
221  ///
222  /// @arg tables - The DisassemblerTables to populate with the specifier for
223  ///               the current instruction.
224  void emitInstructionSpecifier(DisassemblerTables &tables);
225
226  /// emitDecodePath - Populates the proper fields in the decode tables
227  ///   corresponding to the decode paths for this instruction.
228  ///
229  /// @arg tables - The DisassemblerTables to populate with the decode
230  ///               decode information for the current instruction.
231  void emitDecodePath(DisassemblerTables &tables) const;
232
233  /// Constructor - Initializes a RecognizableInstr with the appropriate fields
234  ///   from a CodeGenInstruction.
235  ///
236  /// @arg tables - The DisassemblerTables that the specifier will be added to.
237  /// @arg insn   - The CodeGenInstruction to extract information from.
238  /// @arg uid    - The unique ID of the current instruction.
239  RecognizableInstr(DisassemblerTables &tables,
240                    const CodeGenInstruction &insn,
241                    InstrUID uid);
242public:
243  /// processInstr - Accepts a CodeGenInstruction and loads decode information
244  ///   for it into a DisassemblerTables if appropriate.
245  ///
246  /// @arg tables - The DiassemblerTables to be populated with decode
247  ///               information.
248  /// @arg insn   - The CodeGenInstruction to be used as a source for this
249  ///               information.
250  /// @uid        - The unique ID of the instruction.
251  static void processInstr(DisassemblerTables &tables,
252                           const CodeGenInstruction &insn,
253                           InstrUID uid);
254};
255
256} // namespace X86Disassembler
257
258} // namespace llvm
259
260#endif
261