1/* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34FILE_LICENCE ( GPL2_ONLY ); 35 36#ifndef H_MTNIC_IF_DEFS_H 37#define H_MTNIC_IF_DEFS_H 38 39 40 41/* 42* Device setup 43*/ 44#define MTNIC_MAX_PORTS 2 45#define MTNIC_PORT1 0 46#define MTNIC_PORT2 1 47#define NUM_TX_RINGS 1 48#define NUM_RX_RINGS 1 49#define NUM_CQS (NUM_RX_RINGS + NUM_TX_RINGS) 50#define GO_BIT_TIMEOUT 6000 51#define TBIT_RETRIES 100 52#define UNITS_BUFFER_SIZE 8 /* can be configured to 4/8/16 */ 53#define MAX_GAP_PROD_CONS ( UNITS_BUFFER_SIZE / 4 ) 54#define ETH_DEF_LEN 1540 /* 40 bytes used by the card */ 55#define ETH_FCS_LEN 14 56#define DEF_MTU ETH_DEF_LEN + ETH_FCS_LEN 57#define DEF_IOBUF_SIZE ETH_DEF_LEN 58 59#define MAC_ADDRESS_SIZE 6 60#define NUM_EQES 16 61#define ROUND_TO_CHECK 0x400 62 63#define DELAY_LINK_CHECK 300 64#define CHECK_LINK_TIMES 7 65 66 67#define XNOR(x,y) (!(x) == !(y)) 68#define dma_addr_t unsigned long 69#define PAGE_SIZE 4096 70#define PAGE_MASK (PAGE_SIZE - 1) 71#define MTNIC_MAILBOX_SIZE PAGE_SIZE 72 73 74 75 76/* BITOPS */ 77#define MTNIC_BC_OFF(bc) ((bc) >> 8) 78#define MTNIC_BC_SZ(bc) ((bc) & 0xff) 79#define MTNIC_BC_ONES(size) (~((int)0x80000000 >> (31 - size))) 80#define MTNIC_BC_MASK(bc) \ 81 (MTNIC_BC_ONES(MTNIC_BC_SZ(bc)) << MTNIC_BC_OFF(bc)) 82#define MTNIC_BC_VAL(val, bc) \ 83 (((val) & MTNIC_BC_ONES(MTNIC_BC_SZ(bc))) << MTNIC_BC_OFF(bc)) 84/* 85 * Sub word fields - bit code base extraction/setting etc 86 */ 87 88/* Encode two values */ 89#define MTNIC_BC(off, size) ((off << 8) | (size & 0xff)) 90 91/* Get value of field 'bc' from 'x' */ 92#define MTNIC_BC_GET(x, bc) \ 93 (((x) >> MTNIC_BC_OFF(bc)) & MTNIC_BC_ONES(MTNIC_BC_SZ(bc))) 94 95/* Set value of field 'bc' of 'x' to 'val' */ 96#define MTNIC_BC_SET(x, val, bc) \ 97 ((x) = ((x) & ~MTNIC_BC_MASK(bc)) | MTNIC_BC_VAL(val, bc)) 98 99/* Like MTNIC_BC_SET, except the previous value is assumed to be 0 */ 100#define MTNIC_BC_PUT(x, val, bc) ((x) |= MTNIC_BC_VAL(val, bc)) 101 102 103 104/* 105 * Device constants 106 */ 107typedef enum mtnic_if_cmd { 108 /* NIC commands: */ 109 MTNIC_IF_CMD_QUERY_FW = 0x004, /* query FW (size, version, etc) */ 110 MTNIC_IF_CMD_MAP_FW = 0xfff, /* map pages for FW image */ 111 MTNIC_IF_CMD_RUN_FW = 0xff6, /* run the FW */ 112 MTNIC_IF_CMD_QUERY_CAP = 0x001, /* query MTNIC capabilities */ 113 MTNIC_IF_CMD_MAP_PAGES = 0x002, /* map physical pages to HW */ 114 MTNIC_IF_CMD_OPEN_NIC = 0x003, /* run the firmware */ 115 MTNIC_IF_CMD_CONFIG_RX = 0x005, /* general receive configuration */ 116 MTNIC_IF_CMD_CONFIG_TX = 0x006, /* general transmit configuration */ 117 MTNIC_IF_CMD_CONFIG_INT_FREQ = 0x007, /* interrupt timers freq limits */ 118 MTNIC_IF_CMD_HEART_BEAT = 0x008, /* NOP command testing liveliness */ 119 MTNIC_IF_CMD_CLOSE_NIC = 0x009, /* release memory and stop the NIC */ 120 121 /* Port commands: */ 122 MTNIC_IF_CMD_CONFIG_PORT_RSS_STEER = 0x10, /* set RSS mode */ 123 MTNIC_IF_CMD_SET_PORT_RSS_INDIRECTION = 0x11, /* set RSS indirection tbl */ 124 MTNIC_IF_CMD_CONFIG_PORT_PRIO_STEERING = 0x12, /* set PRIORITY mode */ 125 MTNIC_IF_CMD_CONFIG_PORT_ADDR_STEER = 0x13, /* set Address steer mode */ 126 MTNIC_IF_CMD_CONFIG_PORT_VLAN_FILTER = 0x14, /* configure VLAN filter */ 127 MTNIC_IF_CMD_CONFIG_PORT_MCAST_FILTER = 0x15, /* configure mcast filter */ 128 MTNIC_IF_CMD_ENABLE_PORT_MCAST_FILTER = 0x16, /* enable/disable */ 129 MTNIC_IF_CMD_SET_PORT_MTU = 0x17, /* set port MTU */ 130 MTNIC_IF_CMD_SET_PORT_PROMISCUOUS_MODE = 0x18, /* enable/disable promisc */ 131 MTNIC_IF_CMD_SET_PORT_DEFAULT_RING = 0x19, /* set the default ring */ 132 MTNIC_IF_CMD_SET_PORT_STATE = 0x1a, /* set link up/down */ 133 MTNIC_IF_CMD_DUMP_STAT = 0x1b, /* dump statistics */ 134 MTNIC_IF_CMD_ARM_PORT_STATE_EVENT = 0x1c, /* arm the port state event */ 135 136 /* Ring / Completion queue commands: */ 137 MTNIC_IF_CMD_CONFIG_CQ = 0x20, /* set up completion queue */ 138 MTNIC_IF_CMD_CONFIG_RX_RING = 0x21, /* setup Rx ring */ 139 MTNIC_IF_CMD_SET_RX_RING_ADDR = 0x22, /* set Rx ring filter by address */ 140 MTNIC_IF_CMD_SET_RX_RING_MCAST = 0x23, /* set Rx ring mcast filter */ 141 MTNIC_IF_CMD_ARM_RX_RING_WM = 0x24, /* one-time low-watermark INT */ 142 MTNIC_IF_CMD_CONFIG_TX_RING = 0x25, /* set up Tx ring */ 143 MTNIC_IF_CMD_ENFORCE_TX_RING_ADDR = 0x26, /* setup anti spoofing */ 144 MTNIC_IF_CMD_CONFIG_EQ = 0x27, /* config EQ ring */ 145 MTNIC_IF_CMD_RELEASE_RESOURCE = 0x28, /* release internal ref to resource */ 146} 147mtnic_if_cmd_t; 148 149 150/** selectors for MTNIC_IF_CMD_QUERY_CAP */ 151typedef enum mtnic_if_caps { 152 MTNIC_IF_CAP_MAX_TX_RING_PER_PORT = 0x0, 153 MTNIC_IF_CAP_MAX_RX_RING_PER_PORT = 0x1, 154 MTNIC_IF_CAP_MAX_CQ_PER_PORT = 0x2, 155 MTNIC_IF_CAP_NUM_PORTS = 0x3, 156 MTNIC_IF_CAP_MAX_TX_DESC = 0x4, 157 MTNIC_IF_CAP_MAX_RX_DESC = 0x5, 158 MTNIC_IF_CAP_MAX_CQES = 0x6, 159 MTNIC_IF_CAP_MAX_TX_SG_ENTRIES = 0x7, 160 MTNIC_IF_CAP_MAX_RX_SG_ENTRIES = 0x8, 161 MTNIC_IF_CAP_MEM_KEY = 0x9, /* key to mem (after map_pages) */ 162 MTNIC_IF_CAP_RSS_HASH_TYPE = 0xa, /* one of mtnic_if_rss_types_t */ 163 MTNIC_IF_CAP_MAX_PORT_UCAST_ADDR = 0xc, 164 MTNIC_IF_CAP_MAX_RING_UCAST_ADDR = 0xd, /* only for ADDR steer */ 165 MTNIC_IF_CAP_MAX_PORT_MCAST_ADDR = 0xe, 166 MTNIC_IF_CAP_MAX_RING_MCAST_ADDR = 0xf, /* only for ADDR steer */ 167 MTNIC_IF_CAP_INTA = 0x10, 168 MTNIC_IF_CAP_BOARD_ID_LOW = 0x11, 169 MTNIC_IF_CAP_BOARD_ID_HIGH = 0x12, 170 MTNIC_IF_CAP_TX_CQ_DB_OFFSET = 0x13, /* offset in bytes for TX, CQ doorbell record */ 171 MTNIC_IF_CAP_EQ_DB_OFFSET = 0x14, /* offset in bytes for EQ doorbell record */ 172 173 /* These are per port - using port number from cap modifier field */ 174 MTNIC_IF_CAP_SPEED = 0x20, 175 MTNIC_IF_CAP_DEFAULT_MAC = 0x21, 176 MTNIC_IF_CAP_EQ_OFFSET = 0x22, 177 MTNIC_IF_CAP_CQ_OFFSET = 0x23, 178 MTNIC_IF_CAP_TX_OFFSET = 0x24, 179 MTNIC_IF_CAP_RX_OFFSET = 0x25, 180 181} mtnic_if_caps_t; 182 183typedef enum mtnic_if_steer_types { 184 MTNIC_IF_STEER_NONE = 0, 185 MTNIC_IF_STEER_PRIORITY = 1, 186 MTNIC_IF_STEER_RSS = 2, 187 MTNIC_IF_STEER_ADDRESS = 3, 188} mtnic_if_steer_types_t; 189 190/** types of memory access modes */ 191typedef enum mtnic_if_memory_types { 192 MTNIC_IF_MEM_TYPE_SNOOP = 1, 193 MTNIC_IF_MEM_TYPE_NO_SNOOP = 2 194} mtnic_if_memory_types_t; 195 196 197enum { 198 MTNIC_HCR_BASE = 0x1f000, 199 MTNIC_HCR_SIZE = 0x0001c, 200 MTNIC_CLR_INT_SIZE = 0x00008, 201}; 202 203#define MTNIC_RESET_OFFSET 0xF0010 204 205 206 207/******************************************************************** 208* Device private data structures 209* 210* This section contains structures of all device private data: 211* descriptors, rings, CQs, EQ .... 212* 213* 214*********************************************************************/ 215/* 216 * Descriptor format 217 */ 218struct mtnic_ctrl_seg { 219 u32 op_own; 220#define MTNIC_BIT_DESC_OWN 0x80000000 221#define MTNIC_OPCODE_SEND 0xa 222 u32 size_vlan; 223 u32 flags; 224#define MTNIC_BIT_NO_ICRC 0x2 225#define MTNIC_BIT_TX_COMP 0xc 226 u32 reserved; 227}; 228 229struct mtnic_data_seg { 230 u32 count; 231#define MTNIC_INLINE 0x80000000 232 u32 mem_type; 233#define MTNIC_MEMTYPE_PAD 0x100 234 u32 addr_h; 235 u32 addr_l; 236}; 237 238struct mtnic_tx_desc { 239 struct mtnic_ctrl_seg ctrl; 240 struct mtnic_data_seg data; /* at least one data segment */ 241}; 242 243struct mtnic_rx_desc { 244 u16 reserved1; 245 u16 next; 246 u32 reserved2[3]; 247 struct mtnic_data_seg data; /* actual number of entries depends on 248 * rx ring stride */ 249}; 250 251/* 252 * Rings 253 */ 254struct mtnic_rx_db_record { 255 u32 count; 256}; 257 258struct mtnic_ring { 259 u32 size; /* REMOVE ____cacheline_aligned_in_smp; *//* number of Rx descs or TXBBs */ 260 u32 size_mask; 261 u16 stride; 262 u16 cq; /* index of port CQ associated with this ring */ 263 u32 prod; 264 u32 cons; /* holds the last consumed index */ 265 266 /* Buffers */ 267 u32 buf_size; /* ring buffer size in bytes */ 268 dma_addr_t dma; 269 void *buf; 270 struct io_buffer *iobuf[UNITS_BUFFER_SIZE]; 271 272 /* Tx only */ 273 struct mtnic_txcq_db *txcq_db; 274 u32 db_offset; 275 276 /* Rx ring only */ 277 dma_addr_t iobuf_dma; 278 struct mtnic_rx_db_record *db; 279 dma_addr_t db_dma; 280}; 281 282/* 283 * CQ 284 */ 285 286struct mtnic_cqe { 287 u8 vp; /* VLAN present */ 288 u8 reserved1[3]; 289 u32 rss_hash; 290 u32 reserved2; 291 u16 vlan_prio; 292 u16 reserved3; 293 u8 flags_h; 294 u8 flags_l_rht; 295 u8 ipv6_mask; 296 u8 enc_bf; 297#define MTNIC_BIT_BAD_FCS 0x10 298#define MTNIC_OPCODE_ERROR 0x1e 299 u32 byte_cnt; 300 u16 index; 301 u16 chksum; 302 u8 reserved4[3]; 303 u8 op_tr_own; 304#define MTNIC_BIT_CQ_OWN 0x80 305}; 306 307 308struct mtnic_cq_db_record { 309 u32 update_ci; 310 u32 cmd_ci; 311}; 312 313struct mtnic_cq { 314 int num; /* CQ number (on attached port) */ 315 u32 size; /* number of CQEs in CQ */ 316 u32 last; /* number of CQEs consumed */ 317 struct mtnic_cq_db_record *db; 318 struct net_device *dev; 319 320 dma_addr_t db_dma; 321 u8 is_rx; 322 u16 ring; /* ring associated with this CQ */ 323 u32 offset_ind; 324 325 /* CQE ring */ 326 u32 buf_size; /* ring size in bytes */ 327 struct mtnic_cqe *buf; 328 dma_addr_t dma; 329}; 330 331/* 332 * EQ 333 */ 334 335struct mtnic_eqe { 336 u8 reserved1; 337 u8 type; 338 u8 reserved2; 339 u8 subtype; 340 u8 reserved3[3]; 341 u8 ring_cq; 342 u32 reserved4; 343 u8 port; 344#define MTNIC_MASK_EQE_PORT MTNIC_BC(4,2) 345 u8 reserved5[2]; 346 u8 syndrome; 347 u8 reserved6[15]; 348 u8 own; 349#define MTNIC_BIT_EQE_OWN 0x80 350}; 351 352struct mtnic_eq { 353 u32 size; /* number of EQEs in ring */ 354 u32 buf_size; /* EQ size in bytes */ 355 void *buf; 356 dma_addr_t dma; 357}; 358 359enum mtnic_state { 360 CARD_DOWN, 361 CARD_INITIALIZED, 362 CARD_UP, 363 CARD_LINK_DOWN, 364}; 365 366/* FW */ 367struct mtnic_pages { 368 u32 num; 369 u32 *buf; 370}; 371struct mtnic_err_buf { 372 u64 offset; 373 u32 size; 374}; 375 376 377 378struct mtnic_cmd { 379 void *buf; 380 unsigned long mapping; 381 u32 tbit; 382}; 383 384 385struct mtnic_txcq_db { 386 u32 reserved1[5]; 387 u32 send_db; 388 u32 reserved2[2]; 389 u32 cq_arm; 390 u32 cq_ci; 391}; 392 393 394 395/* 396 * Device private data 397 * 398 */ 399struct mtnic { 400 struct net_device *netdev[MTNIC_MAX_PORTS]; 401 struct mtnic_if_cmd_reg *hcr; 402 struct mtnic_cmd cmd; 403 struct pci_device *pdev; 404 405 struct mtnic_eq eq; 406 u32 *eq_db; 407 408 /* Firmware and board info */ 409 u64 fw_ver; 410 struct { 411 struct mtnic_pages fw_pages; 412 struct mtnic_pages extra_pages; 413 struct mtnic_err_buf err_buf; 414 u16 ifc_rev; 415 u8 num_ports; 416 u64 mac[MTNIC_MAX_PORTS]; 417 u16 cq_offset; 418 u16 tx_offset[MTNIC_MAX_PORTS]; 419 u16 rx_offset[MTNIC_MAX_PORTS]; 420 u32 mem_type_snoop_be; 421 u32 txcq_db_offset; 422 u32 eq_db_offset; 423 } fw; 424}; 425 426 427 428 429 430struct mtnic_port { 431 432 struct mtnic *mtnic; 433 u8 port; 434 435 enum mtnic_state state; 436 437 /* TX, RX, CQs, EQ */ 438 struct mtnic_ring tx_ring; 439 struct mtnic_ring rx_ring; 440 struct mtnic_cq cq[NUM_CQS]; 441 u32 poll_counter; 442 struct net_device *netdev; 443 444 445}; 446 447 448 449 450 451 452 453 454 455 456 457 458/*************************************************************************** 459 * NIC COMMANDS 460 * 461 * The section below provides struct definition for commands parameters, 462 * and arguments values enumeration. 463 * 464 * The format used for the struct names is: 465 * mtnic_if_<cmd name>_<in|out>_<imm|mbox> 466 * 467 ***************************************************************************/ 468/** 469 * Command Register (Command interface) 470 */ 471struct mtnic_if_cmd_reg { 472 unsigned long in_param_h; 473 u32 in_param_l; 474 u32 input_modifier; 475 u32 out_param_h; 476 u32 out_param_l; 477 u32 token; 478#define MTNIC_MASK_CMD_REG_TOKEN MTNIC_BC(16,32) 479 u32 status_go_opcode; 480#define MTNIC_MASK_CMD_REG_OPCODE MTNIC_BC(0,16) 481#define MTNIC_MASK_CMD_REG_T_BIT MTNIC_BC(21,1) 482#define MTNIC_MASK_CMD_REG_GO_BIT MTNIC_BC(23,1) 483#define MTNIC_MASK_CMD_REG_STATUS MTNIC_BC(24,8) 484}; 485 486 487 488/* CMD QUERY_FW */ 489struct mtnic_if_query_fw_out_mbox { 490 u16 fw_pages; /* Total number of memory pages the device requires */ 491 u16 rev_maj; 492 u16 rev_smin; 493 u16 rev_min; 494 u16 reserved1; 495 u16 ifc_rev; /* major revision of the command interface */ 496 u8 ft; 497 u8 reserved2[3]; 498 u32 reserved3[4]; 499 u64 clr_int_base; 500 u32 reserved4[2]; 501 u64 err_buf_start; 502 u32 err_buf_size; 503}; 504 505/* CMD MTNIC_IF_CMD_QUERY_CAP */ 506struct mtnic_if_query_cap_in_imm { 507 u16 reserved1; 508 u8 cap_modifier; /* a modifier for the particular capability */ 509 u8 cap_index; /* the index of the capability queried */ 510 u32 reserved2; 511}; 512 513/* CMD OPEN_NIC */ 514struct mtnic_if_open_nic_in_mbox { 515 u16 reserved1; 516 u16 mkey; /* number of mem keys for all chip*/ 517 u32 mkey_entry; /* mem key entries for each key*/ 518 u8 log_rx_p1; /* log2 rx rings for port1 */ 519 u8 log_cq_p1; /* log2 cq for port1 */ 520 u8 log_tx_p1; /* log2 tx rings for port1 */ 521 u8 steer_p1; /* port 1 steering mode */ 522 u16 reserved2; 523 u8 log_vlan_p1; /* log2 vlan per rx port1 */ 524 u8 log_mac_p1; /* log2 mac per rx port1 */ 525 526 u8 log_rx_p2; /* log2 rx rings for port1 */ 527 u8 log_cq_p2; /* log2 cq for port1 */ 528 u8 log_tx_p2; /* log2 tx rings for port1 */ 529 u8 steer_p2; /* port 1 steering mode */ 530 u16 reserved3; 531 u8 log_vlan_p2; /* log2 vlan per rx port1 */ 532 u8 log_mac_p2; /* log2 mac per rx port1 */ 533}; 534 535 536/* CMD CONFIG_RX */ 537struct mtnic_if_config_rx_in_imm { 538 u16 spkt_size; /* size of small packets interrupts enabled on CQ */ 539 u16 resp_rcv_pause_frm_mcast_vlan_comp; /* Two flags see MASK below */ 540 /* Enable response to receive pause frames */ 541 /* Use VLAN in exact-match multicast checks (see SET_RX_RING_MCAST) */ 542}; 543 544/* CMD CONFIG_TX */ 545struct mtnic_if_config_send_in_imm { 546 u32 enph_gpf; /* Enable PseudoHeader and GeneratePauseFrames flags */ 547 u32 reserved; 548}; 549 550/* CMD HEART_BEAT */ 551struct mtnic_if_heart_beat_out_imm { 552 u32 flags; /* several flags */ 553#define MTNIC_MASK_HEAR_BEAT_INT_ERROR MTNIC_BC(31,1) 554 u32 reserved; 555}; 556 557 558/* 559 * PORT COMMANDS 560 */ 561/* CMD CONFIG_PORT_VLAN_FILTER */ 562/* in mbox is a 4K bits mask - bit per VLAN */ 563struct mtnic_if_config_port_vlan_filter_in_mbox { 564 u64 filter[64]; /* vlans[63:0] sit in filter[0], vlans[127:64] sit in filter[1] .. */ 565}; 566 567 568/* CMD SET_PORT_MTU */ 569struct mtnic_if_set_port_mtu_in_imm { 570 u16 reserved1; 571 u16 mtu; /* The MTU of the port in bytes */ 572 u32 reserved2; 573}; 574 575/* CMD SET_PORT_DEFAULT_RING */ 576struct mtnic_if_set_port_default_ring_in_imm { 577 u8 reserved1[3]; 578 u8 ring; /* Index of ring that collects promiscuous traffic */ 579 u32 reserved2; 580}; 581 582/* CMD SET_PORT_STATE */ 583struct mtnic_if_set_port_state_in_imm { 584 u32 state; /* if 1 the port state should be up */ 585#define MTNIC_MASK_CONFIG_PORT_STATE MTNIC_BC(0,1) 586 u32 reserved; 587}; 588 589/* CMD CONFIG_CQ */ 590struct mtnic_if_config_cq_in_mbox { 591 u8 reserved1; 592 u8 cq; 593 u8 size; /* Num CQs is 2^size (size <= 22) */ 594 u8 offset; /* start address of CQE in first page (11:6) */ 595 u16 tlast; /* interrupt moderation timer from last completion usec */ 596 u8 flags; /* flags */ 597 u8 int_vector; /* MSI index if MSI is enabled, otherwise reserved */ 598 u16 reserved2; 599 u16 max_cnt; /* interrupt moderation counter */ 600 u8 page_size; /* each mapped page is 2^(12+page_size) bytes */ 601 u8 reserved4[3]; 602 u32 db_record_addr_h; /*physical address of CQ doorbell record */ 603 u32 db_record_addr_l; /*physical address of CQ doorbell record */ 604 u32 page_address[0]; /* 64 bit page addresses of CQ buffer */ 605}; 606 607/* CMD CONFIG_RX_RING */ 608struct mtnic_if_config_rx_ring_in_mbox { 609 u8 reserved1; 610 u8 ring; /* The ring index (with offset) */ 611 u8 stride_size; /* stride and size */ 612 /* Entry size = 16* (2^stride) bytes */ 613#define MTNIC_MASK_CONFIG_RX_RING_STRIDE MTNIC_BC(4,3) 614 /* Rx ring size is 2^size entries */ 615#define MTNIC_MASK_CONFIG_RX_RING_SIZE MTNIC_BC(0,4) 616 u8 flags; /* Bit0 - header separation */ 617 u8 page_size; /* Each mapped page is 2^(12+page_size) bytes */ 618 u8 reserved2[2]; 619 u8 cq; /* CQ associated with this ring */ 620 u32 db_record_addr_h; 621 u32 db_record_addr_l; 622 u32 page_address[0];/* Array of 2^size 64b page descriptor addresses */ 623 /* Must hold all Rx descriptors + doorbell record. */ 624}; 625 626/* The modifier for SET_RX_RING_ADDR */ 627struct mtnic_if_set_rx_ring_modifier { 628 u8 reserved; 629 u8 port_num; 630 u8 index; 631 u8 ring; 632}; 633 634/* CMD SET_RX_RING_ADDR */ 635struct mtnic_if_set_rx_ring_addr_in_imm { 636 u16 mac_47_32; /* UCAST MAC Address bits 47:32 */ 637 u16 flags_vlan_id; /* MAC/VLAN flags and vlan id */ 638#define MTNIC_MASK_SET_RX_RING_ADDR_VLAN_ID MTNIC_BC(0,12) 639#define MTNIC_MASK_SET_RX_RING_ADDR_BY_MAC MTNIC_BC(12,1) 640#define MTNIC_MASK_SET_RX_RING_ADDR_BY_VLAN MTNIC_BC(13,1) 641 u32 mac_31_0; /* UCAST MAC Address bits 31:0 */ 642}; 643 644/* CMD CONFIG_TX_RING */ 645struct mtnic_if_config_send_ring_in_mbox { 646 u16 ring; /* The ring index (with offset) */ 647#define MTNIC_MASK_CONFIG_TX_RING_INDEX MTNIC_BC(0,8) 648 u8 size; /* Tx ring size is 32*2^size bytes */ 649#define MTNIC_MASK_CONFIG_TX_RING_SIZE MTNIC_BC(0,4) 650 u8 reserved; 651 u8 page_size; /* Each mapped page is 2^(12+page_size) bytes */ 652 u8 qos_class; /* The COS used for this Tx */ 653 u16 cq; /* CQ associated with this ring */ 654#define MTNIC_MASK_CONFIG_TX_CQ_INDEX MTNIC_BC(0,8) 655 u32 page_address[0]; /* 64 bit page addresses of descriptor buffer. */ 656 /* The buffer must accommodate all Tx descriptors */ 657}; 658 659/* CMD CONFIG_EQ */ 660struct mtnic_if_config_eq_in_mbox { 661 u8 reserved1; 662 u8 int_vector; /* MSI index if MSI enabled; otherwise reserved */ 663#define MTNIC_MASK_CONFIG_EQ_INT_VEC MTNIC_BC(0,6) 664 u8 size; /* Num CQs is 2^size entries (size <= 22) */ 665#define MTNIC_MASK_CONFIG_EQ_SIZE MTNIC_BC(0,5) 666 u8 offset; /* Start address of CQE in first page (11:6) */ 667#define MTNIC_MASK_CONFIG_EQ_OFFSET MTNIC_BC(0,6) 668 u8 page_size; /* Each mapped page is 2^(12+page_size) bytes*/ 669 u8 reserved[3]; 670 u32 page_address[0]; /* 64 bit page addresses of EQ buffer */ 671}; 672 673/* CMD RELEASE_RESOURCE */ 674enum mtnic_if_resource_types { 675 MTNIC_IF_RESOURCE_TYPE_CQ = 0, 676 MTNIC_IF_RESOURCE_TYPE_RX_RING, 677 MTNIC_IF_RESOURCE_TYPE_TX_RING, 678 MTNIC_IF_RESOURCE_TYPE_EQ 679}; 680 681struct mtnic_if_release_resource_in_imm { 682 u8 reserved1; 683 u8 index; /* must be 0 for TYPE_EQ */ 684 u8 reserved2; 685 u8 type; /* see enum mtnic_if_resource_types */ 686 u32 reserved3; 687}; 688 689 690 691 692 693 694 695 696 697/******************************************************************* 698* 699* PCI addon structures 700* 701********************************************************************/ 702 703struct pcidev { 704 unsigned long bar[6]; 705 u32 dev_config_space[64]; 706 struct pci_device *dev; 707 u8 bus; 708 u8 devfn; 709}; 710 711struct dev_pci_struct { 712 struct pcidev dev; 713 struct pcidev br; 714}; 715 716/* The only global var */ 717struct dev_pci_struct mtnic_pci_dev; 718 719 720 721#endif /* H_MTNIC_IF_DEFS_H */ 722 723