| 0f689e773c49536208d40a2e23410deea4acc184 |
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02-Oct-2017 |
Vladimir Marko <vmarko@google.com> |
ARM/ARM64: Move simplifier visitors to .cc files.
Test: Rely on TreeHugger.
Change-Id: Ib2cad20a4d6252812aaf6fa09a576bdfca423b70
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| 74234daabb28a4b9c804bf8bf908e7334bd4d400 |
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13-Jan-2017 |
Anton Kirilov <anton.kirilov@linaro.org> |
ARM: Merge data-processing instructions and shifts/(un)signed extensions
This commit mirrors the work that has already been done for ARM64.
Test: m test-art-target-run-test-551-checker-shifter-operand
Change-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8
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| 7fa7cf59540f36fbfce6d5b553d11ca486a3f207 |
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04-Nov-2016 |
Roland Levillain <rpl@google.com> |
Fix ART run-test 562-no-intermediate.
- Rename it to 562-checker-no-intermediate, so that Checker
assertions are actually verified.
- Fix Checker assertions, as they did not match the
code expected from the compiler.
- Have the test use an integer array (instead of a double
array), so that Checker assertions can be extended to ARM
as well (the ARM back end does not support the
IntermediateAddress instruction on long, float and double
arrays).
Test: make test-art-target-run-test-562-checker-no-intermediate
Bug: 30888043
Change-Id: I32c891948c585983d5fe5d6df092bc7a59c19ae6
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| 5319d3cca5a9b8e9e3f59421818272b966575172 |
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02-Aug-2016 |
Wojciech Staszkiewicz <staszkiewicz@google.com> |
Implement running user defined list of passes
This change introduces new dex2oat switch --run-passes=. This switch
accepts path to a text file with names of passes to run.
Compiler will run optimization passes specified in the file rather
then the default ones.
There is no verification implemented on the compiler side. It is user's
responsibility to provide a list of passes that leads to successful
generation of correct code. Care should be taken to prepare a list
that satisfies all dependencies between optimizations.
We only take control of the optional optimizations. Codegen (builder),
and all passes required for register allocation will run unaffected
by this mechanism.
Change-Id: Ic3694e53515fefcc5ce6f28d9371776b5afcbb4f
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| 328429ff48d06e2cad4ebdd3568ab06de916a10a |
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06-Jul-2016 |
Artem Serov <artem.serov@linaro.org> |
ARM: Port instr simplification of array accesses.
After changing the addressing mode for array accesses (in
https://android-review.googlesource.com/248406) the 'add'
instruction that calculates the base address for the array can be
shared across accesses to the same array.
Before https://android-review.googlesource.com/248406:
add IP, r[Array], r[Index0], LSL #2
ldr r0, [IP, #12]
add IP, r[Array], r[Index1], LSL #2
ldr r0, [IP, #12]
Before this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
add IP. r[Array], #12
ldr r0, [IP, r[Index1], LSL #2]
After this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
ldr r0, [IP, r[Index1], LSL #2]
Link to the original optimization:
https://android-review.googlesource.com/#/c/127310/
Test: Run ART test suite on Nexus 6.
Change-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f
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| 7fc6350f6f1ab04b52b9cd7542e0790528296cbe |
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09-Feb-2016 |
Artem Serov <artem.serov@linaro.org> |
Integrate BitwiseNegated into shared framework.
Share implementation between arm and arm64.
Change-Id: I0dd12e772cb23b4c181fd0b1e2a447470b1d8702
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| 4a0dad67867f389e01a5a6c0fe381d210f687c0d |
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25-Jan-2016 |
Artem Udovichenko <artem.u@samsung.com> |
Revert "Revert "ARM/ARM64: Extend support of instruction combining.""
This reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.
Change-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6
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| 6b5afdd144d2bb3bf994240797834b5666b2cf98 |
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22-Jan-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "ARM/ARM64: Extend support of instruction combining."
The test fails its checker parts.
This reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.
Change-Id: I49929e15950c7814da6c411ecd2b640d12de80df
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| debeb98aaa8950caf1a19df490f2ac9bf563075b |
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11-Dec-2015 |
Ilmir Usmanov <i.usmanov@samsung.com> |
ARM/ARM64: Extend support of instruction combining.
Combine multiply instructions in the following way:
ARM64:
MUL/NEG -> MNEG
ARM32 (32-bit integers only):
MUL/ADD -> MLA
MUL/SUB -> MLS
Change-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb
|