History log of /art/compiler/utils/arm64/assembler_arm64.h
Revision Date Author Comments
57943810cfc789da890d73621741729da5feaaf8 07-Dec-2017 Andreas Gampe <agampe@google.com> ART: Replace base/logging with android-base/logging

Replace wherever possible. ART's base/logging is now mainly VLOG
and initialization code that is unnecessary to pull in and makes
changes to verbose logging more painful than they have to be.

Test: m test-art-host
Change-Id: I3e3a4672ba5b621e57590a526c7d1c8b749e4f6e
e764d2e50c544c2cb98ee61a15d613161ac6bd17 05-Oct-2017 Vladimir Marko <vmarko@google.com> Use ScopedArenaAllocator for register allocation.

Memory needed to compile the two most expensive methods for
aosp_angler-userdebug boot image:
BatteryStats.dumpCheckinLocked() : 25.1MiB -> 21.1MiB
BatteryStats.dumpLocked(): 49.6MiB -> 42.0MiB
This is because all the memory previously used by Scheduler
is reused by the register allocator; the register allocator
has a higher peak usage of the ArenaStack.

And continue the "arena"->"allocator" renaming.

Test: m test-art-host-gtest
Test: testrunner.py --host
Bug: 64312607
Change-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01
2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40 06-Jun-2017 Roland Levillain <rpl@google.com> Instrument ARM64 generated code to check the Marking Register.

Generate run-time code in the Optimizing compiler checking that
the Marking Register's value matches `self.tls32_.is.gc_marking`
in debug mode (on target; and on host with JIT, or with AOT when
compiling the core image). If a check fails, abort.

Test: m test-art-target
Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false
Test: ARM64 device boot test with libartd.
Bug: 37707231
Change-Id: Ie9b322b22b3d26654a06821e1db71dbda3c43061
8cf9cb386cd9286d67e879f1ee501ec00d72a4e1 19-Jul-2017 Andreas Gampe <agampe@google.com> ART: Include cleanup

Let clang-format reorder the header includes.

Derived with:

* .clang-format:
BasedOnStyle: Google
IncludeIsMainRegex: '(_test|-inl)?$'

* Steps:
find . -name '*.cc' -o -name '*.h' | xargs sed -i.bak -e 's/^#include/ #include/' ; git commit -a -m 'ART: Include cleanup'
git-clang-format -style=file HEAD^
manual inspection
git commit -a --amend

Test: mmma art
Change-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02
0b671c0408e98824e1f92b1ee951b210c090fe7a 19-Aug-2016 Roland Levillain <rpl@google.com> Add support for Baker read barriers in SystemArrayCopy intrinsics.

Benchmarks (ARM64) score variations on Nexus 5X with CPU
cores clamped at 960000 Hz (aosp_bullhead-userdebug build):
- Ritzperf - average (lower is better): -3.03% (slightly better)
- CaffeineMark - average (higher is better): +1.26% (slightly better)
- DeltaBlue (lower is better): -10.50% (better)
- Richards - average (lower is better): -3.36% (slightly better)
- SciMark2 - average (higher is better): +0.26% (virtually unchanged)

Details about Ritzperf benchmarks with meaningful variations
(lower is better):
- FormulaEvaluationActions.EvaluateAndApplyChanges: -13.26% (better)
- FormulaEvaluationActions.EvaluateCascadingSums: -10.94% (better)
- FormulaEvaluationActions.EvaluateComplexFormulas: -15.50% (better)
- FormulaEvaluationActions.EvaluateFibonacci: -10.41% (better)
- FormulaEvaluationActions.EvaluateLargeSums: +6.02% (worse)

Boot image code size variation on Nexus 5X
(aosp_bullhead-userdebug build):
- total ARM64 framework Oat files size change:
107047632 bytes -> 107154128 bytes (+0.10%)
- total ARM framework Oat files size change:
90932028 bytes -> 91009852 bytes (+0.09%)

Test: ART host and target (ARM, ARM64) tests + Nexus 5X boot.
Bug: 29516905
Bug: 29506760
Bug: 12687968
Change-Id: I85431368d09965687a0301ae2eb3c991f276ce5d
af4e42a0d210aa3aa5d52926536b2ca5c2952934 08-Aug-2016 Artem Serov <artem.serov@linaro.org> ARM64: VIXL: Support a newer version of VIXL.

Please note that compiling VIXL with -Wshadow is a known VIXL issue.

This will be resolved in a later version of VIXL, when we can drop
the deprecated API for getters and setters.

For more info take a look at VIXL_DEPRECATED in the VIXL source code.

Change-Id: Iea30b1a7b065f9b16a92c6cc7ebdc50ef068b348
dcf3014718d9542927a4c8dc93701ce892484c84 09-Aug-2016 Andreas Gampe <agampe@google.com> ART: Extract JNI macro assembler for arm64

Extract the JNI assembler parts from the regular assembler.

Change-Id: I0b0ad32e18f585b75e9da0237afe082c25a1d291
Test: m test-art-target (N9)
3b165bc53c2f063e3a9c644d0edc7bc30c634884 02-Aug-2016 Andreas Gampe <agampe@google.com> ART: Extract macro assembler

Extract macro assembler functionality used by the JNI compiler from
the assembler interface. Templatize the new interface so that
type safety ensures correct usage.

Change-Id: Idb9f56e5b87e43ee6a7378853d8a9f01abe156b2
Test: m test-art-host
087930f2be5a628c65db280a73fecf468899d983 02-Aug-2016 Alexandre Rames <alexandre.rames@linaro.org> ARM64: Make the VIXL macro assembler part of ART ARM64's assembler.

This avoids a dynamic allocation of the VIXL macro assembler.

Change-Id: I4cd62678d0978f1ad6f32ea0ce7279e09152be38
542451cc546779f5c67840e105c51205a1b0a8fd 26-Jul-2016 Andreas Gampe <agampe@google.com> ART: Convert pointer size to enum

Move away from size_t to dedicated enum (class).

Bug: 30373134
Bug: 30419309
Test: m test-art-host
Change-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269
97c72b76cf776228196c6abd33973ef751de61ad 24-Jun-2016 Scott Wakeling <scott.wakeling@linaro.org> Fixes to build against new VIXL interface.

- Fix namespace usage and use of deprecated functions.
- Link all dependants to new libvixl-arm64 target for now.

Change-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509
3224838dfe9c95330ad963286f2c47e9546d3b5c 19-May-2016 Vladimir Marko <vmarko@google.com> Clean up JNI calling convention callee saves.

Precalculate callee saves at compile time and return them
as ArrayRef<> instead of keeping then in a std::vector<>.

Change-Id: I4fd7d2bbf6138dc31b0fe8554eac35b0777ec9ef
c393d63aa2b8f6984672fdd4de631bbeff14b6a2 15-Apr-2016 Alexandre Rames <alexandre.rames@linaro.org> Fix: correctly destruct VIXL labels.

(cherry picked from commit c01a66465a398ad15da90ab2bdc35b7f4a609b17)

Bug: 27505766
Change-Id: I077465e3d308f4331e7a861902e05865f9d99835
d1ee80948144526b985afb44a0574248cf7da58a 13-Apr-2016 Vladimir Marko <vmarko@google.com> Move Assemblers to the Arena.

And clean up some APIs to return std::unique_ptr<> instead
of raw pointers that don't communicate ownership.

(cherry picked from commit 93205e395f777c1dd81d3f164cf9a4aec4bde45f)

Bug: 27505766
Change-Id: I3017302307a0253d661240750298802fb0d9585e
c01a66465a398ad15da90ab2bdc35b7f4a609b17 15-Apr-2016 Alexandre Rames <alexandre.rames@linaro.org> Fix: correctly destruct VIXL labels.

Bug: 27505766
Change-Id: I077465e3d308f4331e7a861902e05865f9d99835
93205e395f777c1dd81d3f164cf9a4aec4bde45f 13-Apr-2016 Vladimir Marko <vmarko@google.com> Move Assemblers to the Arena.

And clean up some APIs to return std::unique_ptr<> instead
of raw pointers that don't communicate ownership.

Change-Id: I3017302307a0253d661240750298802fb0d9585e
85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d 09-Sep-2015 Andreas Gampe <agampe@google.com> ART: Refactor intrinsics slow-paths

Refactor slow paths so that there is a default implementation for
common cases (only arm64 with vixl is special). Write a generic
intrinsic slow-path that can be reused for the specific architectures.
Move helper functions into CodeGenerator so that they are accessible.

Change-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550
3887c468d731420e929e6ad3acf190d5431e94fc 12-Aug-2015 Roland Levillain <rpl@google.com> Remove unnecessary `explicit` qualifiers on constructors.

Change-Id: Id12e392ad50f66a6e2251a68662b7959315dc567
4d02711ea578dbb789abb30cbaf12f9926e13d81 01-Jul-2015 Roland Levillain <rpl@google.com> Implement heap poisoning in ART's Optimizing compiler.

- Instrument ARM, ARM64, x86 and x86-64 code generators.
- Note: To turn heap poisoning on in Optimizing, set the
environment variable `ART_HEAP_POISONING' to "true"
before compiling ART.

Bug: 12687968
Change-Id: Ib3120b38cf805a8a50207a314b9ccc90c8d93740
eb7b7399dbdb5e471b8ae00a567bf4f19edd3907 19-Jun-2015 Alexandre Rames <alexandre.rames@linaro.org> Opt compiler: Add disassembly to the '.cfg' output.

This is automatically added to the '.cfg' output when using the usual
`--dump-cfg` option.

Change-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb
cf93a5cd9c978f59113d42f9f642fab5e2cc8877 16-Jun-2015 Vladimir Marko <vmarko@google.com> Revert "Revert "ART: Implement literal pool for arm, fix branch fixup.""

This reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.

Adjust block label positions. Bad catch block labels were the
reason for the revert.

Change-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310
fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98 16-Jun-2015 Vladimir Marko <vmarko@google.com> Revert "ART: Implement literal pool for arm, fix branch fixup."

This reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.

Change-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40
Reason: broke the tests.
f38caa68cce551fb153dff37d01db518e58ed00f 29-May-2015 Vladimir Marko <vmarko@google.com> ART: Implement literal pool for arm, fix branch fixup.

Change-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7
3d21bdf8894e780d349c481e5c9e29fe1556051c 22-Apr-2015 Mathieu Chartier <mathieuc@google.com> Move mirror::ArtMethod to native

Optimizing + quick tests are passing, devices boot.

TODO: Test and fix bugs in mips64.

Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.
Some of the savings are from removal of virtual methods and direct
methods object arrays.

Bug: 19264997

(cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33)

Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d

Fix some ArtMethod related bugs

Added root visiting for runtime methods, not currently required
since the GcRoots in these methods are null.

Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes
--trace run-tests 005, 044.

Fixed optimizing compiler bug where we used a normal stack location
instead of double on ARM64, this fixes the debuggable tests.

TODO: Fix JDWP tests.

Bug: 19264997

Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3

ART: Fix casts for 64-bit pointers on 32-bit compiler.

Bug: 19264997
Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457

Fix JDWP tests after ArtMethod change

Fixes Throwable::GetStackDepth for exception event detection after
internal stack trace representation change.

Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of
proxy method.

Bug: 19264997
Change-Id: I363e293796848c3ec491c963813f62d868da44d2

Fix accidental IMT and root marking regression

Was always using the conflict trampoline. Also included fix for
regression in GC time caused by extra roots. Most of the regression
was IMT.

Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to
detached thread.

EvaluateAndApplyChanges:
From ~2500 -> ~1980
GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots

Bug: 19264997
Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0

Fix bogus image test assert

Previously we were comparing the size of the non moving space to
size of the image file.

Now we properly compare the size of the image space against the size
of the image file.

Bug: 19264997
Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a

[MIPS64] Fix art_quick_invoke_stub argument offsets.

ArtMethod reference's size got bigger, so we need to move other args
and leave enough space for ArtMethod* and 'this' pointer.

This fixes mips64 boot.

Bug: 19264997
Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
e401d146407d61eeb99f8d6176b2ac13c4df1e33 22-Apr-2015 Mathieu Chartier <mathieuc@google.com> Move mirror::ArtMethod to native

Optimizing + quick tests are passing, devices boot.

TODO: Test and fix bugs in mips64.

Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.
Some of the savings are from removal of virtual methods and direct
methods object arrays.

Bug: 19264997
Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d
41b175aba41c9365a1c53b8a1afbd17129c87c14 19-May-2015 Vladimir Marko <vmarko@google.com> ART: Clean up arm64 kNumberOfXRegisters usage.

Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.

Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.

Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.

Bug: 13925192

(cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0)

Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
80afd02024d20e60b197d3adfbb43cc303cf29e0 19-May-2015 Vladimir Marko <vmarko@google.com> ART: Clean up arm64 kNumberOfXRegisters usage.

Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.

Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.

Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.

Bug: 13925192
Change-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7
2cebb24bfc3247d3e9be138a3350106737455918 22-Apr-2015 Mathieu Chartier <mathieuc@google.com> Replace NULL with nullptr

Also fixed some lines that were too long, and a few other minor
details.

Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d 14-Apr-2015 Zheng Xu <zheng.xu@arm.com> ARM64: Remove suspend register.

It also clean up build/remove frame used by JNI compiler and generates
stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and
optimizing compiler.

Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
65b798ea10dd716c1bb3dda029f9bf255435af72 06-Apr-2015 Andreas Gampe <agampe@google.com> ART: Enable more Clang warnings

Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
82e52ce8364e3e1c644d0d3b3b4f61364bf7089a 26-Mar-2015 Serban Constantinescu <serban.constantinescu@arm.com> ARM64: Update to VIXL 1.9.

Update VIXL's interface to VIXL 1.9.

Change-Id: Iebae947539cbad65488b7195aaf01de284b71cbb
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
277ccbd200ea43590dfc06a93ae184a765327ad0 04-Nov-2014 Andreas Gampe <agampe@google.com> ART: More warnings

Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,
and -Wunused-but-set-parameter for GCC builds.

Change-Id: I81bbdd762213444673c65d85edae594a523836e5
5319defdf502fc4569316473846b83180ec08035 23-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> ART: optimizing compiler: initial support for ARM64.

The ARM64 port uses VIXL for code generation, to which it defers work
like label binding and branch resolving, register type coherency
checking, and immediate values handling.

Change-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
37c92df53979f9f6ab83155ab9521d554d717161 17-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> Rename arm64 `Register` to `XRegister`.

This will avoid naming conflicts in the arm64 port of
the optimizing compiler.

Change-Id: Ie736ddd2ddbd2e299058256de28bad5d41c57d6f
a304f97c97d38af73afe6b49259ac4faf0902123 17-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> Rework arm64 register codes and fix Arm64ManagedRegister tests.

Change-Id: I81ce3bc8a212c9c35be3a41b182ada87b32391ec
13735955f39b3b304c37d2b2840663c131262c18 08-Oct-2014 Ian Rogers <irogers@google.com> stdint types all the way!

Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
cee7524afa53216fcd13df8122ece495548a829c 08-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> ARM64: Update code after the VIXL 1.6 release.

We now leave the assembler buffer management to VIXL.

Change-Id: Ieefe83cf5cf5e1ab8c924b0e7dc03af6a55053ae
c8ccf68b805c92674545f63e0341ba47e8d9701c 30-Sep-2014 Andreas Gampe <agampe@google.com> ART: Fix some -Wpedantic errors

Remove extra semicolons.

Dollar signs in C++ identifiers are an extension.

Named variadic macros are an extension.

Binary literals are a C++14 feature.

Enum re-declarations are not allowed.

Overflow.

Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
ba9388c14381400bcc3f6bc327331fbaca12602a 22-Aug-2014 Alexandre Rames <alexandre.rames@arm.com> ARM64: Avoid the duplication of condition codes.
700a402244a1a423da4f3ba8032459f4b65fa18f 20-May-2014 Ian Rogers <irogers@google.com> Now we have a proper C++ library, use std::unique_ptr.

Also remove the Android.libcxx.mk and other bits of stlport compatibility
mechanics.

Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
507dfdd147c97bfbadebfd63584d094b6a4e7b47 16-May-2014 Ian Rogers <irogers@google.com> Compatibility layer to transition from UniquePtr to std::unique_ptr.

Use ART_WITH_STLPORT (enabled for the target) to cause the use of UniquePtr,
for the host switch to std::unique_ptr. For now the type remains called
UniquePtr.
Make dalvik compile with clang on the host, move its build to C++11.

Change-Id: I5ba8d2757904bc089ed62047ea03de3c0853fb12
eb8167a4f4d27fce0530f6724ab8032610cd146b 08-May-2014 Mathieu Chartier <mathieuc@google.com> Add Handle/HandleScope and delete SirtRef.

Delete SirtRef and replaced it with Handle. Handles are value types
which wrap around StackReference*.

Renamed StackIndirectReferenceTable to HandleScope.

Added a scoped handle wrapper which wraps around an Object** and
restores it in its destructor.

Renamed Handle::get -> Get.

Bug: 8473721

Change-Id: Idbfebd4f35af629f0f43931b7c5184b334822c7a
0f89dac7336251f7921621a926319d461837840f 08-May-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Fix the usage of IP0, IP1 as temporary registers

This patch fixes the usage of temporary registers by using VIXL's
UseScratchRegisterScope. For the primitives used by the trampoline
compiler we explicitly exclude IP0, IP1 from the temporary list.

Change-Id: Icf9afbabd93214302891ddd536ce03a9c181463b
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
75b9113b2b0a5807043af2a669a93d1579af8e2c 09-Apr-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Jni compiler fixes

This patch fixes some of the issues with the ARM64 assembler and JNI
compiler.

The JNI compiler is not enabled by default, yet. To enable, change
line 1884 in compiler/driver/compiler_driver.cc, removing kArm64 from
the GenericJNI list.

The compiler passes all tests in jni_compiler_test.

Also change the common_compiler_test instruction-set-features logic.
We allow tests when the build-time features are a subset of the
runtime features.

Dex2oat cross-compiling is now working. A 32b version of dex2oat should
be able to compile correctly.

Change-Id: I51d1c24f2c75d4397a11c54724a8b277ff3b3df8
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
15523731549152276f23dcf94d81b1a9ce9c5038 02-Apr-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Fix Managed Register unit tests

Fixes the XZR change introduced by one of the previous patches. It
also adds extra testing for VIXL register integration.

Change-Id: I4935f06726e25829613ef7bb6ac052d82056812c
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
44e135459e30286d7cb2a1f21680edaa84f2e171 03-Apr-2014 Andreas Gampe <agampe@google.com> Do not output ARM64 assembler debug code.

This breaks the run tests, which are a simple diff against an
expected output. Please do such changes in a local change.

Change-Id: Ib961919600ba79eca1356278bc6c09ca17041c7c
dd7624d2b9e599d57762d12031b10b89defc9807 15-Mar-2014 Ian Rogers <irogers@google.com> Allow mixing of thread offsets between 32 and 64bit architectures.

Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.

Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
fca82208f7128fcda09b6a4743199308332558a2 21-Mar-2014 Dmitry Petrochenko <dmitry.petrochenko@intel.com> x86_64: JNI compiler

Passed all tests from jni_compiler_test and art/test on host with jni_copiler.
Incoming argument spill is enabled, entry_spills refactored. Now each entry spill
contains data type size (4 or 8) and offset which should be used for spill.
Assembler REX support implemented in opcodes used in JNI compiler.
Please note, JNI compiler is not enabled by default yet (see compiler_driver.cc:1875).

Change-Id: I5fd19cca72122b197aec07c3708b1e80c324be44
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
c6ee54e9a9fd67d24c63bd802ef2fe540a4f86a5 25-Mar-2014 Andreas Gampe <agampe@google.com> Trampoline and assembly fixes for ARM64

Trampolines need a jump, not a call. Expose br in the ARM64
assembler to allow this.

The resolution trampoline is called with the Quick ABI, and will
continue to a Quick ABI function. Then the method pointer must be
in x0.

Change-Id: I4e383b59d6c40a659d324a7faef3fadf0c890178
b95a5345ae4217b70ca36f0cced92f68dda7caf5 12-Mar-2014 Stuart Monteith <stuart.monteith@arm.com> AArch64: Add arm64 runtime support.

Adds support for arm64 to ART. Assembler stubs are sufficient for
down calls into interpreter. JNI compiler and generics are not finished.

Basic Generic JNI functionality.

Change-Id: I4a07c79d1e037b9f5746673480e32cf456867b82
ed8dd492e43cbaaa435c4892447072c84dbaf2dc 11-Feb-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Add ARM64 Assembler

This patch adds the ARM64 Assembler and ManagedRegister backend.
The implementation of the Arm64Assembler class is based on VIXL (a
programmatic A64 Assembler - see external/vixl ).

Change-Id: I842fd574637a953c19631eedf26f6c70d9ed7f9e
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>