| 97c46466aea25ab63a99b3d1afc558f0d9f55abb |
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11-May-2017 |
Roland Levillain <rpl@google.com> |
Introduce a Marking Register in ARM64 code generation.
When generating code for ARM64, maintain the status of
Thread::Current()->GetIsGcMarking() in register X20,
dubbed MR (Marking Register), and check the value of that
register (instead of loading and checking a read barrier
marking entrypoint) in read barriers.
Test: m test-art-target
Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false
Test: ARM64 device boot test
Bug: 37707231
Change-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b
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| 9bd88b0933a372e6a7b64b850868e6a7998567e2 |
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22-Apr-2015 |
Serban Constantinescu <serban.constantinescu@linaro.org> |
ARM64: Move xSELF from x18 to x19.
This patch moves xSELF to callee saved x19 and removes support for
ETR (external thread register), previously used across native calls.
Change-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b
Signed-off-by: Serban Constantinescu <serban.constantinescu@linaro.org>
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| 37c92df53979f9f6ab83155ab9521d554d717161 |
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17-Oct-2014 |
Alexandre Rames <alexandre.rames@arm.com> |
Rename arm64 `Register` to `XRegister`.
This will avoid naming conflicts in the arm64 port of
the optimizing compiler.
Change-Id: Ie736ddd2ddbd2e299058256de28bad5d41c57d6f
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| a304f97c97d38af73afe6b49259ac4faf0902123 |
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17-Oct-2014 |
Alexandre Rames <alexandre.rames@arm.com> |
Rework arm64 register codes and fix Arm64ManagedRegister tests.
Change-Id: I81ce3bc8a212c9c35be3a41b182ada87b32391ec
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| 0db7ad3687e9639c45d598ce0f4ce2cbeedf8840 |
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03-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Rename registers in arm64."
This reverts commit 11daa0adbb30f341ccbdec64a2d43d8eeb111288.
Change-Id: I2ce0879dce8fbf5512649d0d9c3a2c189c23dd5f
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| 11daa0adbb30f341ccbdec64a2d43d8eeb111288 |
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01-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Rename registers in arm64.
Change-Id: I4c3ed96be2a7efaa674486515c84c689f382eceb
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| b551fdcda9eb128c80de37c4fb978968bec6d4b3 |
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25-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Clean up CalleeSaveMethod frame and the use of temp registers.
CalleeSaveMethod frame size changes :
SaveAll : 368 -> 176
RefOnly : 176 -> 96
RefsAndArgs : 304 -> 224
JNI register spill size changes :
160 -> 88
In the transition assembly, use registers following the rules:
1. x0-x7 as temp/argument registers.
2. IP0, IP1 as scratch registers.
3. After correct type of callee-save-frame has been setup, all registers
are scratch-able(probably except xSELF and xSUSPEND).
4. When restore callee-save-frame, IP0 and IP1 should be untouched.
5. From C to managed code, we assume all callee save register in AAPCS
will be restored by managed code except x19(SUSPEND).
In quick compiler:
1. Use IP0, IP1 as scratch register.
2. Use IP1 as hidden argument register(IP0 will be scratched by
trampoline.)
Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
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| 63206f3038d3d6e1cb24166726613808a4b0ad8c |
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07-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Fix the usage of Thread Register for arm64
This patch cleans-up the usage of x18 as TR for Arm64. As described in
the Arm64 Procedure Call Standard, the recommended usage for x18 is to
carry inter-procedural state (i.e. ART thread information).
However, since x18 is a temporary register there is no guarantee that on
calls to external functions x18 is preserved. Thus on JNI calls we need
to save and restore x18 before coming back to managed runtime. For the
JNI compiler trampoline we move x18 (temporary register - caller saved)
to x19 (ETR, callee saved) before calling into native code, and
restore it on the way back.
Change-Id: If24091018d640027a497517a9238bf4a80d013aa
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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| 75b9113b2b0a5807043af2a669a93d1579af8e2c |
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09-Apr-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Jni compiler fixes
This patch fixes some of the issues with the ARM64 assembler and JNI
compiler.
The JNI compiler is not enabled by default, yet. To enable, change
line 1884 in compiler/driver/compiler_driver.cc, removing kArm64 from
the GenericJNI list.
The compiler passes all tests in jni_compiler_test.
Also change the common_compiler_test instruction-set-features logic.
We allow tests when the build-time features are a subset of the
runtime features.
Dex2oat cross-compiling is now working. A 32b version of dex2oat should
be able to compile correctly.
Change-Id: I51d1c24f2c75d4397a11c54724a8b277ff3b3df8
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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| 15523731549152276f23dcf94d81b1a9ce9c5038 |
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02-Apr-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Fix Managed Register unit tests
Fixes the XZR change introduced by one of the previous patches. It
also adds extra testing for VIXL register integration.
Change-Id: I4935f06726e25829613ef7bb6ac052d82056812c
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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| b95a5345ae4217b70ca36f0cced92f68dda7caf5 |
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12-Mar-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
AArch64: Add arm64 runtime support.
Adds support for arm64 to ART. Assembler stubs are sufficient for
down calls into interpreter. JNI compiler and generics are not finished.
Basic Generic JNI functionality.
Change-Id: I4a07c79d1e037b9f5746673480e32cf456867b82
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| ed8dd492e43cbaaa435c4892447072c84dbaf2dc |
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11-Feb-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add ARM64 Assembler
This patch adds the ARM64 Assembler and ManagedRegister backend.
The implementation of the Arm64Assembler class is based on VIXL (a
programmatic A64 Assembler - see external/vixl ).
Change-Id: I842fd574637a953c19631eedf26f6c70d9ed7f9e
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
|