| b97fbe5a636745110529aced389b251d59ab2fd6 |
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16-Mar-2018 |
Aart Bik <ajcbik@google.com> |
Minor DCHECK bug fix.
Rationale:
Should use the utility to test for SIMD result,
Test: 623
Bug: b/80497244
(cherry picked from commit 5a0eb0cbeeabda48bfef05df9f59a6fd607e1a1e)
Change-Id: I2966efea643eb7292c59f4f3e9b8725f0792d689
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| ee74149e9209eabf5928bb0df9a7cf8e194f9677 |
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21-Dec-2017 |
Aart Bik <ajcbik@google.com> |
Force JIT on reduction with many variables.
Rationale:
This method exposed a few bugs with SIMDization, so it
is important we make sure this loops is vectorized under JIT.
Bug: 70559970
Test: 623
Change-Id: I1be82f934d9c929ce390c30e278cb86491b5564d
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| 2dd7b672ea0afd7ea4448b43d24829e9886de3af |
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07-Dec-2017 |
Aart Bik <ajcbik@google.com> |
Fixed spilling bug (visible on ARM64): missed SIMD type.
Test: test-art-host test-art-target
Change-Id: I6f321446f54943e02f250732ec9da729f633c3a9
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| 8c6c3575668831c752820ba4174b07ee407f7a4f |
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25-Oct-2017 |
Aart Bik <ajcbik@google.com> |
Make SIMD checker tests more robust.
Rationale:
With more and more peeling and cleanup loops coming up,
some of our checker tests were a bit fragile testing for
the first Phi occurrence. This CL fixes that. Also fixes
a few omissions found during the refactoring.
Test: test-art-host test-art-target
Change-Id: I9b27237cf048981ca2b5a18057e09211b7002486
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| df011c3bc3db8b327f2b2d93e108c3a53a9a4f34 |
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28-Sep-2017 |
Aart Bik <ajcbik@google.com> |
Generalized zero/sign-ext analysis. Generalized SAD.
Rationale:
The more, the better. Some of the analysis was
overly conservative (e.g. extension does not
need to happen from terminals only as long
as vectorized guarantees higher order bits
don't contribute). Also, added hidden-SUB for SAD.
Test: test-art-host test-art-target
Bug: 64091002
Change-Id: I66afd8fb4292ce5cf14f98f9c5ce2bf2b8c98488
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| 521b50f58f2af8b5a68f821a6c4eac7d86ec01f5 |
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09-Sep-2017 |
Aart Bik <ajcbik@google.com> |
No unrolling for large loop bodies.
Rationale:
should yield 1, not 0
Test: test-art-host test-art-target
Change-Id: I0ca68b2a5a4dba1c3e41248376002d9635716840
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| dcaf0e5da40dafc51c70d2ce4e23925d30b27374 |
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08-Sep-2017 |
Aart Bik <ajcbik@google.com> |
Bug fix on 32-bit vs 64-bit movd/movdq on x86_64.
Bug: 65478356
Test: test-art-host
Change-Id: I5335225ab8ca40e099c4a6b93cbf58783a6ddd0b
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| 7f56ff42ac663ccfa62034ed22297bd7d9bce2f6 |
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30-Aug-2017 |
Aart Bik <ajcbik@google.com> |
Refined range rule for ABS(x)
Rationale;
ABS(minint) = minint prevents assuming >=0 always.
With a fail-before(sig11)/pass-after regression test.
Test: 623
Change-Id: If5fb1580b207c7cdd964f7498849d1768bb1589d
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| 671e48a4895cc1a0b7a1458d608f8c4f9b5cf85c |
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09-Aug-2017 |
Aart Bik <ajcbik@google.com> |
Fix performance regression.
Rationale:
One "improvement" overlooked in the previous CL hoists
a try-test out of the optimization to make sure we don't
change HIR when not needed. However, the try-test may
affect the outcome of the test, so that was bad, bad!
Bug: 64091002
Test: test-art-host
Change-Id: Icf5f73e7cbeb209ee5fa5f6c1bef64fe127bb2fd
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| 21c7e6fbcabef2f22b467e1e89f4abe1aa43e459 |
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27-Jul-2017 |
Artem Serov <artem.serov@linaro.org> |
ART: Fix SimplifyInduction for an instruction with HEnvironment.
After an instruction is removed during RemoveFromCycle its
environment isn't properly cleaned: it still has input instructions
present and registered (those instructions still hold records for
that).
Test: test-art-target, test-art-host.
Change-Id: Iea315bdf735d75fe477f43671f05b40dfecc63a8
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| 8f7c41044bdb7a36913444a3437bf2b946f7efe9 |
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21-Jun-2017 |
Artem Serov <artem.serov@linaro.org> |
ARM: ART Vectorizer (64-bit vectors).
Basic vectorization support with 64-bit vector length on ARM 32-bit
platforms (128-bit vectors require massive changes in register
allocator).
Test: test-art-target, test-art-host
Change-Id: I1d740146c3f00170fc033ae5fd69d59321ddcbf4
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| 19680d3655433e98582983ed0a6d44d6b4822951 |
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11-May-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: ART Vectorizer
MIPS64 implementation which uses MSA extension. Also extended all
relevant checker tests to test MIPS64 implementation.
Test: booted MIPS64R6 in QEMU
Test: ./testrunner.py --target --optimizing -j1 in QEMU
Change-Id: I8b8a2f601076bca1925e21213db8ed1d41d79b52
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| 304c8a5dfe92d5677e9561270b19313d3e450c59 |
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23-May-2017 |
Aart Bik <ajcbik@google.com> |
Support for narrow operands in "dangerous" operations.
This is a revert^2 of commit 636e870d55c1739e2318c2180fac349683dbfa97.
Rationale:
Under strict conditions, even operations that are sensitive
to higher order bits can vectorize by inspecting the operands
carefully. This enables more vectorization, as demonstrated
by the removal of quite a few TODOs.
Test: test-art-target, test-art-host
Change-Id: Ic2684f771d2e36df10432286198533284acaf472
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| 9231690d586ecf45d5d9481bc5df5a5ad2628c89 |
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23-May-2017 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Support for narrow operands in "dangerous" operations."
Fails on armv8 / speed-profile
This reverts commit 636e870d55c1739e2318c2180fac349683dbfa97.
Change-Id: Ib2a09b3adeba994c6b095672a1e08b32d3871872
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| 636e870d55c1739e2318c2180fac349683dbfa97 |
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18-May-2017 |
Aart Bik <ajcbik@google.com> |
Support for narrow operands in "dangerous" operations.
Rationale:
Under strict conditions, even operations that are sensitive
to higher order bits can vectorize by inspecting the operands
carefully. This enables more vectorization, as demonstrated
by the removal of quite a few TODOs.
Test: test-art-target, test-art-host
Change-Id: I2b0fda6a182da9aed9ce1708a53eaf0b7e1c9146
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| 06886e53ad3218407db42cd14a43b8824fb61547 |
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03-May-2017 |
Aart Bik <ajcbik@google.com> |
Fixed bug due to not updating TC information
(with regression test)
Bug: 37768917
Test: test-art-target, test-art-host
(cherry picked from commit e22445fba0e5747ea787429ac64577a9a62aded3)
Change-Id: I505106ef7ab8eed1e37067b39d6ef657ee234292
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| e22445fba0e5747ea787429ac64577a9a62aded3 |
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03-May-2017 |
Aart Bik <ajcbik@google.com> |
Fixed bug due to not updating TC information
(with regression test)
Bug: 37768917
Test: test-art-target, test-art-host
Change-Id: Ia0cd4e0874941a047625448cbb95b7b4733d70d1
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| f50c2b9023e32cefb1f8e57c0751c394d251b61f |
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01-May-2017 |
Aart Bik <ajcbik@google.com> |
Allow same-length integral type mixing in SIMD.
Rationale:
Just like the incoming sequential code, the SIMD
code allows for some type matching, as long as
it is integral and same length.
Bug: 37764324
Test: test-art-target, test-art-host
Change-Id: Ide1c5403e0f3b8c5372e8ac6dd282d8211ca8f1b
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| d58bc3212a968fe5a2e1fba51df9a7efedcf1b60 |
|
01-May-2017 |
Aart Bik <ajcbik@google.com> |
Allow same-length integral type mixing in SIMD.
Rationale:
Just like the incoming sequential code, the SIMD
code allows for some type matching, as long as
it is integral and same length.
Bug: 37764324
Test: test-art-target, test-art-host
Change-Id: Ide1c5403e0f3b8c5372e8ac6dd282d8211ca8f1b
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| 472821b210a7fc7a4d2e3d45762c7b5b9628a35b |
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28-Apr-2017 |
Aart Bik <ajcbik@google.com> |
Enable string "array get" vectorization.
Rationale:
Like its scalar counterpart, the SIMD implementation of array get from
a string needs to deal with compressed and uncompressed cases.
Micro benchmarks shows 2x to 3x speedup for just copying data!
Test: test-art-target, test-art-host
Change-Id: I2fd714e50715b263123c215cd181f19194456d2b
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| d86c08555905dbc42233a506683e3995446fc113 |
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14-Apr-2017 |
Aart Bik <ajcbik@google.com> |
Fixed bug on pending environment use of termination condition.
With regression test.
Test: test-art-host
Bug: 37247891
Change-Id: I55b06939d465d3ddb736d1ba659b1df179a5c390
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| 3101e58114b21876f77940d716385c54f697761b |
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11-Apr-2017 |
Aart Bik <ajcbik@google.com> |
Fix bug in vectorization of charAt, with regression test
Rationale:
String array get instruction cannot be vectorized
in a straightforward way, since compression has
to be dealt with. So rejected for now.
Test: test-art-target, test-art-host
Bug: 37151445
Change-Id: I16112cb8b1be30babd8ec07af5976db0369f8c28
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| fa76296bc624bc2c879167c260ad6925238efb3d |
|
07-Apr-2017 |
Aart Bik <ajcbik@google.com> |
Fixed missing context while detecting unit strides.
With regression test (found by fuzz testing).
Bug: 37033123
Test: test-art-target
Change-Id: Id738b2a3a353985c3d0bf3beeb581a31f1fcbc3f
|
| 7adb688fe1213c6dcaf4d2adae3d8b7decf7c28a |
|
07-Mar-2017 |
Aart Bik <ajcbik@google.com> |
Improve isunit computation, some tests edits needed for SIMD.
Rationale:
Break-out CL of ART Vectorizer: number 4.
The purpose is making the original CL smaller
and easier to review.
Bug: 34083438
Test: test-art-host
Change-Id: I62a174944bbbe1e08f631f322c513eeaea14de26
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| b603a5cdff7c1fb300b83175bfb3cd990fdd6265 |
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07-Mar-2017 |
Aart Bik <ajcbik@google.com> |
Bug fix in overflow detection on pow. With regression test.
Rationale:
Missed potential overflow in base update.
Test: test-art-host
Bug: 35706963
Change-Id: I117d96c1fa95dde37f5676f9dc750f0a71becafa
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| d3ba626b424511b91db8e04660e3248cdd597100 |
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30-Jan-2017 |
Aart Bik <ajcbik@google.com> |
Fix bug in geometric last value (found with fuzz testing)
Rationale:
When power computation overflows, div should use 0 while mul should
use truncated version. Both cases were incorrectly using the latter.
Test: test-art-host
Bug: 34779592
Change-Id: I9eb8e1280c58b09d57886128f4df4541c143afaa
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| 74da5290dd5cc040bee5430796715bd9302036c2 |
|
20-Dec-2016 |
Aart Bik <ajcbik@google.com> |
Fix transfer over rejected induction.
Rationale:
With the more precise rejection of narrowing
linear induction, parent rules should be
prepared to reject failed transfers. Also
added a bit more comments to clarify rules.
With regression tests.
Bug: 33774618
Test: test-art-host
Change-Id: I4a206e51d4359ab383379914dd4697fc81903547
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| 807868eac75a39e79ee6309ed4cbe038407efa29 |
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04-Nov-2016 |
Aart Bik <ajcbik@google.com> |
Account for early exit loop.
Rationale:
last value computation is obviously only right if
the loop does not have early exits; only needed
if cycle leaks to outside loop in any way.
Bug:32633772
Test: 623-checker-loop-regressions
Change-Id: Id60beca4704491cff611ad12a24bfc63c09d32c3
|