9cb7fe4daf872fd0cb312489af263ebc622033a8 |
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30-Nov-2017 |
Aart Bik <ajcbik@google.com> |
Exploited CHECK-START-{x,y,z} syntax. Rationale: Previous CL introduced new check syntax to define multiple target architectures. This CL exploits the new feature. Bug: 62352954 Test: test-art-host test-art-target Change-Id: Ia2b9f210b0c1483e96e1df2d3d5e27f24420245d
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8c6c3575668831c752820ba4174b07ee407f7a4f |
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25-Oct-2017 |
Aart Bik <ajcbik@google.com> |
Make SIMD checker tests more robust. Rationale: With more and more peeling and cleanup loops coming up, some of our checker tests were a bit fragile testing for the first Phi occurrence. This CL fixes that. Also fixes a few omissions found during the refactoring. Test: test-art-host test-art-target Change-Id: I9b27237cf048981ca2b5a18057e09211b7002486
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61b922847403ac0e74b6477114c81a28ac2e01a0 |
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11-Oct-2017 |
Vladimir Marko <vmarko@google.com> |
ART: Introduce Uint8 loads in compiled code. Some vectorization patterns are not recognized anymore. This shall be fixed later. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: testrunner.py --target --optimizing on Nexus 5X Test: Nexus 5X boots. Bug: 23964345 Bug: 67935418 Change-Id: I587a328d4799529949c86fa8045c6df21e3a8617
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d5d2f2ce627aa0f6920d7ae05197abd1a396e035 |
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26-Sep-2017 |
Vladimir Marko <vmarko@google.com> |
ART: Introduce Uint8 compiler data type. This CL adds all the necessary codegen for the Uint8 type but does not add code transformations that use that code. Vectorization codegens are modified to use Uint8 as the packed type when appropriate. The side effects are now disconnected from the instruction's type after the graph has been built to allow changing HArrayGet/H*FieldGet/HVecLoad to use a type different from the underlying field or array. Note: HArrayGet for String.charAt() is modified to have no side effects whatsoever; Strings are immutable. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing --jit Test: testrunner.py --target --optimizing on Nexus 6P Test: Nexus 6P boots. Bug: 23964345 Change-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0
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8f7c41044bdb7a36913444a3437bf2b946f7efe9 |
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21-Jun-2017 |
Artem Serov <artem.serov@linaro.org> |
ARM: ART Vectorizer (64-bit vectors). Basic vectorization support with 64-bit vector length on ARM 32-bit platforms (128-bit vectors require massive changes in register allocator). Test: test-art-target, test-art-host Change-Id: I1d740146c3f00170fc033ae5fd69d59321ddcbf4
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19680d3655433e98582983ed0a6d44d6b4822951 |
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11-May-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: ART Vectorizer MIPS64 implementation which uses MSA extension. Also extended all relevant checker tests to test MIPS64 implementation. Test: booted MIPS64R6 in QEMU Test: ./testrunner.py --target --optimizing -j1 in QEMU Change-Id: I8b8a2f601076bca1925e21213db8ed1d41d79b52
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f3e61ee363fe7f82ef56704f06d753e2034a67dd |
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13-Apr-2017 |
Aart Bik <ajcbik@google.com> |
Implement halving add idiom (with checker tests). Rationale: First of several idioms that map to very efficient SIMD instructions. Note that the is-zero-ext and is-sign-ext are general-purpose utilities that will be widely used in the vectorizer to detect low precision idioms, so expect that code to be shared with many CLs to come. Test: test-art-host, test-art-target Change-Id: If7dc2926c72a2e4b5cea15c44ef68cf5503e9be9
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