e47ac1fd634a3934d7d3ac446190b2f4bd8a640f |
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14-Sep-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Fix type of `unsigned long` constants The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in AArch64. This is inconsistent and that's why we avoid using it as per the Coding Guidelines. This patch changes all `UL` occurrences to `U` or `ULL` depending on the context so that the size of the constant is clear. This problem affected the macro `BIT(nr)`. As long as this macro is used to fill fields of registers, that's not a problem, since all registers are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the macro is used to fill the fields of a 64-bit integer, it won't be able to set the upper 32 bits in AArch32. By changing the type of this macro to `unsigned long long` the behaviour is always the same regardless of the architecture, as this type is 64-bit wide in both cases. Some Tegra platform files have been modified by this patch. Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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ee1ebbd18e2a1e3b8a5b9ac9fba155177e2af4a1 |
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14-Jul-2017 |
Isla Mitchell <isla.mitchell@arm.com> |
Fix order of remaining platform #includes This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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9a8f05e47d00efa2f1eac07fe4373de464b5b11c |
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26-May-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: gic: fix MISRA defects Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Fixed assert/if statements conditions to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Convert macros form headers to unsigned ints Change-Id: I8051cc16499cece2039c9751bd347645f40f0901 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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82cb2c1ad9897473743f08437d0a3995bed561b9 |
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03-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Use SPDX license identifiers To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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45eab456e6da0e79c51ffced6c3a46053a1adc70 |
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21-May-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1 This patch modifies the secure IRQ registration process to allow platforms to specify the target CPUs as well as the owner of the IRQ. IRQs "owned" by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted OS would return INTR_TYPE_S_EL1 as a result. Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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d33603016971adbe2aba04f96c2a45b56d33f99a |
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28-Dec-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: GIC: enable FIQ interrupt handling Tegra chips support multiple FIQ interrupt sources. These interrupts are enabled in the GICD/GICC interfaces by the tegra_gic driver. A new FIQ handler would be added in a subsequent change which can be registered by the platform code. This patch adds the GIC programming as part of the tegra_gic_setup() which now takes an array of all the FIQ interrupts to be enabled for the platform. The Tegra132 and Tegra210 platforms right now do not register for any FIQ interrupts themselves, but will definitely use this support in the future. Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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e1e094c799e0bebcf4020d8f70a041ae30eddbc9 |
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16-Jun-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Add missing features to the Tegra GIC driver In order to handle secure/non-secure interrupts, overload the plat_ic_* functions and copy GIC helper functions from arm_gic.c. Use arm_gic.c as the reference to add Tegra's GIC helper functions. Now that Tegra has its own GIC implementation, we have no use for plat_gic.c and arm_gic.c files. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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08438e24e10504642634da9ee3dde794ac6fa8f0 |
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19-May-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Support for NVIDIA's Tegra T210 SoCs T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c
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