| f4ffe2786bd5f0f5b894e4772a64ba78276ea2d2 |
|
09-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/a3xx: make _emit_const() static
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| e6bfe1c7734cfbf41a763797527db6cb49fa1566 |
|
19-Jul-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno: move needs_wfi into batch
This is also used in gmem code, which executes from the "bottom half"
(ie. from the flush_queue worker thread), so it cannot be in fd_context.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 7f8fd02dc7cad1ddcfb610db10ffbb41e3e34e7d |
|
11-Jul-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno: re-order support for hw queries
Push query state down to batch, and use the resource tracking to figure
out which batch(es) need to be flushed to get the query result.
This means we actually need to allocate the prsc up front, before we
know the size. So we have to add a special way to allocate an un-
backed resource, and then later allocate the backing storage.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 9bbd239a4039522d7c1023ecb21764679447bb2d |
|
20-May-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno: introduce fd_batch
Introduce the batch object, to track a batch/submit's worth of
ringbuffers and other bookkeeping. In this first step, just move
the ringbuffers into batch, since that is mostly uninteresting
churn.
For now there is just a single batch at a time. Note that one
outcome of this change is that rb's are allocated/freed on each
use. But the expectation is that the bo pool in libdrm_freedreno
will save us the GEM bo alloc/free which was the initial reason
to implement a rb pool in gallium.
The purpose of the batch is to eventually facilitate out-of-order
rendering, with batches associated to framebuffer state, and
tracking the dependencies on other batches.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 663c0e5155e9916b10163c102f0ece4eda5c3154 |
|
24-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use pipe_debug_callback for shader-db traces
For multi-threaded shader-db support.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 51f20dd279f420492779e4256b111d65f6fc0917 |
|
24-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: add debug callback to emit
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 476551a21fbb255a3effa7aa46801764a38ef213 |
|
13-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: move where we deal w/ binning FS
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 09b34473446163eb737c2b183095c0342eab7eea |
|
13-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: constify the shader variants
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 6206da736c84c4f7316ab586c886b4865fda8805 |
|
15-Oct-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: cache-flush is needed after MEM_WRITE
Otherwise the mem2gmem blit would see potentially bogus texture
coordinates. Fixes an issue that shows up with glamor.
CC: "11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 56462a30080c1f25a81ae566d59a25d2ad6bb809 |
|
24-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: move emit_const to ir3
Details of the cmdstream packets are different between a3xx and a4xx,
but the logic about the layout of const registers is the same, as that
is dictated by the ir3 shader compiler. So rather than duplicating
logic that is tightly coupled to ir3 between a3xx and a4xx, move this
into ir3 and use per-generation callbacks for to build the cmdstream
packets.
This should make it easier to pass additional const regs (such as for
transform feedback). And it also keeps the layout internal to ir3 in
case we want to make the layout more dynamic some day.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| b060b56772cdb349478757382de036a20a2402ba |
|
04-Apr-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a3xx: pass sprite coord mode through to program emit
Use the correct sprite replacement depending on the flip of the coord
mode, using either T or 1-T depending on whether we have an upper-left or
lower-left coordinate origin. This fixes all the point sprite piglits.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 4a3c0e995063320693782b934962969e11dab29d |
|
15-Feb-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a3xx: add MRT support
The hardware only supports 4 MRTs. It should be possible to emulate
support for 8, but doesn't seem worth the trouble.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| ee670c9efa471aa78563b14f47bcd89220b608dc |
|
17-Mar-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a3xx: add support for point sprite coordinate replacement
This does not (yet) support different coordinate origins, so the tests
still fail due to fbo flipping.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| d63afe3b588096ca6b91db8d1d8807968b63b390 |
|
28-Nov-2014 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a3xx: add format to emit info, use to set sint/uint flags
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 3338bfcf498aa93a256aaadaee25951d4864f78f |
|
28-Nov-2014 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a3xx: fd3_util -> fd3_format
All the "util" helpers are actually format-related
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| d595987ea3d1706fecb9f6416031ec8b27c95a9e |
|
14-Oct-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: refactor/optimize emit
Because we reuse various bits of emit code (for state/vertex/prog/etc)
for both regular draws and internal draws (gmem<->mem, clear, etc), the
number of parameters getting passed around has been growing. Refactor
to group these into fd3_emit. This simplifies fxn signatures, avoids
passing around shader key on the stack, etc. It also gives us a nice
place to cache shader-variant lookup to avoid looking up shader variants
multiple times per draw (without having to *also* pass them around as
fxn args everywhere).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| d5d80b37392c7f15c4fb39b6b1826230239930fd |
|
14-Oct-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: refactor vertex state emit
Get rid of fd3_vertex_buf and use fd_vertex_state directly for all
draws. Removes a tiny bit of CPU overhead for munging around the vertex
state every time it is emitted, but more importantly it cleans things up
for later optimizations, so the emit paths don't have to special case
internal draws (gmem<->mem, clears, etc) with regular draws.
Instead of constructing fd3_vertex_buf array each time for internal
draws, and context init time pre-create solid_vbuf_state and
blit_vbuf_state.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 720cfb6fe9a3dafadf3bc034008f7c5c15973866 |
|
09-Sep-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: enable hw primitive-restart
Since software primitive-restart emulation is going to be removed (and
anyways, mostly seemed to be crash prone in combination with
u_primconvert and oddball scenarios (like PIPE_PRIM_POLYGON with only a
single vertex), might as well do it in hardware (which fortunately
didn't turn out to be too hard to figure out).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| db193e5ad06e7a2fbcffb3bb5df85d212eb12291 |
|
25-Jul-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: split out shader compiler from a3xx
Move the bits we want to share between generations from fd3_program to
ir3_shader. So overall structure is:
fdN_shader_stateobj -> ir3_shader -> ir3_shader_variant -> ir3
|- ...
\- ir3_shader_variant -> ir3
So the ir3_shader becomes the topmost generation neutral object, which
manages the set of variants each of which generates, compiles, and
assembles it's own ir.
There is a bit of additional renaming to s/fd3_compiler/ir3_compiler/,
etc.
Keep the split between the gallium level stateobj and the shader helper
object because it might be a good idea to pre-compute some generation
specific register values (ie. anything that is independent of linking).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 141ae716719a9160365ecaf5fd7354b83b063b30 |
|
22-Feb-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: add shader variants
Start putting in place infrastructure to deal with multiple shader
variants. Initially we'll use this for two sided color (frag) and
binning pass (vert) shaders. Possibly need for others later (such
as YUV vs RGB eglImage?).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 8d27be2633f2fc543a6d00d66dcb033798d44749 |
|
14-Jan-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: handle frag z write
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 725d736f6a6a14d10223888d585ddab80ee803f0 |
|
08-Jan-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: use cs patch instead of RFI+RMW
Since we now have the cmdstream patch mechanism needed for hw binning,
might as well also use it for RB_RENDER_CONTROL updates. This avoids
the need to use RMW (and associated WFI) to update RB_RENDER_CONTROL.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| c0766528baaef48902c87bbdaa4f5926c472269b |
|
07-Jan-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: support for hw binning pass
The binning pass sorts vertices into which bins/tiles they apply to.
The visibility information generated during the binning pass can be
used to speed up the rendering pass by filtering out vertices which
do not apply to the current tile. See:
https://github.com/freedreno/freedreno/wiki/Adreno-tiling#optimized-approach
This brings a significant fps boost. A rough assortment of tests
(supertuxkart, etracer, tremulous, glmark2 'build' test, etc) seems
to yield a ~35-45% fps improvement.
For now, to be conservative, the binning pass is not enabled yet by
default. To enable it use:
FD_MESA_DEBUG=binning
So far I haven't found anything that breaks with binning enabled,
but I'd like a bit more testing before I enable it as default.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 8ab47b435319c05521bdfced6da6ce72850a2dd7 |
|
23-Dec-2013 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: fix blend state corruption issue
Using RMW on banked context registers is not safe. The value read
could be the wrong one. So if there has been a DRAW_IDX launched,
the RMW must be preceded by a WAIT_FOR_IDLE to ensure the read part
of RMW sees the correct value.
To avoid unnecessary WFI's, keep track if there is a need for WFI,
and only emit one if needed. Furthermore, keep track if we even
need to update the register in the first place.
And to cut down on the amount of RMW to avoid excessive WFI's, at the
tiling/GMEM level we can always overwrite RB_RENDER_CONTROL, as the
state at beginning of draw/clear cmds (which we IB to) is always
undefined. In the draw/clear commands, we always still use RMW (with
WFI if needed), but only if the register value actually changes. (At
points where the current value cannot be known, the saved value is
reset to ~0, which includes bits outside of RBRC_DRAW_STATE, so there
never is chance for confusion.)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|
| 2855f3f7bcd9b36a275e942c9c7d0eb8e485c16f |
|
26-May-2013 |
Rob Clark <robclark@freedesktop.org> |
freedreno: add a3xx support
The adreno a3xx GPU is found in newer snapdragon devices, such as the
nexus4. The a3xx is GLESv3 and OpenCL capable, although that is not
enabled yet in gallium.
Compared to a2xx, it introduces an entirely new unified shader ISA, and
re-shuffles all or nearly all of the registers. The good news is that
(for the most part) the registers are more orthogonal, not combining
unrelated state in a single register. And that there is a lot more
flexibility, so we don't need to patch and re-emit the shader like we
did on a2xx.
The shader compiler is currently quite dumb, there would be a lot of
room for improvement with an optimizing pass. Despite that, with the
a320 in my nexus4 it seems to be ~2-3x faster compared to the a220 in my
HP touchpad.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
|