| 45eef9af03639a409ef54b136bb4902b9825864b |
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30-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/a5xx: fix negative branches
Looks like immed branch offset size increased again.. making what we
think is a small negative number look to hw like a huge positive number.
And things go badly when shader tries to jump to hyperspace.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| 70735643f4cf660dc3022f40f853a138aea738c2 |
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27-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: encode instruction category in opc_t
Been on my TODO list for a while. If nothing else this will make gdb
properly grok the opc_t enum.
This first step preserves ir3_instruction::category (with an added
assert that category matches what is encoded in opc_t). Next step is
to drop the category field (and arg to ir3_instr_create()), but that
is split into next commit for bisectability and so that we can run
piglit in the intermediate state to flush out any problems.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| 6a33c5c0dffce136bdc95daa2db2d3e9d3c1741f |
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16-Jan-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: array offset can be negative
It at least happens with some piglit tests, like
$piglit/bin/vp-address-01
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..7]
DCL ADDR[0]
0: ARL ADDR[0].x, IN[1].xxxx
1: MOV_SAT OUT[1], CONST[ADDR[0].x-1]
2: DP4 OUT[0].x, CONST[4], IN[0]
3: DP4 OUT[0].y, CONST[5], IN[0]
4: DP4 OUT[0].z, CONST[6], IN[0]
5: DP4 OUT[0].w, CONST[7], IN[0]
6: END
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| bc5e2bec303acd7fd962996bf369be5ce0e15cd2 |
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23-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: updated cat6 encoding
Sync updated cat6 encoding from freedreno.git, needed to properly encode
store instructions.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| 660d5c1646f5d63f9626b24beabc9cfc318849d4 |
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01-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: a4xx encodes larger immed offset
Without this, negative branch/jump offsets look like very large positive
offsets.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| 0f6faa8ff317634ffb75e6040f2de2019dd80d13 |
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25-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: remove tgsi f/e
Also remove ir3_flatten which was only used by tgsi f/e.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| cb24d3b7ad2f6c03edd86d827db2b308670ae8a7 |
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22-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno: misc minor cleanups
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| f0e9a632a12798bd727799e396cde665bd960665 |
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06-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/cp: support to swap mad src's
For a normal MAD (ie. not MADSH), if first source is gpr and second
source is const, we can swap the first two sources to avoid needing a
mov instruction.
This gives back the biggest advantage TGSI f/e had over NIR f/e for
common shaders, since TGSI f/e had this logic in the f/e. Note that
doing this in copy-prop step has the advantage that it will also work
for cases like:
MOV TEMP[b], CONST[x]
MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c]
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| 203f37540a698a812f0a66e2f3f1fff954af22ab |
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19-Mar-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add ir3 builder helpers
Add helpers for constructing SSA forms of instructions.
Only partial cat5/cat6 coverage.. but we can add stuff as needed.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| 17754b70d78649f29e25dfe938de91d64dbf5ebf |
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04-Feb-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: drop deref nodes
The meta-deref instruction doesn't really do what we need for relative
destination. Instead, since each instruction can reference at most a
single address value, track the dependency on the address register via
instr->address. This lets us express the dependency regardless of
whether it is used for dst and/or src.
The foreach_ssa_src{_n} iterator macros now also iterates the address
register so, at least in SSA form, the address register behaves as an
additional virtual src to the instruction. Which is pretty much what
we want, as far as scheduling/etc.
TODO:
For now, the foreach_src{_n} iterators are unchanged. We could wrap
the address in an ir3_register and make the foreach_src_{_n} iterators
behave the same way. But that seems unnecessary at this point, since
we mainly care about the address dependency when in SSA form.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| 20b50a071271e2caf8a4c3d4fd72f877af8a18d9 |
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26-Feb-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix up cat6 instruction encodings
I think there is at least one more sub-encoding, but these two should be
enough to cover the common load/store instructions.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
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| db193e5ad06e7a2fbcffb3bb5df85d212eb12291 |
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25-Jul-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: split out shader compiler from a3xx
Move the bits we want to share between generations from fd3_program to
ir3_shader. So overall structure is:
fdN_shader_stateobj -> ir3_shader -> ir3_shader_variant -> ir3
|- ...
\- ir3_shader_variant -> ir3
So the ir3_shader becomes the topmost generation neutral object, which
manages the set of variants each of which generates, compiles, and
assembles it's own ir.
There is a bit of additional renaming to s/fd3_compiler/ir3_compiler/,
etc.
Keep the split between the gallium level stateobj and the shader helper
object because it might be a good idea to pre-compute some generation
specific register values (ie. anything that is independent of linking).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/instr-a3xx.h
|