Cross Reference: /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3

History log of /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
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5fd152bae8a765024231a7390ae48752b579a5a9	01-Mar-2016	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: add dev ptr to ir3_compiler And use this for allocating bo's to hold the shader binary, rather than accessing the dev via ctx ptr. One step towards making shaders sharable across contexts. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
d52fb2f5ad828f879286b9068023b82b9897bc17	01-May-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3/ra: use register_allocate Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
694beb8b830c993e9bfb744655be3dbd558ab3a8	23-May-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: introduce ir3_compiler object Right now, just provides a cleaner way to get at the gpu-id, given the separation between compiler and context. But we will need this also to hold the reg-set for new register allocation. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
0f6faa8ff317634ffb75e6040f2de2019dd80d13	25-Apr-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: remove tgsi f/e Also remove ir3_flatten which was only used by tgsi f/e. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
67d994c6761e09205dbc9a0515c510fc9dde02c7	30-Apr-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: drop dot graph dumping At least for now.. right now the instruction and instruction list printing should suffice, and the re-working of ir3_block would require a lot of changes in that code. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
3e7bc6728520b469ed53a2588ead28287f8b88f0	28-Apr-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/ir3: fix immediate usage in tgsi tex fe get_immediate will return a const reference, the requested immediate isn't necessarily in the x slot. Make sure to use the swizzle. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
e1c4e8aaaafddd0e04cf2a16e28ef8f1e09d8b44	17-May-2015	Marek Olšák <marek.olsak@amd.com>	gallium: remove TGSI_SAT_MINUS_PLUS_ONE It's a remnant of some old NV extension. Unused. I also have a patch that removes predicates if anyone is interested. Reviewed-by: Roland Scheidegger <sroland@vmware.com> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
1de72dfc8a2014069edd1b3d3d46dad478d0680a	31-Mar-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a3xx: add UBO support Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
6cd9c94ce49a2c1a8826c1b1bf2fb73dc595131d	01-Apr-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: handle FRAG IN's without interpolation specified Fallback to picking based on semantic name. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
104713d9f2dced94a427004a25c54b2c7feee166	29-Mar-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: split float/int abs/neg Even though in the end, they map to the same bits, the backend will need to be able to differentiate float abs/neg vs integer abs/neg. Rather than making the backend figure it out based on instruction opcode (which when combined with mov/absneg instructions, can be awkward), just split out different flags for each so the frontend can signal it's intentions more clearly. Also, since (neg) for bitwise op's is actually a bitwise- not, split it out into bnot flag. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
b1c9fb9fcaf34923f69d671fdba0a35ea581b3a0	30-Mar-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: fix sam argument order comment Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
d13803c76fd7429df64c1aa3631dcc451e7f1a29	30-Mar-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/ir3: add support for FS_COLOR0_WRITES_ALL_CBUFS property This will enable the driver to tell which regids to link up to which MRT outputs. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
8efa3e340d13a9f373e7b2834f12d9fae43e6867	30-Mar-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno: remove alpha key from ir3_shader This complication is unnecessary and makes MRTs more complicated and likely to generate tons of variants. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
feb858b788cf27b31d12ad8a00805f015d4063cc	11-Mar-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: avoid scheduler deadlock Deadlock can occur if we schedule an address register write, yet some instructions which depend on that address register value also depend on other unscheduled instructions that depend on a different address register value. To solve this, before scheduling an address register write, ensure that all the other dependencies of the instructions which consume this address register are already scheduled. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
cb3eb43ad690a7355429ba8dcd40120646c55b9c	08-Mar-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/ir3: get the # of miplevels from getinfo This fixes ARB_texture_query_levels to actually return the desired value. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Rob Clark <robclark@freedesktop.org> Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
8ac957a51c67fc095db9539df6482b9533b1d05c	07-Mar-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/ir3: fix array count returned by TXQ Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Rob Clark <robclark@freedesktop.org> Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
060d3499202c339a27fbc366335f2122ed4ff7bc	23-Jan-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: relative dst To simplify RA, assign arrays that are written to first. Since enough dependency information is in the graph to preserve order of reads and writes of array, so all SSA names for the array collapse into one, just assign the entire thing by array-id. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
b7703212d8dc2b38407565768ac45d1a307cd810	04-Feb-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: split out array_fanin() helper We'll need this too for relative dst.. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
17754b70d78649f29e25dfe938de91d64dbf5ebf	04-Feb-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: drop deref nodes The meta-deref instruction doesn't really do what we need for relative destination. Instead, since each instruction can reference at most a single address value, track the dependency on the address register via instr->address. This lets us express the dependency regardless of whether it is used for dst and/or src. The foreach_ssa_src{_n} iterator macros now also iterates the address register so, at least in SSA form, the address register behaves as an additional virtual src to the instruction. Which is pretty much what we want, as far as scheduling/etc. TODO: For now, the foreach_src{_n} iterators are unchanged. We could wrap the address in an ir3_register and make the foreach_src_{_n} iterators behave the same way. But that seems unnecessary at this point, since we mainly care about the address dependency when in SSA form. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
0f797f7b7dd84f0bbb6efc68f230ce99eea00488	23-Jan-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: split up ssa_dst And a couple other trivial renames, to prepare for relative dst. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
60096ed906e5ebfdce41024c7af69f03b96dbe82	05-Mar-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: fix silly typo for binning pass shaders Was resulting in gl_PointSize write being optimized out, causing particle system type shaders to hang if hw binning enabled. Fixes neverball, OGLES2ParticleSystem, etc. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
e9f2abe349886ae5423c7c31d201e7d587a3695a	25-Feb-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: handle flat bypass for a4xx We may not need this for later a4xx patchlevels, but we do at least need this for patchlevel 0. Bypass bary.f for fetching varyings when flat shading is needed (rather than configure via cmdstream). This requires a special dummy bary.f w/ (ei) flag to signal to scheduler when all varyings are consumed. And requires shader variants based on rasterizer flatshade state to handle TGSI_INTERPOLATE_COLOR. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
f6b2e8af7425c67f8def9dfba92f6f0ad9585b40	02-Oct-2014	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a3xx: add support for vertexid and instanceid sysvals Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
1e5c207dba4dbd07919bff2efe57ad361a44ac84	31-Dec-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: start on indirect gpr reads Handle TEMP[ADDR[]] src registers by generating a fanin to group array elements, similarly to how texture fetch instructions work. NOTE: For all the scalar instructions generated for a single tgsi vector operation which uses an array src (or possibly even uses the same array as multiple srcs), re-use the same fanin node. Since a vector operation operates on all components at the same time, it should never see more than one version of the same array. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
63e5b72da8b1df4bbb0fcf46524d106f51264605	07-Jan-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: make reg array dynamic To use fanin's to group registers in an array, we can potentially have a much larger array of registers. Rather than continuing to bump up the array size, just make it dynamically allocated when the instruction is created. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
9a9f2a893b5e29a77d66671191653f0b4261f546	25-Oct-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: simplify RA Group inputs/outputs, in addition to fanin/fanout, as they must also exist in sequential scalar registers. This lets us simplify RA by working in terms of neighbor groups. NOTE: has the slight problem that it can't optimize out mov's for things like: MOV OUT[n], IN[m] To avoid this, instead of trying to figure out what mov's we can eliminate, we first remove all mov's prior to grouping, and then re-insert mov's as needed while grouping inputs/outputs/fanins. Eventually we'd prefer the frontend to not insert extra mov's in the first place (so we don't have to bother removing them). This is the plan for an eventual NIR based frontend, so separate out the instr grouping (which will still be needed for NIR frontend) from the mov elimination (which won't). Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
9bb865b3cf5b283a877ef937919e62e7e71ad588	31-Dec-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: split up ssa_src Slight bit of refactoring that will be needed for indirect gpr addressing (TEMP[ADDR[]]). Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
d15db9e7c05fde924c3dbced83c0af9c97c3973b	01-Jan-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: drop instr_clone() stuff Unnecessary and overly complicated. And gets in the way for temp arrays (TEMP[ADDR[]]). Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
56370b9feb269f185858422ee8fdf74a3dc99a33	06-Jan-2015	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: legalize vs unused sam dst components We probably could be more clever elsewhere and mask out components that are not used. But either way, legalize should realize that there is also a write-after-write hazard with texture sample instructions. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
f332cf92b69e52de3cb7c3088ad1efd2e291bb88	25-Oct-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: split out legalize pass Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
f20a0acd433acc6fe747bd6bf0179e0fd9e8e157	20-Dec-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: trans_kill cleanup trans_kill() only handles the single opcode. Drop the remnant of a time when both KILL and KILL_IF were handled by the same fxn. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
4ee545646d58cda4429f3dcfa4505471e424a4f2	20-Dec-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: hack for standalone compiler Standalone compiler doesn't have screen or context. We need to come up with a better way to control the target arch (ie. something that we can control from cmdline w/ standalone compiler) but for now this hack keeps it from segfault'ing. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
eb6fd3b8eb9c19bb501a091d1696e5db1ac4c690	06-Dec-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: lower TXP as needed On a3xx, lower TXP for 3D textures, on a4xx lower all TXP. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
82104c19f304a0e953172ad61d149640f0512fa0	30-Nov-2014	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a3xx: enable sampling from integer textures We need to produce a u32 destination type on integer sampling instructions, so keep that in a shader key set based on the currently-bound textures. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
547182977f5d893334cb630b974136c05a9461ab	29-Nov-2014	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/ir3: remove unused arg parameter Leaving it around in the struct in case we want to use it later. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
de83ef677f6d845e63f9e5e790d3078372f752df	03-Oct-2014	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/ir3: fix UMAD Looks like none of the mad variants do u16 * u16 + u32, so just add in the extra value "by hand". Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
37fe347542aad40aac5be9066c21f65f55d0f48c	26-Nov-2014	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/ir3: don't pass consts to madsh.m16 in MOD logic madsh.m16 can't handle a const in src1, make sure to unconst it Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Rob Clark <robdclark@gmail.com> Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
4dff2a642913cb9b72eccc3c290b1e5a71560156	24-Oct-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: always mov tex coords Always insert extra mov's for the tex coord into the fanin. This simplifies things a bit, and avoids a scenario where multiple sam instructions can have mutually exclusive input's to it's fanin, for example: 1: TEX OUT[0].xy, IN[0].xyxx, SAMP[0], 2D 2: TEX OUT[0].zw, IN[0].yxxx, SAMP[0], 2D The CP pass can always remove the mov's that are not actually needed, so better to start out with too many mov's in the front end, than not enough. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
d6252d0f633292b01c3964d0e3da12f759bec9c5	24-Oct-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: standalone compiler updates for ir3test In order to test compiler changes more easily, spit out the assembled shader with some header information so that we can know about inputs/outputs more easily. See: git://people.freedesktop.org/~robclark/ir3test In ir3test we have a big collection of tgsi shaders and reference ir3_compiler outputs. When making compiler changes, regenerate the compiler outputs and feed to ir3test to compare the new vs reference shader. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
4f17e026bb99c173444ff5ca7d0b782ed89ee604	19-Oct-2014	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: add debug flag to disable cp FD_MESA_DEBUG=nocp will disable copy propagation pass. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler.c