| b48fde15767284814b3df6e9d7946ca7f5eccbfb |
|
09-Jan-2017 |
Rob Clark <robdclark@gmail.com> |
freedreno/a5xx: use the non-_ZERO_BASE for vertexid
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 832dddcf91f168ab057cb5c7f6914b24ae6b864c |
|
28-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: rework varying slots (maybe??)
See:
dEQP-GLES2.functional.shaders.swizzles.vector_swizzles.mediump_vec2_yyyy_fragment
if we only access (in FS) varying.y then it ends up in slot zero.. I'm
not sure the hw likes that..
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| c416ea31cfe50e3d8ac3e433f9e4490a850b8e56 |
|
25-Dec-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: treat clipvertex like a normal varying
We need this in case it is streamed out. Not sure why we were treating
it specially before. Having it as a VS out is harmless if FS doesn't
have a matching input.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| d10c5a24818b39585acfa60ceb6dbbae22b5be09 |
|
24-Dec-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/a5xx: transform-feedback support
We'll need to revisit when adding hw binning pass support, whether we
can still do this in main draw step, as we do w/ a3xx/a4xx, or if we
needed to move it to the binning stage.
Still some failing piglits but most tests pass and the common cases seem
to work.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 6d77ceb701b889e76c93092b845986fc53e89257 |
|
24-Dec-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: UBO support for 64b GPUs (a5xx)
Update address calculation to support 64b addresses.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| fc10dc9fdea6ad7d04dfcdb8fd2e2d59ea67f68b |
|
22-Dec-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: rework location of driver constants
Rework how we lay out driver constants (driver-params, UBO/TFBO buffer
addresses, immediates) for more flexibility. For a5xx+ we need to deal
with the fact that gpu ptrs are 64b instead of 32b, which makes the
fixed offset scheme not work so well. While we are dealing with that
we might also make the layout more dynamic to account for varying # of
UBOs, etc.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| fd249c803e3ae2acb83f5e3b7152728e73228b7b |
|
12-Dec-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
treewide: s/comparitor/comparator/
git grep -l comparitor | xargs sed -i 's/comparitor/comparator/g'
Just happened to notice this in a patch that was sent and included one
of the tokens in question.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 728e2c4d38b2c03ad1fdc997bef70e646ada9fe4 |
|
23-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: don't offset inloc by 8
On a3xx/a4xx, the SP_VS_VPC_DST_REG.OUTLOCn is offset by 8, so we used
to add this offset into fs->inputs[n].inloc. But a5xx drops this extra
offset-by-8. So instead make inloc zero based and add the offset when
we emit OUTLOCn values (for the gen's that need the offset).
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| dfc001dccc7a29b1acf8d1ecf8072223aa98bc1b |
|
10-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: fixup ralloc fallout
Fixes fallout from acc23b04 ("ralloc: remove memset from ralloc_size").
We were still depending on zero'd allocations in a couple of places.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 93bfa1d7a2e70a72a01c48a04c208845c22f9376 |
|
25-Aug-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
nir: Change nir_shader_get_entrypoint to return an impl.
Jason suggested adding an assert(function->impl) here. All callers
of this function actually want ->impl, so I decided just to change
the API.
We also change the nir_lower_io_to_temporaries API here. All but one
caller passed nir_shader_get_entrypoint(), and with the previous commit,
it now uses a nir_function_impl internally. Folding this change in
avoids the need to change it and change it back.
v2: Fix one call I missed in ir3_compiler (caught by Eric).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| c078c41520214baf469dd4413f868e42c2959c5e |
|
04-Aug-2016 |
Eric Anholt <eric@anholt.net> |
ttn: Use nir_load_front_face instead of the TGSI-style input.
This reduces the diff between GLSL-to-NIR and TGSI-to-NIR, and gives NIR
more optimization to work on.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| ed92241d7848a5f08360240795869d72b68054a3 |
|
27-Jul-2016 |
Eric Anholt <eric@anholt.net> |
ttn: Make FRAG_RESULT_DEPTH be a float variable to match gtn and ptn.
This lets TTN-using drivers handle FRAG_RESULT_DEPTH the same between all
their source paths.
Reviewed-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 78ba262d004989c43b0a9e76c84b71bb16d4b333 |
|
11-Aug-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: fix issue with emit_tex()
For various tex fetch instructions, coord's get fixed up in different
ways. But modifying the array returned from get_src() has side-effects
if the same SSA src is used again.. the later instruction will see the
previous fixups.
Fix this, and const'ify things to prevent this sort of mistake in the
future.
Noticed by Varad when adding support for txf_ms.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| ac1181ffbef5250cb3b651e047cce5116727c34c |
|
07-Jul-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
compiler: Rename INTERP_QUALIFIER_* to INTERP_MODE_*.
Likewise, rename the enum type to glsl_interp_mode.
Beyond the GLSL front-end, talking about "interpolation modes" seems
more natural than "interpolation qualifiers" - in the IR, we're removed
from how exactly the source language specifies how to interpolate an
input. Also, SPIR-V calls these "decorations" rather than "qualifiers".
Generated by:
$ find . -regextype egrep -regex '.*\.(c|cpp|h)' -type f -exec sed -i \
-e 's/INTERP_QUALIFIER_/INTERP_MODE_/g' \
-e 's/glsl_interp_qualifier/glsl_interp_mode/g' {} \;
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| da39ac9c5126825418c979989ea7e017554a0aaa |
|
22-Jun-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: support non-user_buffer consts
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 374ad2e2bd14b4fd0c161d41e3627793ffabe468 |
|
02-Jun-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use nir_shader_get_entrypoint() helper
Should also fix coverity warning: CID 1362454
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| b65bd3dee5d84f4bd7806518282299960d426dc1 |
|
16-May-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix compiler warning
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 53cde5e295077e2a51df3a3d0db474cff5c10313 |
|
21-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: handle VARYING_SLOT_PNTC
In the glsl->tgsi path, this already gets translated to VAR8, which
matches up with rasterizer->sprite_coord_enable.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 2f1581059b31a99e8f15dff6339a4bd80baebe1b |
|
21-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: disable TGSI specific hacks in nir case
When we got NIR directly from state tracker (vs using tgsi_to_nir) we
need to realize this and skip some TGSI specific hacks.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 784086f3c1f50ca78fe62f925dfe66fb3aa5f22c |
|
28-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add support for NIR as preferred IR
For now under debug flag, since only suitable for debugging/testing.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8623e599fc050e33a1e19bc7f5aac59bc7fa3ae3 |
|
10-May-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: size input/output arrays properly
We index into these based on var->data.driver_location, which might have
gaps (ie. two inputs, one w/ drvloc 0 and other 2). This shows up in
(for example) 'bin/copyteximage 1D', but was only noticed recently due
to additional asserts.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| f33083a216563abac307c414bba2e32dc7405fea |
|
06-May-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: allow for additional VS sysval inputs
There are a total of four possible currently, rather than 2. So we need
to be prepared for the input array to grow by 16 components. We could
get away with less if we could pack sysval inputs.. and the way this is
handled currently isn't really the nicest thing. But it's a tactical
fix for an issue hit in:
GL31-CTS.gtf30.GL3Tests.transform_feedback.transform_feedback_vertex_id
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| b15c7fc268785cc8c960368d287ec799fe9dc502 |
|
11-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add ir3_cp_ctx
Needed in next commit.. just split out to reduce noise.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 9464d8c49813aba77285e7465b96e92a91ed327c |
|
27-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir: Switch the arguments to nir_foreach_function
This matches the "foreach x in container" pattern found in many other
programming languages. Generated by the following regular expression:
s/nir_foreach_function(\([^,]*\),\s*\([^,]*\))/nir_foreach_function(\2, \1)/
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 707e72f13bb78869ee95d3286980bf1709cba6cf |
|
27-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir: Switch the arguments to nir_foreach_instr
This matches the "foreach x in container" pattern found in many other
programming languages. Generated by the following regular expression:
s/nir_foreach_instr(\([^,]*\),\s*\([^,]*\))/nir_foreach_instr(\2, \1)/
and similar expressions for nir_foreach_instr_safe etc.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| adf795432f788b33822d3a94b704be4ca536c8f1 |
|
19-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: better workaround for astc+srgb
This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions. But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures. Work around this
setting up a second texture state and using that to sample alpha
separately.
This way, srgb->linear conversion happens in hw *prior* to
interpolation.
This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 216225ce57de3987aefc2c052eebe54b9c312bc0 |
|
12-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix array textures on a4xx
Seems like a4xx needs offset added to array index for all arrays,
whereas a3xx only for cubemap arrays. Fixes a whole swath of dEQP fails
(roughly *sampler2darray*).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 506b561ba7e3df2a7759dded684fae84bf459f65 |
|
05-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: insert extra move into phi
We had an implicit assumption that the phi src was assigned in it's
source (pred) block leading into the phi. But this is not true with
NIR, so we can't just ignore the source block specified in the
nir_phi_src. Insert an extra mov in the source block. If it is not
required the CP pass will take it back out again.
Fixes:
./tests/spec/glsl-1.10/execution/vs-call-in-nested-loop.shader_test
./tests/spec/glsl-1.10/execution/vs-inner-loop-modifies-outer-loop-var.shader_test
and probably others.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 38ae05a340bdf526d5da62159223ad9938fea36a |
|
04-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: drop unused instr category arg
No longer used, so drop the extra arg to ir3_instr_create()
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 19739e4fb9024f42a8fc332e6fa94c292bb6bc16 |
|
27-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: remove ir3_instruction::category
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 70735643f4cf660dc3022f40f853a138aea738c2 |
|
27-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: encode instruction category in opc_t
Been on my TODO list for a while. If nothing else this will make gdb
properly grok the opc_t enum.
This first step preserves ir3_instruction::category (with an added
assert that category matches what is encoded in opc_t). Next step is
to drop the category field (and arg to ir3_instr_create()), but that
is split into next commit for bisectability and so that we can run
piglit in the intermediate state to flush out any problems.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| b4c72b792caecd8be271af20de92d24b4ae7da4c |
|
22-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix for load_front_face intrinsic
Seems like trying to widen in the same instruction as the add.s does a
non-sign-extending widen.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 3ca034cada87aea58a92113cb38cf92a97d70c55 |
|
06-Feb-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix compiler warn
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 084b24f5582567ebf5aa94b7f40ae3bdcb71316b |
|
16-Mar-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
nir: rename nir_const_value fields to include bitsize information
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 2a7ceb5957c4be718122a5451efdfbcfffcaa691 |
|
16-Feb-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: fix new gcc6 errors
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c: In function ‘emit_tex’:
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c:1368:26: warning: unused variable ‘const_off’ [-Wunused-variable]
struct ir3_instruction *const_off[4];
^~~~~~~~~
unused since:
commit 8750299a420af76cebd3067f6f603eacde06ae06
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Tue Feb 9 14:51:28 2016 -0800
nir: Remove the const_offset from nir_tex_instr
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8750299a420af76cebd3067f6f603eacde06ae06 |
|
09-Feb-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir: Remove the const_offset from nir_tex_instr
When NIR was originally drafted, there was no easy way to determine if
something was constant or not. The result was that we had lots of
special-casing for constant values such as this. Now that load_const
instructions are SSA-only, it's really easy to find constants and this
isn't really needed anymore.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| ee85014b90af1d94d637ec763a803479e9bac5dc |
|
06-Feb-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir/tex_instr: Rename sampler to texture
We're about to separate the two concepts. When we do, the sampler will
become optional. Doing a rename first makes the separation a bit more
safe because drivers that depend on GLSL or TGSI behaviour will be fine to
just use the texture index all the time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8b0fb1c152fe191768953aa8c77b89034a377f83 |
|
21-Jan-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| f15447e7c9dc1e00973b02098637da0aa74de7d5 |
|
27-Jan-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: ignore clip-vertex varying
Since we emulate clip-planes, the clip-vertex is used within the VS
itself (thanks to nir_lower_clip). So just ignore it as a VS output.
Fixes a boatload of piglit tests that were asserting on unknown
varying slot.
(Also unrelated spelling/typo fix.)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| f20cf22b54dfda13324aa714debe55a8f093640d |
|
07-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: don't ignore local vars
With glsl_to_nir we end up with local variables, instead of global, for
arrays.
Note that we'll eventually have to do something more clever, I think,
when we support multiple functions, but that will probably take some
work in a few places.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8039a2a6b377f5d2a047fda82f6eaaa0a6a79a94 |
|
05-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: handle tex instrs w/ const offset
Something we start to see with glsl_to_nir.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| f212d7dc50a6a81e65f146d0ccef5776ec5e497f |
|
05-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: support load_front_face intrinsic
With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE.
But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 6a33c5c0dffce136bdc95daa2db2d3e9d3c1741f |
|
16-Jan-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: array offset can be negative
It at least happens with some piglit tests, like
$piglit/bin/vp-address-01
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..7]
DCL ADDR[0]
0: ARL ADDR[0].x, IN[1].xxxx
1: MOV_SAT OUT[1], CONST[ADDR[0].x-1]
2: DP4 OUT[0].x, CONST[4], IN[0]
3: DP4 OUT[0].y, CONST[5], IN[0]
4: DP4 OUT[0].z, CONST[6], IN[0]
5: DP4 OUT[0].w, CONST[7], IN[0]
6: END
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| fad158a0e01f4c28851477e6d1eb5c8fd67e226b |
|
10-Jan-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: array rework
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 2809c87f90e359bd94f1bd15d7615ea28010779a |
|
09-Jan-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: remove unused tgsi tokens ptr
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 23bd6affb24662e9e8dbe1ed353babd17b5a016d |
|
26-Oct-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: we require block_index metadata
Found during NIR_TEST_CLONE=1 piglit run. We were using block->index
but forgetting to require it. Causing things to not work with a cloned
shader which didn't preserve block_index.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 74135f804a4f18040a0a62664df67d35c8090d1d |
|
24-Oct-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: refactor NIR IR handling
Immediately convert into NIR and do an initial key-agnostic lowering/
optimization pass. This should let us share most of the per-variant
transformations between each variant, and hopefully minimize the draw-
time variant creation part of the compilation process.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| ab4efb19dc4dd5f4e5822f90178f0edba1c4095a |
|
21-Dec-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: drop unnecessary unreachable() case
It will still hit a compile_assert() in emit_tex, which has the
advantage of dumping out the offending shader.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 237f2f2d8b45d9d956102eec6f9be63193e5269b |
|
26-Dec-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir: Get rid of function overloads
When Connor originally drafted NIR, he copied the same function+overload
system that GLSL IR had with a few names changed. However, this
double-indirection is not really needed and has only served to confuse
people. Instead, let's just have functions which may not have unique names
and may or may not have an implementation. If someone wants to do overload
resolving, they can hav a hash table based function+overload system in the
overload resolving pass. There's no good reason to keep it in core NIR.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
ir3 bits are
Reviewed-by: Rob Clark <robclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 843cec6d3a5cd2ef0986ddcaa0960895b99f066b |
|
23-Dec-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: spelling..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 7d539080c1a491aff9fb3e90c25df89884477aa8 |
|
17-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
nir: Add a writemask to store intrinsics.
Tessellation control shaders need to be careful when writing outputs.
Because multiple threads can concurrently write the same output
variables, we need to only write the exact components we were told.
Traditionally, for sub-vector writes, we've read the whole vector,
updated the temporary, and written the whole vector back. This breaks
down with concurrent access.
This patch prepares the way for a solution by adding a writemask field
to store_var intrinsics, as well as the other store intrinsics. It then
updates all produces to emit a writemask of "all channels enabled". It
updates nir_lower_io to copy the writemask to output store intrinsics.
Finally, it updates nir_lower_vars_to_ssa to handle partial writemasks
by doing a read-modify-write cycle (which is safe, because local
variables are specific to a single thread).
This should have no functional change, since no one actually emits
partial writemasks yet.
v2: Make nir_validate momentarily assert that writemasks cover the
complete value - we shouldn't have partial writemasks yet
(requested by Jason Ekstrand).
v3: Fix accidental SSBO change that arose from merge conflicts.
v4: Don't try to handle writemasks in ir3_compiler_nir - my code
for indirects was likely wrong, and TTN doesn't generate partial
writemasks today anyway. Change them to asserts as requested by
Rob Clark.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3]
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 78b81be627734ea7fa50ea246c07b0d4a3a1638a |
|
25-Nov-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir: Get rid of *_indirect variants of input/output load/store intrinsics
There is some special-casing needed in a competent back-end. However, they
can do their special-casing easily enough based on whether or not the
offset is a constant. In the mean time, having the *_indirect variants
adds special cases a number of places where they don't need to be and, in
general, only complicates things. To complicate matters, NIR had no way to
convdert an indirect load/store to a direct one in the case that the
indirect was a constant so we would still not really get what the back-ends
wanted. The best solution seems to be to get rid of the *_indirect
variants entirely.
This commit is a bunch of different changes squashed together:
- nir: Get rid of *_indirect variants of input/output load/store intrinsics
- nir/glsl: Stop handling UBO/SSBO load/stores differently depending on indirect
- nir/lower_io: Get rid of load/store_foo_indirect
- i965/fs: Get rid of load/store_foo_indirect
- i965/vec4: Get rid of load/store_foo_indirect
- tgsi_to_nir: Get rid of load/store_foo_indirect
- ir3/nir: Use the new unified io intrinsics
- vc4: Do all uniform loads with byte offsets
- vc4/nir: Use the new unified io intrinsics
- vc4: Fix load_user_clip_plane crash
- vc4: add missing src for store outputs
- vc4: Fix state uniforms
- nir/lower_clip: Update to the new load/store intrinsics
- nir/lower_two_sided_color: Update to the new load intrinsic
NIR and i965 changes are
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NIR indirect declarations and vc4 changes are
Reviewed-by: Eric Anholt <eric@anholt.net>
ir3 changes are
Reviewed-by: Rob Clark <robdclark@gmail.com>
NIR changes are
Acked-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 58efff89a2af1d3996255f76cda510f2c2d9bda0 |
|
05-Dec-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: nir shader prints with 'disasm' debug option
Move these to 'disasm' instead of the more verbose 'optmsgs' since, like
the tgsi dumps, it is useful without the more verbose compiler logging
enabled.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| ad2cc7bddc094639508e4942310dbd2896be7774 |
|
03-Dec-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: don't reuse a0.x across blocks
It causes confusion in sched if we need to split_addr() since otherwise
we wouldn't easily know which block the new addr instr will be scheduled
in. So just side-step the whole situation.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8e52344dc1bd801a81ac773bb0010de5eca726f3 |
|
03-Dec-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: rename ir3_block::bd
We'll need to add similar for ir3_instruction, but following the pattern
to use 'id' seems confusing. Let's just go w/ generic 'data' as the
name.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 57fc0dd8d5610a0a25cece53b172b0c992421db0 |
|
26-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: assign varying locations later
Rather than assigning inloc up front, when we don't yet know if it will
be unused, assign it last thing before the legalize pass.
Also, realize when inputs are unused (since for frag shader's we can't
rely on them being removed from ir->inputs[]). This doesn't make sense
if we don't also dynamically assign the inloc's, since we could end up
telling the hw the wrong # of varyings (since we currently assume that
the # of varyings and max-inloc are related..)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 754b26e76dd7738a3dc5d6be8eb5a6d7b256ee1a |
|
22-Nov-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/ir3: add support for a few gs5 ops
Tested on a4xx. This is part of the builtins added by ARB_gpu_shader5
and GLSL ES 3.10.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 190acb34ca165c840f87a25149eab1d1b7dc85c4 |
|
22-Nov-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a4xx: add ARB_texture_query_lod support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| f58813842bcece3498f55ec5d582466ccff92a5e |
|
15-May-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir: s/nir_type_unsigned/nir_type_uint
v2: do the same in tgsi_to_nir (Samuel)
v3: added missing cases after rebase (Iago)
v4: Add a blank space after '#' in one of the comments (Matt)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 457bb290efc162ea3c7c51a820ab7cf88a4efb8d |
|
18-Nov-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
nir: Add nir_texop_samples_identical opcode
This is the NIR analog to GLSL IR ir_samples_identical.
v2: Don't add the second nir_tex_src_ms_index parameter. Suggested by
Ken and Jason.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8f55ebe802ea930d14eef9cd622aeb9a8d989e01 |
|
16-Oct-2015 |
Boyan Ding <boyan.j.ding@gmail.com> |
freedreno/ir3: Use nir_foreach_variable
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| c9b982b72d443b138cfbded2f40350771c0bb321 |
|
09-Oct-2015 |
Rob Clark <robclark@freedesktop.org> |
glsl: move shader_enums into nir
First step towards inverting the dependency between glsl and nir (so nir
can be used without glsl). Also solves this issue with 'make distclean'
Making distclean in mesa
make[2]: Entering directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa'
Makefile:2486: ../glsl/.deps/shader_enums.Plo: No such file or directory
make[2]: *** No rule to make target '../glsl/.deps/shader_enums.Plo'. Stop.
make[2]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa'
Makefile:684: recipe for target 'distclean-recursive' failed
make[1]: *** [distclean-recursive] Error 1
make[1]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src'
Makefile:615: recipe for target 'distclean-recursive' failed
make: *** [distclean-recursive] Error 1
Reported-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 9ffc1049cae07e4e2d2dc8f4d1f5f113b4b1fdc4 |
|
17-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use nir two-sided-color lowering
With this, we completely switch over to nir lowering passes instead of
tgsi_lowering. So one step closer to supporting direct glsl or spirv to
nir support for freedreno a3xx/a4xx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| c71cb670ba786a4bc443d23e6aa4b866e069dcd2 |
|
16-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: lower txp/clamp in NIR
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 91ec210ea8e35af8a7b30fa599b67b1faa55f34c |
|
10-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add support for ucp
Use nir_lower_clip pass for adding the VS/FS instructions to handle
user-clip-planes and CLIPDIST. Wire up support for load_user_clip_plane
intrinsic to fetch ucp[plane] values as driver-params (passed as const's
to the shader).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| c4572b7dfe7a4ae9dc6e900f89786fa9cf7769df |
|
11-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: convert from tgsi semantic/index to varying-slot
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| e523f69b1d2f0cb3ff7659e3c55b9a2e40240c9c |
|
10-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: switch to shader_enums.h interp constants
A small step towards un-TGSI'ifying ir3.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8fd3e53f3dc40e4013348e63a0cc7a2787410899 |
|
04-Aug-2015 |
Eric Anholt <eric@anholt.net> |
gallium/ttn: Convert to using VARYING_SLOT_* / FRAG_RESULT_*.
This avoids exceeding the size of the .index bitfield since it got
truncated, and should make our NIR look more like the NIR that the rest of
the NIR developers are working on.
v2: split out vc4 updates, first patch uses varying_slot_to_tgsi_semantic()
helper, and second patch does the actual conversion.
v3: add frag_result_to_tgsi_semantic() helper and don't try to map
frag_results to semantic name/index as if they were varying_slot's
v4: use VERT_ATTRIB_ for VS inputs
v5: Fix vc4 build.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| b3958f9f8387b5967530ff77a08120074042c8e5 |
|
14-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use NIR to lower ffract instead of tgsi_lowering
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 59519c2283e91ce4b8c2028673d6d8dc4ee5138f |
|
13-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix compile warn after 1807a08e
New enum to add to switch so compiler doesn't complain.
commit 1807a08e4f35b014f2a80d1e88dd74a9f096d7a5
Author: Ilia Mirkin <imirkin@alum.mit.edu>
AuthorDate: Thu Aug 27 23:05:03 2015 -0400
Commit: Ilia Mirkin <imirkin@alum.mit.edu>
CommitDate: Thu Sep 10 17:38:33 2015 -0400
nir: add nir_texop_texture_samples and convert from glsl
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8b2d0bb844e4c9b6141f68431b6e6dc135eb3503 |
|
25-Aug-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix compile break after fxn->start_block removal
The commit:
commit 8e0d4ef3410ea07d9621df3e083bc3e7c1ad2ab0
Author: Kenneth Graunke <kenneth@whitecape.org>
AuthorDate: Thu Aug 6 18:18:40 2015 -0700
nir: Delete the nir_function_impl::start_block field.
removed the start_block field without fixing up drivers..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| b4ace13eeae7ec58262d8a3ec38adca63b6add76 |
|
03-Aug-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a4xx: add cube map array support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 0667962103034d7426c763a7793ce22baab46c8e |
|
11-Aug-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use nir pass to lower const to scalar
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 98a4b111fbb9e3ae45e907ddd4d2407e5ab669ec |
|
25-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add transform-feedback support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 96d4db683f90f02e72d34ece544de7eedfa873ee |
|
25-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: track "keeps" in ir
Previously we had a fixed array to track kills, since they don't
generate an SSA value, and then cheated by stuffing them in the
outputs array before sending things through depth/sched/etc. But
store instructions will need similar treatment. So convert this
over to a more general array of instructions that must be kept
and fix up the places that were previously relying on kills being
in the output array.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| a240748de52f2e469e91b60d29ae872828a594d7 |
|
25-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: cleanup driver-param stuff
Add 'enum ir3_driver_param' to track driver-param slots, and a
create_driver_param() helper to avoid having the knowledge about
where driver params are placed in const regs spread throughout
the code as we add additional driver-params.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 810763deb514c3fec41c3e95761de34e6211d291 |
|
24-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: drop unused create_input() arg
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 0815729d964f4e8e6e263acf70b5b91577de027a |
|
23-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: bit of shader API refactoring
Since for transform-feedback, we'll need more than just the TGSI
tokens from the state object, just pass the entire state object to
ir3_shader_create(). This also cleans things up a bit for some
day in the future when we could take shader either as TGSI or
directly NIR (for ex, glsl2nir or spirv2nir paths). In the same
spirit, drop extra args from ir3_compile_shader_nir() (since it
can anyways get what it needs from the ir3_shader_variant).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| bc5e2bec303acd7fd962996bf369be5ce0e15cd2 |
|
23-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: updated cat6 encoding
Sync updated cat6 encoding from freedreno.git, needed to properly encode
store instructions.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 65b2ae510bb07b75f583ecedfd59766621e1cb43 |
|
06-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: shader-db traces
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 6b9f5cd5f7b25e9e03104fe279df74817f69fe87 |
|
02-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix indirects tracking
cp would update instr->address but not update the indirects array
resulting in sched getting confused when it had to 'spill' the address
register. Add an ir3_instr_set_address() helper to set instr->address
and also update ir->indirects, and update all places that were writing
instr->address to use helper instead.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 0a155538eb7e7870b99fb8b3fd8e2a268361d2c8 |
|
27-Jun-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
gallium/ttn: mark location specially in nir for color0-writes-all
We need to distinguish a shader that has separate writes to each MRT
from one which is supposed to write the data from MRT 0 to all the MRTs.
In TGSI this is done with a property. NIR doesn't have that, so encode
it as a funny location and decode on the other end.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| bb2c4b68f78f0105088c11408f8902fb22802125 |
|
26-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fixes for indirect writes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 01b5f1336330f1c0f937fb08a444efc593b43435 |
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25-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix constlen in case of load_uniform_indirect
We can't rely on what we get from the assembler if we have indirect
addressing of constant file, since the assembler doesn't know the array
index. This got lost in the transition to NIR.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 66a93a0ff9aa402c37aa9d00b4489715d611b496 |
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13-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: pass sz to split_dest()
For query_levels, we generate a getinfo with writemask of (z), which RA
will consider as size==3. But we were still generating four fanouts.
Which meant that RA would see it as two different register classes,
depending on the path to definer. Ie. on the getinfo instruction itself
it would see size==3, but when chasing back through the fanouts it would
see size==4.
Easiest way to solve that is to just generate the chain of neighboring
fanouts to have the correct size in the first place.
Note: we may eventually want split_dest() to take start/end or wrmask
instead, since really we only need size==1. But RA is not clever enough
for that, query_levels is not that common, and the other two registers
that get allocated are never used so those register slots can be
immediately re-used. So bunch of work for probably no real gain.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 1ee4d51e7a68f8f2dcb52a0e2f9af81fdbe078a2 |
|
12-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: add more opcodes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 43048c7093c367897fbcbb3ca8580e9c122cd6f6 |
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08-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: only unminify txf coords on a3xx
Seems like a4xx gets this right.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 0f008082b184072159e5aedc7fc103efba8740ed |
|
08-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno: remove int sampler shader variants
We get this information from NIR (which gets it from sview decl in tgsi
when translating from tgsi), so no need to maintain shader variants for
this.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 457f7c2a2a93b45396ac66e0d4b3896d2db8fdf3 |
|
09-Jun-2015 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: block reshuffling and loops!
This shuffles things around to allow the shader to have multiple basic
blocks. We drop the entire CFG structure from nir and just preserve the
blocks. At scheduling we know whether to schedule conditional branches
or unconditional jumps at the end of the block based on the # of block
successors. (Dropping jumps to the following instruction, etc.)
One slight complication is that variables (load_var/store_var, ie.
arrays) are not in SSA form, so we have to figure out where to put the
phi's ourself. For this, we use the predecessor set information from
nir_block. (We could perhaps use NIR's dominance frontier information
to help with this?)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| c8fb5f8a011e1db78af3ceaf91c5cb3b1acaee14 |
|
25-May-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: move inputs/outputs to shader
These belong in the shader, rather than the block. Mostly a lot of
churn and nothing too interesting. But splitting this out from the
rest of ir3_block reshuffling to cut down the noise in the later
patch.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| d52fb2f5ad828f879286b9068023b82b9897bc17 |
|
01-May-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/ra: use register_allocate
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 694beb8b830c993e9bfb744655be3dbd558ab3a8 |
|
23-May-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: introduce ir3_compiler object
Right now, just provides a cleaner way to get at the gpu-id, given the
separation between compiler and context. But we will need this also to
hold the reg-set for new register allocation.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 7674ab12e826d2ea33f13fb2e6ca8ae2a62fe460 |
|
09-Jun-2015 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: silence warnings
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 7273cb4e933f8be65fc73b9d8c69c76d1078cb14 |
|
30-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/sched: convert to priority queue
Use a more standard priority-queue based scheduling algo. It is simpler
and will make things easier once we have multiple basic blocks and flow
control.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 67d994c6761e09205dbc9a0515c510fc9dde02c7 |
|
30-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: drop dot graph dumping
At least for now.. right now the instruction and instruction list
printing should suffice, and the re-working of ir3_block would require
a lot of changes in that code.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 2126c68e5cba79709e228f12eb3062a9be634a0e |
|
20-May-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
nir: Get rid of the array elements parameter on load/store intrinsics
Previously, we used intrinsic->const_index[1] to represent "the number of
array elements to load" for load/store intrinsics. However, this set to 1
by every pass that ever creates a load/store intrinsic. Also, while it
might make some sense for registers, it makes no sense whatsoever in SSA.
On top of that, the i965 backend was the only backend to ever support it;
freedreno and vc4 just assert that it's always 1. Let's just delete it.
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 632ea2a1139f4b228ca55331e411dbae9920c28d |
|
22-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/nir: sysval fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 95e68adcd9f2589ae6d998328c72b84ffc49edc7 |
|
16-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: few little fixes
isaml needs to scale up coords based on LoD. Also fix bogus bary.f
varying # when there are non-bary frag shader inputs. And use sub.s of
a positive immediate rather than add.s of negative (since CP is better
about figuring out that those can be collapsed into the cat2 instr).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| efbf14e8936384ab1d243afbe3fa9bb0f40e3898 |
|
15-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: lower if/else
For now, completely flatten if/else blocks. That will almost certainly
change once we have flow control.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 57f0d3b3c6ae3b9f79a03517410b8dbfab0382c6 |
|
12-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: UBO support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| b98c0262d1183d24a37272558c51678cd6a0e9ec |
|
11-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: couple little fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 1b936bb9f8da72baaef5c7454e8bebb63bbe067a |
|
10-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: handle system values
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 715b2e0dbb88ef80880b8517f8fe822c26ef3be5 |
|
10-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: handle txs and query_levels tex ops
These correspond to the tgsi TXQ opcode
(plus sneak in a fix for two-sided color)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 97e8fc3fdd8a5e7e9e5635cfde81c3cb297e9f1a |
|
09-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: split out tex helpers
We'll need these in one or two other spots.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 6e8160d6e3ea7b000de112538dcbb0e29a6c3838 |
|
09-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: simplify emit_tex()
Just build up arrays for src0/src1, and use create_collect()..
Also add back missing .3d flag for 3d/cube textures.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 4cf4006674bd7c507688316e2033d77066c45c90 |
|
08-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: add variable-indexing support
A bit fugly.. try and make this cleaner.. note if we hoist all the
get_addr() out of the loop we can drop the hashtable and just use
create_addr()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 09cbd97a47a81f5d4b014adb5bdb9a490b24db82 |
|
06-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3/nir: set first_driver_param
Without this, a3xx breaks.. a4xx would too if it had already implemented
support for passing driver params.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|
| 8b0b81339b9c3806981ee2ec7c08501bbd8bb7a3 |
|
12-Mar-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add NIR compiler
The NIR compiler frontend is an alternative to the TGSI f/e, producing
the same ir3 IR and using the same backend passes for scheduling, etc.
It is not enabled by default yet, as there are still some regressions.
To enable, use 'FD_MESA_DEBUG=nir'. It is enough to use with, for
example, xonotic or supertuxkart.
With the NIR f/e, scalarizing and a number of other lowering steps
happen in NIR, so we don't have to do them in ir3. Which simplifies the
f/e and allows the lowered instructions to pass through other
optimization stages.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
|