45d9cd36fe9a3132e32f3efda0fbcbade2c71d21 |
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09-Nov-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
swr: [rasterizer memory] add support for R32_FLOAT_X8X24 formats This is the format used for the primary surface of a PIPE_FORMAT_Z32_FLOAT_S8X24_UINT resource. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h
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488992221056edaf7111f9290afdf216c5e98d62 |
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11-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core/sim] 8x2 backend + 16-wide tile clear/load/store Work in progress (disabled). USE_8x2_TILE_BACKEND define in knobs.h enables AVX512 code paths (emulated on non-AVX512 HW). Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h
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1b86c050adcb9c166c2aab2f4c6e41cc07686bf3 |
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06-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] update/add formats Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h
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2550b04179614da4c71dbef195d06a7f53273438 |
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07-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer memory] split load/store for compile speed Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h
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