| 75149088bea168a10f47df08fc62bcfeed744ce9 |
|
12-Dec-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core/memory] StoreTile: AVX512 progress
Fixes to 128-bit formats.
Reviwed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
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| 7aea08667c673713e1f419539e788eedeea047cb |
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08-Dec-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core/memory] Finish R24_UNORM_X8_TYPELESS for AVX512
This one-off specialization was missed.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
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| 5dd0b8d3c635b67d8274c64653d825b8855b8167 |
|
12-Nov-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
swr: [rasterizer memory] fix store tile for 128-bit ymajor tiling
Noticed by inspection.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
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| 45d9cd36fe9a3132e32f3efda0fbcbade2c71d21 |
|
09-Nov-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
swr: [rasterizer memory] add support for R32_FLOAT_X8X24 formats
This is the format used for the primary surface of a
PIPE_FORMAT_Z32_FLOAT_S8X24_UINT resource.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
|
| 937b7d8e5a97d1c3cc5ab7303c03dbdd2fdc8017 |
|
28-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] 16-wide tile store nearly completed
* All format combinations coded
* Fully emulated on AVX2 and AVX
* Known issue: the MSAA sample locations need to be adjusted for 8x2
Set ENABLE_AVX512_SIMD16 and USD_8x2_TILE_BACKEND to 1 in knobs.h to enable
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
|
| 488992221056edaf7111f9290afdf216c5e98d62 |
|
11-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core/sim] 8x2 backend + 16-wide tile clear/load/store
Work in progress (disabled).
USE_8x2_TILE_BACKEND define in knobs.h enables AVX512 code paths
(emulated on non-AVX512 HW).
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
|
| 1b86c050adcb9c166c2aab2f4c6e41cc07686bf3 |
|
06-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] update/add formats
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
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| 2550b04179614da4c71dbef195d06a7f53273438 |
|
07-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer memory] split load/store for compile speed
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
|