| 9c7717c066b4a315ed6dccd8a48d9eaf81a5b33f |
|
15-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Provide slice details to color resolver
v2: Make intel_miptree_resolve_color() take start layer and
layer count.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 540395bf9bba2a255809328d019b58a318e19c83 |
|
09-Sep-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a copy_miptrees helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 348509269ead23cb7f953c174d400e6e3d17d723 |
|
19-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move blorp into src/intel/blorp
At this point, blorp is completely driver agnostic and can be safely moved
into its own folder. Soon, we hope to start using it for doing blits in
the Vulkan driver.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 8bd35d8bd2bff51b39baf559efd9f3a0e20fd2b0 |
|
19-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Remove the remaining brw prefixes from the blorp.h API
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 87a1cb697937fa01405b0a57470ee69b9cf19998 |
|
19-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move the hiz_op enum to blorp
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| bc159ff0f7364970dbcb4c73d47c57ddb1aa8303 |
|
18-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add an "exec" function pointer to blorp_context
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| a14d1b63ce74773bec34d0c2b24b7d6fc36d0330 |
|
16-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a blorp_context struct and init/finish funcs
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| f5fbcc36831cd23ee9402a9fb8a9fb70d6ac412d |
|
09-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Split brw_blorp.c/h into multiple files
This mega-commit pulls most of the i965-specific bits of blorp into the
brw_blorp.c/h files which now contain nothing but i965 wrappers around
"core blorp" calls. The "core blorp" api is moved into blorp.h and the
internal blorp data structures are moved into blorp_priv.h. The new file
blorp.c is created to house "core blorp" internals which are pulled from
the old brw_blorp.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 8fccdf85ba329dc4ccd5764e430ae8d9abce0c69 |
|
20-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Make the guts of brw_blorp_blit_miptrees miptree-unaware
Now that we have the brw_blorp_surf struct, we can start to make bits of
blorp completely miptree-unaware. To start things off, we split the guts
of brw_blorp_blit_miptrees into a brw_blorp_blit function which knows
nothing about miptrees.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 75deae9c9064382976aa261e1ff3057939c22cd5 |
|
20-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a new brw_blorp_surf intermediate struct
At the moment, this seems to make all of the interfaces messier rather than
clener. However, it does provide a representation of a surface that
simultaneously contains everything and is completely unaware of miptrees.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| d8644f3eb6d24c50f8fbad4820e5b9e7803d09c3 |
|
20-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Do gen6 stencil offsets up-front
This keeps all of the nastyness of gen6 stencil on the i965 side of the API
line and lets us delete that nasty hand-rolled ISL-based offset path that
we were using for ALL_SLICES_AT_EACH_LOD.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 406c503396b3b4ab01d97d3e90eb09f2ed10a281 |
|
22-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Set up HiZ surfaces up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 4d86b3fa2dbc38bffdd87de7d6e81b488a068155 |
|
02-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i964/blorp: Set up most aux surfaces up-front
This commit also adds support for an offset for aux surfaces. In GL, this
only gets used for HiZ on SNB at the moment. However, in Vulkan, all aux
surfaces are at a non-zero offset and that is likely to happen in GL
eventually.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| d540864730f2cfa36366a47021554ac00b625b58 |
|
22-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Stop using the miptree in state setup for tex/rt surfaces
This commit movies us from a miptree model to a surf+bo+offset model. In
the GL driver, miptrees are almost always at the start of the bo so the
offset is zero but we don't want to always make that assumption. In the
sort term, gen6 stencil and HiZ will be at an offset but, in the long term,
any Vulkan surface is liable to be at a non-zero offset.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 56746d04d59f711d5ace0b86f2b2da96bd337ea1 |
|
28-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Remove unused fields from blorp_surface_info
The only reason why we need layer or level is that we need the z-offset for
3-D surfaces. Let's just have the one field for that.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 96fa98c18e54a31622a0dea5516f7db7642ca866 |
|
27-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Only do offset hacks for fake W-tiling and IMS
Since the dawn of time, blorp has used offsets directly to get at different
mip levels and array slices of surfaces. This isn't really necessary since
we can just use the base level/layer provided in the surface state. While
it may have simplified blorp's original design, we haven't been using the
blorp path for surface state on gen8 thanks to render compression and
there's really no good need for it most of the time. This commit restricts
such surface munging to the cases of fake W-tiling and fake interleaved
multisampling.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 9f9abc82149839159a5fe5412ad09daa4f80442d |
|
28-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a z_offset field to blorp_surface_info
The layer field is in terms of physical layers which isn't quite what the
sampler will want for 2-D MS array textures.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| c097160463c678c5544bfa8cda9cc3ef67361f4e |
|
17-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Get rid of brw_blorp_surface_info::width/height
Instead, we manually mutate the surface size as needed.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 7997f4f95b59a48a579d5f57a26a89dbcc5b2c7f |
|
24-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add an isl_view to blorp_surface_info
Eventually, this will be the actual view that gets passed into isl to
create the surface state. For now, we just use it for the format and the
swizzle.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| e046a4646090aa6b96664d128af70fd36cc2e065 |
|
24-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Move intratile offset calculations out of surface state setup
Previously we multiplied full x/y offsets, resolved tile aligned buffer
offset and intra tile offset based on that. Now we let ISL to take into
account the msaa setting and we only multiply the resolved intra tile
offsets.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 3c25caa318b70e603a11441d5459a0b55fbca0a2 |
|
24-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Get rid of brw_blorp_surface_info::array_layout
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 09879eff30ad4501bf72c1f3d0a45779be0235a6 |
|
24-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout
We also remove brw_blorp_surface_info::msaa_layout.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| e2a1bdb3c524f0a25bc311b1025e257f6b16cfaa |
|
24-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 28b0ad890c5d99092bcff5a38a9491b0716d014d |
|
23-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Get rid of brw_blorp_surface_info::num_samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| aa4117a9e45928289ba193506b377d06d1e09584 |
|
23-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled
Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 801189e1994a0daa96ff64b9f27a2e14b19cb446 |
|
23-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Remove compute_tile_offsets
We have a handy little function is ISL that does exactly the same thing.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| b82de88008ddfef051eeccfbc4b36e0e7d47daf3 |
|
23-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Create the isl_surf up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 6553dc0d70efef4f4ee5dbcb3e2ae404ff3c9460 |
|
10-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a generic ISL-based surface state emit path
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| fa0654fc3c3051fb4230cad3623227256b6f5c79 |
|
05-Jul-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Remove trailing whitespace
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| d92ac671261de20952eeb9d352a9ef37db0f9b4f |
|
05-Jul-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Make inline function static
Without this the i965 driver fails to load.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 175e09574443845e746d8cb3e9738ac776ce78a1 |
|
18-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Remove support for push constants
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 07db95c24d00d0d06d9dbdf678006a1636e857cd |
|
18-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Fix the size requirement for vertex elements
v2: Rebased as this is needed before flat inputs are enabled
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 741a245ae41546f9e2660575e90beb17fccc333f |
|
17-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Load tranformation coordinates as vec4
In preparation for loading as flat vertex input.
v2: Use LOAD_INPUT() macro
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 641868103c07366eb0fd3091c15cad0917c6cc36 |
|
17-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Organize pixel kill and blend/scaled inputs into vec4s
In addition, as these are never used in parallel, add a few
assertions.
v2 (Jason): Skip some complexity by putting them into a union but
pad rectangle grid into a vec4 instead. Also keep the
LOAD_UNIFORM macro.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 9e3774a4606b826921f1c0ea7d8afd8f91049758 |
|
18-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Prepare for more than two vertex attributes
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 9b2fa17e97f2a6161c0aea6872b6e3823de626d0 |
|
31-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Store input read mask
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 73f78ab44bff8e02b699940f830d50789d4edf34 |
|
17-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Rename push constants to inputs
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| f5e8575ab474f0b30e37b527b47ebb0b03bf6997 |
|
15-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Use prog data counters to guide sf/sbe setup
just as core upload logic does.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 672cffee0f24a40585c6c0a77caedd3aa0af60b1 |
|
11-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Get rid of the blorp_prog_data_int() helper
The helper was initially created to allow us to set reasonable defaults as
we mutated the brw_blorp_prog_data structure in preparation for NIR. Now
that everything is going through brw_blorp_compile_nir_shader() which fully
fills out the brw_blorp_prog_data structure, we don't need the helper.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| c1fe8859d3ec28bd7046390a1c0e9ec76074e2d1 |
|
28-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a helper for compiling NIR shaders
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 353eadb1703c2ac43200642ef329e8d2b5db9cea |
|
10-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
blorp: Add initial state setup support for SIMD8 dispatch
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| cd5a2905cf0721b71bcc5a7ef41a540ab5deb675 |
|
28-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a param array to prog_data
This array allows the push constants to be re-arranged on upload. The
actual arrangement will, eventually, come from the back-end compiler.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| c46cbe19f455b27fec717d8a80b2b07995424048 |
|
28-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Add a prog_data_init helper
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| ba9f954e603a1976125e9fdccc35e32ac947c8fd |
|
17-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Set full resolve for lossless compressed
v2 (Ben): Introduce union for fast clear and resolve ops
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 0551f3dfa4a14108dda58eceba3522c9071b2a90 |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Make all of brw_blorp.h accessible to C
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| b3f08b5424f581092b375c335c722fced25fb40e |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Turn brw_blorp_params into a C-style struct
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 33fa12c50f2e5e4fd4cfde1234ed6fdcc612fe92 |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Turn coord_transform into a C-style struct
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| b6dd8e42f09d98a536a38c33383238ec3595d066 |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Turn blorp_surface_info into a C-style struct
This commit is mostly mechanical except that it changes where we set the
swizzle. Previously, the blorp_surface_info constructor defaulted the
swizzle to SWIZZLE_XYZW. Now, we memset to zero and fill out the swizzle
when we setup the rest of the struct.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| a543f741bf33e4632d4d43b797bdcd0e04c7983f |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Roll mip_info into surface_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 38399364978f5576aae71a70d735b4d1b3a8e4dc |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Get rid of the blorp_blit_params class
It was really just a wrapper around the function that constructed it.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 8096ed7e27abc0619f4a4298481e1e072aa91828 |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Remove the hiz params class
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 659400cba371ec102c568e34b9f5feb00debf4c1 |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Remove the arguments to brw_blorp_params()
No one was using anything other than the defaults.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 2dda4ff014aba08df484cce94621c7844d4e4ee8 |
|
22-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Refactor to get rid of the get_wm_prog virtual function
Instead of having a virtual member function for getting the WM/PS kernel,
we simply add fields for prog_data and the kernel to brw_blorp_parms and
always make sure those get set as part of the different constructors.
v2: Use use prog_data != NULL to check for a valid program instead of a
magic kernel offset value
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 0e850452d1af72ae2af3a77892483bd1564af481 |
|
22-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp/gen6: Use normal base state address setup
This is identical to the blorp version which only differs in case
fragment shader isn't used. In that case blorp would reset batch
buffer address to zero.
This is not really needed, and having blorp to use base state
address setup that is compatible with normal upload allows one to
skip resetting it.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 87d333f2fe9e0be458eeff21ea70087ba524e9fa |
|
01-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Re-introduce clear programs
This partially reverts 2f28a0dc23165123cf1e8b5942acad37878edd8a
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| c40b1efa700cb594e397fd9ab839aa89cbbb067a |
|
03-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Switch the order of render and texture targets
On gen8 color resolving won't work anymore if the target isn't
the first entry in the binding table.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 4c3de6b2d651e43d686085872b916a04f4444930 |
|
03-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Add support for disabling color blending
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| da5a477ce413e4355eb5d826d112459629087fb0 |
|
01-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Add support for setting fast clear operation
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 9e4d19372b1d7f6ab12ddab1929a53335d9cce06 |
|
08-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Add support for sampling 3D textures
This patch adds additional MOV instruction for all blorp programs
that use SHADER_OPCODE_TXF. Alternative is to augment blorp program
key to tell if z-coordinate is needed, add condition to the blorp
blit compiler and to produce a variant with and without the MOV.
This seems a little overkill.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 6b33d63d77ab7835b5883140e54316e86e73888d |
|
09-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Add support for source swizzle
In order to support cases where gen9 uses RGBA format to back client
requested RGB, one needs to have means to force alpha channel to one
when user requested RGB surface is used as blit source.
v2 (Ken): Use helper for constructing the swizzle (this should be
changed to use brw_get_texture_swizzle() as a follow-up).
Also calculate the swizzle for CopyTexSubImage.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 52e7008a5a3655c9bd0abf8bfeb5110a98723e57 |
|
29-Mar-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Pipeline upload support for gen8
v2 (Ken): Drop GEN8_RASTER_FRONT_WINDING_CCW in raster state
Add emission of pma stall.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 395abb9c3b8b7b1a3e757e6dfee5b23cf9cf5753 |
|
01-Mar-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp/gen7: Expose state setup applicable to gen8
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 8679bb7c9e8bcf25639664fa2bd02cd2a3de9e52 |
|
17-Mar-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/blorp: Refactor sRGB encoding/decoding.
Because the rules for sRGB are so insane, we change brw_blorp_miptrees
to take decode_srgb and encode_srgb flags, which control linearization
of the source and destination separately.
This should make it easy to implement whatever crazy combination of
rules people throw at us. For now, it should be equivalent.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| f36993b46962eab4446bc1964eb47149751aee26 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Clean up #includes in the compiler.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 836aaa43943f5f7e112f6ea4750ffa8e0e530afd |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Remove useless gen6_blorp.h/gen7_blorp.h headers.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| dfd896699d9f640518c0fbafb0352f454d5fc466 |
|
27-Mar-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Add support for layered rendering
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 91daf9f09bac41c84c6868a56e0d538cc59cc334 |
|
26-Mar-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Allow blend state to be set for multiple render targets
Original blorp writes only one buffer per shader invocation. Once
the launch mechanism is shared with glsl-based programs there will
be need for supporting multiple render targets.
Also drop the always constant color write disable settings.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 7fb0db4dd18e49d3ccdb872f7ed174740301f3a2 |
|
27-Feb-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Prepare for attributes other than render position
Note that the magic number of one in gen7 logic is replaced by
BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity.
On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET)
has no effect for native blorp as blorp doesn't use any
additional attributes. In fact, regular pipeline setup always
uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional
attributes. Hence the change makes the two (blorp and regular)
consistent.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 25ce6c6943576e22d8d00049578d0e6cc5feea07 |
|
30-Jan-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Remove unused arguments
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 4de0bef7f438147091a7489728c4d187c6efbbc3 |
|
27-Feb-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Allow caller to provide sampler settings
v2 (Ken): s/use_unorm_coords/non_normalized_coords/
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| d271a13ba31168e0de75d7d4c1d4d7a2e2fb136c |
|
14-Mar-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Remove constant parameter
This was still needed when we had support for blorp clears but now
this is fixed to nop.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 7599886b26853163ef354476be70aa7fd9ae35c5 |
|
03-Sep-2014 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Pass image formats seperately from the miptree
When a texture is wrapped in a texture view, we can't trust the format in
the miptree itself. This patch allows us to pass the format seperately
through blorp so we can proprerly handled wrapped textures.
It's worth noting here that we can use the miptree format directly for
depth/stencil formats because they cannot be reinterpreted by a texture
view.
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
CC: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 7e856d0b180d3fc0c25f94156ded4a539f456030 |
|
14-Jun-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Change mipmap array_spacing_lod0 to array_layout (enum)
We will want to setup gen6 separate stencil and hiz miptrees in a
layout that is similar to array_spacing_lod0. This is needed because
gen6 hiz and stencil only support a single mip-level.
In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz),
the array slices will be packed at each LOD without reserving extra
space for LODs within each array slice.
So, we generalize the name of this field and add comments to indicate
the old and new uses.
Motivation for the gen6 change comes from the PRM:
PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
"The separate stencil buffer does not support mip mapping, thus the
storage for LODs other than LOD 0 is not needed."
PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
"[DevSNB]: The hierarchical depth buffer does not support the LOD
field, it is assumed by hardware to be zero. A separate
hierarachical depth buffer is required for each LOD used, and the
corresponding buffer’s state delivered to hardware each time a new
depth buffer state with modified LOD is delivered."
v2:
* Rename array_spacing_lod0 to non_mip_arrays
v3:
* Instead, replace array_spacing_lod0 with array_layout enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 2f28a0dc23165123cf1e8b5942acad37878edd8a |
|
08-Jul-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Implement fast color clears using meta operations
This patch uses the infrastructure put in place by previous patches
to implement fast color clears and replicated color clears in terms of
meta operations.
This works all the way back to gen7 where fast clear was introduced and
adds support for fast clear on gen8. It replaces the blorp path
completely and improves on a few cases. Layered clears are now done
using instanced rendering and multiple render-target clears use a
MRT shader with rep16 writes.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 3d1a4d1f5b26400878fa99c723759a2c54721de2 |
|
27-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make BLORP use brw_emit_sampler_state().
This simplifies the code, removes use of the old structures, and also
allows us to combine the Gen6 and Gen7+ code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 3de11cacf0cb307ff3b4130746732d9db73d7583 |
|
30-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use enum brw_reg_type for register types.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| a5957f7bc5e3618243f03cf9459394f9a83e5971 |
|
31-Mar-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: glClearBuffer() should only clear a single buffer.
glClearBuffer() is currently clearing all active draw color buffers (all
buffers that have not been set to GL_NONE when calling glDrawBuffers) instead
of only clearing the one it receives as parameter. Altough brw_clear()
receives a bit mask indicating the color buffers that should be cleared,
this mask is ignored when calling brw_blorp_clear_color().
This was breaking the 'fbo-drawbuffers-none glClearBuffer' piglit test.
The patch provides the bit mask to brw_blorp_clear_color() so it can limit
clearing to the color buffers present in the mask.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76832
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 50a01d2acafb2a937e62b24258e2e777c0cd1489 |
|
21-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: Change many Type A MESA_FORMATs to meet naming standard
Update comments. Conversion of the following Type A formats:
s/MESA_FORMAT_RGB888\b/MESA_FORMAT_BGR_UNORM8/g
s/MESA_FORMAT_BGR888\b/MESA_FORMAT_RGB_UNORM8/g
s/MESA_FORMAT_A8\b/MESA_FORMAT_A_UNORM8/g
s/MESA_FORMAT_A16\b/MESA_FORMAT_A_UNORM16/g
s/MESA_FORMAT_L8\b/MESA_FORMAT_L_UNORM8/g
s/MESA_FORMAT_L16\b/MESA_FORMAT_L_UNORM16/g
s/MESA_FORMAT_I8\b/MESA_FORMAT_I_UNORM8/g
s/MESA_FORMAT_I16\b/MESA_FORMAT_I_UNORM16/g
s/MESA_FORMAT_R8\b/MESA_FORMAT_R_UNORM8/g
s/MESA_FORMAT_R16\b/MESA_FORMAT_R_UNORM16/g
s/MESA_FORMAT_Z16\b/MESA_FORMAT_Z_UNORM16/g
s/MESA_FORMAT_Z32\b/MESA_FORMAT_Z_UNORM32/g
s/MESA_FORMAT_S8\b/MESA_FORMAT_S_UINT8/g
s/MESA_FORMAT_SRGB8\b/MESA_FORMAT_BGR_SRGB8/g
s/MESA_FORMAT_RGBA_16\b/MESA_FORMAT_RGBA_UNORM16/g
s/MESA_FORMAT_SL8\b/MESA_FORMAT_L_SRGB8/g
s/MESA_FORMAT_Z32_FLOAT\b/MESA_FORMAT_Z_FLOAT32/g
s/MESA_FORMAT_XBGR16161616_UNORM\b/MESA_FORMAT_RGBX_UNORM16/g
s/MESA_FORMAT_XBGR16161616_SNORM\b/MESA_FORMAT_RGBX_SNORM16/g
s/MESA_FORMAT_XBGR16161616_FLOAT\b/MESA_FORMAT_RGBX_FLOAT16/g
s/MESA_FORMAT_XBGR16161616_UINT\b/MESA_FORMAT_RGBX_UINT16/g
s/MESA_FORMAT_XBGR16161616_SINT\b/MESA_FORMAT_RGBX_SINT16/g
s/MESA_FORMAT_XBGR32323232_FLOAT\b/MESA_FORMAT_RGBX_FLOAT32/g
s/MESA_FORMAT_XBGR32323232_UINT\b/MESA_FORMAT_RGBX_UINT32/g
s/MESA_FORMAT_XBGR32323232_SINT\b/MESA_FORMAT_RGBX_SINT32/g
s/MESA_FORMAT_XBGR8888_UINT\b/MESA_FORMAT_RGBX_UINT8/g
s/MESA_FORMAT_XBGR8888_SINT\b/MESA_FORMAT_RGBX_SINT8/g
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 73e8bd9f5c7cc026dc1e7c5b030f8949a1805d6b |
|
03-Dec-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Get rid of redundant num_samples blorp param.
Previously, brw_blorp_params contained two fields for determining
sample count: num_samples (which determined the multisample
configuration of the rendering pipeline) and dst.num_samples (which
determined the multisample configuration of the render target
surface). This was redundant, since both fields had to be set to the
same value to avoid rendering errors.
This patch eliminates num_samples to avoid future confusion.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| b5fe413b4d665cdb7a9be6ebae23a6c5f3ec393d |
|
04-Dec-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Document conventions for counting layers in 2D multisample buffers.
The "layer" parameters used in blorp, and the
intel_renderbuffer::mt_layer field, represent a physical layer rather
than a logical layer. This is important for 2D multisample arrays on
Gen7+ because the UMS and CMS multisample layouts use N physical
layers to represent each logical layer, where N is the number of
samples.
Also add an assertion to blorp to help catch bugs if we fail to follow
these conventions.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 185b5a54c94ce11487146042c8eec24909187ed6 |
|
18-Jun-2013 |
Eric Anholt <eric@anholt.net> |
i965: Avoid flushing the batch for every blorp op.
This brings over the batch-wrap-prevention and aperture space checking
code from the normal brw_draw.c path, so that we don't need to flush the
batch every time.
There's a risk here if the intel_emit_post_sync_nonzero_flush() call isn't
high enough up in the state emit sequences -- before, we implicitly had
one at the batch flush before any state was emitted, so Mesa's workaround
emits didn't really matter. Since the SNB fixes by Ken, I didn't see any
regressions after 3 piglit runs.
Improves cairo-gl performance by 13.7733% +/- 1.74876% (n=30/32)
Improves minecraft apitrace performance by 1.03183% +/- 0.482297% (n=90).
Reduces low-resolution GLB 2.7 performance by 1.17553% +/- 0.432263% (n=88)
Reduces Lightsmark performance by 3.70246% +/- 0.322432% (n=126)
No statistically significant performance difference on unigine tropics
(n=10)
No statistically significant performance difference on openarena (n=755)
The two apps that are hurt happen to include stalls on busy buffer
objects, so I think this is an effect of missing out on an opportune
flush.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 4b2e819e10138dba6961d44f07af6de13750a832 |
|
07-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/blorp: Add an is_render_target parameter to surface_info::set.
This allows us to determine whether we're setting up a format for
the source (as a texture) or destination (as a render target).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 079bdba05f870807d3ed77fa3093cdb7727aa2fd |
|
18-Jul-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/blorp: Add support for single sample scaled blit with bilinear filter
Currently single sample scaled blits with GL_LINEAR filter falls
back to meta path. Patch removes this limitation in BLORP engine
and implements single sample scaled blit with bilinear filter.
No piglit, gles3 regressions are observed with this patch on Ivybridge.
V2: Use "sample" message to utilize the linear filtering functionality
built in to hardware.
V3: Define a bool variable (bilinear_filter) to handle the conditions
for GL_LINEAR blits.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 6066fb1721e937ebb1ab48034e744c17a9ee78b5 |
|
18-Jul-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/blorp: Use more appropriate variable names
When we talk about both multi-sample and single-sample scaled blits,
rect_grid_{x1, y1} are more appropriate variable names as compared
to sample_grid_{x1, y1}. There are no functional changes in this patch.
It just prepares for the BLORP implementation of single-sample scaled
blit with bilinear filter.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 6fc3da2da0cce869d807211fdd5e96bba9f003f7 |
|
31-May-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/blorp: Add bilinear filtering of samples for multisample scaled blits
Current implementation of ext_framebuffer_multisample_blit_scaled in
i965/blorp uses nearest filtering for multisample scaled blits. Using
nearest filtering produces blocky artifacts and negates the benefits
of MSAA. That is the reason why extension was not enabled on i965.
This patch implements the bilinear filtering of samples in blorp engine.
Images generated with this patch are free from blocky artifacts and show
big improvement in visual quality.
Observed no piglit and gles3 regressions.
V3:
- Algorithm used for filtering assumes a rectangular grid of samples
roughly corresponding to sample locations.
- Test the boundary conditions on the edges of texture.
V4:
- Clip texcoords and use conditional MOVs.
- Send texture dimensions as push constants.
- Remove the optimization in case of scaled multisample blits.
V5:
- Move mcs_fetch() inside the 'for' loop after computing pixel coordinates.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 418aecea7d626d57da8987c062aeb3d046c6dd9a |
|
06-May-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Write blorp code to do render target resolves.
This patch implements the "render target resolve" blorp operation.
This will be needed when a buffer that has experienced a fast color
clear is later used for a purpose other than as a render target
(texturing, glReadPixels, or swapped to the screen). It resolves any
remaining deferred clear operation that was not taken care of during
normal rendering.
Fortunately not much work is necessary; all we need to do is scale
down the size of the rectangle primitive being emitted, run the
fragment shader with the "Render Target Resolve Enable" bit set, and
ensure that the fragment shader writes to the render target using the
"replicated color" message. We already have a fragment shader that
does that (the shader that we use for fast color clears), so for
simplicity we re-use it.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab |
|
01-May-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7+: Implement fast color clear operation in BLORP.
Since we defer allocation of the MCS miptree until the time of the
fast clear operation, this patch also implements creation of the MCS
miptree.
In addition, this patch adds the field
intel_mipmap_tree::fast_clear_color_value, which holds the most recent
fast color clear value, if any. We use it to set the SURFACE_STATE's
clear color for render targets.
v2: Flag BRW_NEW_SURFACES when allocating the MCS miptree. Generate a
perf_debug message if clearing to a color that isn't compatible with
fast color clear. Fix "control reaches end of non-void function"
build warning.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 0a70fdfb3ffe2b03c037c64076fe4c6d3e8a0fe5 |
|
15-May-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
intel: Add multisample scaled blitting in blorp engine
In traditional multisampled framebuffer rendering, color samples must be
explicitly resolved via BlitFramebuffer before doing the scaled blitting
of the framebuffer. So, scaled blitting of a multisample framebuffer
takes two separate calls to BlitFramebuffer.
This patch implements the functionality of doing multisampled scaled
resolve using just one BlitFramebuffer call. Important changes involved
in this patch are listed below:
- Use float registers to scale and offset texture coordinates.
- Change offset computation to consider float coordinates.
- Round the scaled coordinates down to nearest integer.
- Modify src texture coordinates clipping to account for scaling..
- Linear filter is not yet implemented in blorp. So, don't use
blorp engine to do single sampled scaled blitting.
V3: Fix nearest filtering issue in scaled blits. Makes failing piglit
fbo-blit-stetch test and framebuffer_blit_functionality_magnifying_blit.test
in gles3 CTS pass.
Observed no piglit, gles3 CTS regressions on sandybridge & ivybridge with
this patch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 6e28713a8dceed021bdeaa881e1b4977ac8103ab |
|
08-May-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
intel: Change the register type from UW to UD in blorp engine
These changes are required to implement scaled blitting in blorp
in my next patch.
No regressions observed in piglit quick-driver.tests with this patch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| e56095dc2e40d6d1e37e123c694a609d16932b4a |
|
19-Mar-2013 |
Eric Anholt <eric@anholt.net> |
i965: Implement color clears using a simple shader in blorp.
The upside is less CPU overhead in fiddling with GL error handling, the
ability to use the constant color write message in most cases, and no GLSL
clear shaders appearing in MESA_GLSL=dump output. The downside is more
batch flushing and a total recompute of GL state at the end of blorp.
However, if we're ever going to use the fast color clear feature of CMS
surfaces, we'll need this anyway since it requires very special state
setup.
This increases the fail rate of some the GLES3conform ARB_sync tests,
because of the initial flush at the start of blorp. The tests already
intermittently failed (because it's just a bad testing procedure), and we
can return it to its previous fail rate by fixing the initial flush.
Improves GLB2.7 performance 0.37% +/- 0.11% (n=71/70, outlier removed).
v2: Rename the key member, use the core helper for sRGB, and use
BRW_MASK_* enums, fix comment and indentation (review by Paul).
v3: Rewrite a comment, drop a silly temporary variable (review by Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 87f4541bc1007dda1e345c16db94672620bc8fb2 |
|
20-Mar-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965/blorp: Add fields brw_blorp_mip_info::level,layer
The new fields define the 2D miptree slice to be used. A following patch
will pass the new fields through to intel_miptree_slice_has_hiz().
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 5c8dd6cf7995ae52a5482c1209c218f0b9a7b1c1 |
|
08-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Share the draw x/y offset masking code between main/blorp and all gens.
This code is twisty, and the comment before most of the blocks was actually
giving me the opposite impression from its intention: We want to apply as much
of our offset as possible through coarse tile-aligned adjustment, since we can
do so independently per buffer, and apply the minimum we can through
fine-grained drawing offset x/y, since it has to agree between all buffers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| f04f219906e40a6647a10fd9c1928509fe25fb84 |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Account for offsets when emitting SURFACE_STATE.
Fixes piglit tests "framebuffer-blit-levels {read,draw} depth".
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 3123f0621561549c4566248100661ef77cab2834 |
|
16-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
Previously, when performing a blit using the blorp engine, we failed
to account for the level and layer of the source and destination. As
a result, all blits would occur between miplevel 0 and layer 0 of the
corresponding textures, regardless of which level/layer was bound to
the framebuffer.
This patch passes the correct level and layer through
brw_blorp_miptrees() into the brw_blorp_blit_params data structure.
Further patches in the series will adapt
gen{6,7}_blorp_emit_surface_state to make use of these parameters.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d |
|
29-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: store x and y offsets in brw_blorp_mip_info.
Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and
dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface
offset is required). This is a bug, since the user might try to blit
to and from levels/layers other than 0.
To fix this bug, it will not be sufficient to have
gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the
time they set up the surface state, since these offsets will need to
be tweaked when blitting stencil buffers (due to the fact that stencil
buffer blits have to swizzle between W and Y tiling formats).
So, to pave the way for the bug fix, this patch causes the x and y
offsets to be computed during blit setup and stored in
brw_blorp_mip_info.
As a result of this change, brw_blorp_mip_info doesn't need to store
the level and layer anymore.
For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 09b0fa8499d8035fa31ccb2b550056305fbd149b |
|
29-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: store surface width/height in brw_blorp_mip_info.
Previously, gen{6,7}_blorp_emit_surface_state would look up the width
and height of the surface at the time they set up the surface state,
and then tweak it if necessary (it's necessary when a W-tiled surface
is being mapped as Y-tiled). With this patch, we look up the width
and height when setting up the blit, and store them in
brw_blorp_mip_info. This allows us to do the necessary tweak in the
brw_blorp_blit_params constructor (where it makes more sense). It
also reduces the need to keep track of level and layer in
brw_blorp_mip_info, so that a future patch can eliminate them
entirely.
For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| e42f16c19222dfbc093972e79bd1f7d23778c77e |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Fix incorrect indentation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 6cc9df331b4799715b31d7ec606ad09fa914e260 |
|
07-Aug-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Add function brw_blorp_blit_miptrees
Define a function, brw_blorp_blit_miptrees, that simply wraps
brw_blorp_blit_params + brw_blorp_exec with C calling conventions. This
enables intel_miptree.c, in a following commit, to perform blits with
blorp for the purpose of downsampling multisample miptrees.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| e5d983267a98bf9f73f0ea981eaca339b975a8db |
|
07-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Fix integer downsampling on Gen7.
When downsampling an integer-format buffer on Gen7, we need to use the
"avg" instruction rather than the "add" instruction, to ensure that we
don't overflow the range of 32-bit integers. Also, we need to use the
proper register type (BRW_REGISTER_TYPE_D or BRW_REGISTER_TYPE_UD) for
intermediate color data and for writing to the render target.
Note: this patch causes blorp to use the proper register type for all
operations (downsampling, upsampling, and ordinary blits). Strictly
speaking, this is only necessary for downsampling, because the other
operations exclusively use MOV instructions on the color data. But
it's simpler to use the proper register type in all cases.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 1bd4d456cdecf7bea55f4e3dac574af54efad994 |
|
04-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:
There are three types of multisampled surface layouts designated
as follows:
- IMS Interleaved Multisampled Surface
- CMS Compressed Mulitsampled Surface
- UMS Uncompressed Multisampled Surface
Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved. To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}. It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM. CMS layout is not yet used.
The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 67b0f7c7dddeb92ee4d24ed3977e20b70f5674f6 |
|
05-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Move {rt,tex}_interleaved into blorp program key.
On Gen6, MSAA buffers always use an interleaved layout and non-MSAA
buffers always use a non-interleaved layout, so it is not strictly
necessary to keep track of the layout of the texture and render target
surfaces in the blorp program key. However, it is cleaner to do so,
since (a) it makes the blorp compiler less dependent on implicit
knowledge about how the GPU pipeline is configured, and (b) it paves
the way for implementing compressed multisampled surfaces in Gen7.
This patch won't cause any redundant compiles, because the layout of
the texture and render target surfaces depends on other parameters
that are already in the blorp program key.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 530bda2aacf77b1e4661e5e5dd05cf108640e657 |
|
06-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Implement logic for additional buffer formats.
Previously the blorp engine only supported RGBA8 color buffers and
24-bit depth buffers. This patch adds support for any color buffer
format that is supported as a render target, and for 16-bit and 32-bit
depth buffers.
This required threading the brw_context struct through into
brw_blorp_surface_info::set() so that it can consult the
brw->render_target_format array.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 9dbd0b677815f50a782149f4e20118bbce318f81 |
|
06-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: De-virtualize brw_blorp_{mip,surface}_info::set() function.
Even though brw_blorp_surface_info is derived from brw_blorp_mip_info,
this function doesn't need to be virtual, because it is never accessed
through a base class pointer. Making the function non-virtual will
allow it to take additional parameters in the brw_blorp_surface_info
case.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 040d0157341381708c35c2f27721ebffa2ee1db2 |
|
06-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Refactor surface format determination.
This patch moves the responsibility for deciding on the format of the
source and destination surfaces from the
gen{6,7}_blorp_emit_surface_state() functions to
brw_blorp_surface_info::set(), which is shared between Gen6 and Gen7.
This will make it possible to add support for more surface formats
without code duplication.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 8b1f467cce34340637e9baca4847fc5273cf7541 |
|
08-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.
Since blorp uses color textures and render targets to do all its work
(even when blitting stencil and depth data), it always has to
configure the Gen7 GPU to use the new "sliced" MSAA layout. However,
when blitting stencil or depth data, the actual MSAA layout is
interleaved (as in Gen6). Therefore, blorp has to do extra coordinate
transformation work to account for the interleaving manually.
This patch causes blorp to perform the necessary extra coordinate
transformations.
It also modifies the blorp SURFACE_STATE setup code for Gen7, so that
it does not try to correct the surface width and height to account for
MSAA, since "sliced" MSAA layout doesn't affect the surface width or
height.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| 455ac562722f60ac9fb0c3d3c697fa339fa011ad |
|
08-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Properly handle sliced layout for Gen7.
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for depth and stencil
surfaces only.
- Sliced, in which the surface is stored as a 2D array, with array
slice n containing all pixel data for sample n. On Gen7 this layout
is used for color surfaces.
The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.
This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode. It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
|
| f77959b2c9053b1673418edfe5d74c9b139b2555 |
|
09-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.
This patch separates out the portions of gen6_blorp_emit_batch_head()
that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and
STATE_BASE_ADDRESS. This paves the way for making the blorp code work
on Gen7, where additional command packets
(3DSTATE_PUSH_CONSTANT_ALLOC_VS and 3DSTATE_PUSH_CONSTANT_ALLOC_PS)
need to be emitted before 3DSTATE_MULTISAMPLE.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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| 34a5f12e35dd4a5aff6683a8286d4582ba17df14 |
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09-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessary
This patch modifies the "blorp" WM program so that it can be run in
MSDISPMODE_PERSAMPLE (which means that every single sample of a
multisampled render target is dispatched to the WM program, not just
every pixel).
Previously we were using the ugly hack of configuring multisampled
destination surfaces as single-sampled, and generating sample indices
other than zero by swizzling the pixel coordinates in the WM program.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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| 5b226ad603302554f38e6b12a93bd2cf443d4b56 |
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21-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add an interface for doing hiz ops from C code.
This required moving gen6_hiz_op, and I put it in intel_resolve_map.h
for the next commit.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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| 6335e0b0738a6e466f0b712e30ad9fe506f67a6c |
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15-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Move exec() out of brw_blorp_params.
No functional change. This patch replaces the
brw_blorp_params::exec() method with a global function
brw_blorp_exec() that performs the operation described by the params
data structure.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
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30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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| 506d70be21cd3469118de89297cba0c0f709c1ae |
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30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Add code to perform blits on the render path ("blorp").
This patch expands the "blorp" component to be able to perform blits
as well as HiZ resolves. The new blitting code is located in
brw_blorp_blit.cpp. This includes the necessary fragment shader code
to look up pixels in the source buffer (which is configured as a
texture) and output them to the destination buffer (which is
configured as the render target).
Most of the time the fragment shader code is simple and
straightforward, since it merely has to apply a coordinate offset,
read from the texture, and write to the render target. However, in
the case of blitting stencil buffers, things are more complicated,
since the GPU stores stencil data using W tiling, and W tiling is not
supported for textures or render targets. So, we set up the stencil
buffers as Y tiled, and emit fragment shader code that adjusts the
coordinates to account for the difference between W and Y tiling.
Furthermore, since a rectangular region in W tiling does not
necessarily correspond to a rectangular region in Y tiling, we widen
the rectangle primitive to the nearest tile boundary and have the
fragment shader "kill" any pixels that don't fall inside the actual
desired destination rectangle.
All of this is a necessary prerequisite for implementing MSAA, since
we'll need to be able to blit between multisample color, depth, and
stencil buffers and their non-multisampled counterparts, and none of
the existing blitting mechanisms support multisampling.
In addition, the new blitting code should speed up operations where we
previously fell back to software rasterization, such as blitting of
stencil buffers. The current fallback sequence is: first we try to do
a blit using the hardware blitting engine. If that fails we try to do
a blit using the render path. If that also fails then we do the blit
using a meta-op (which may or may not fall back to software
rasterization).
Note that blitting using the render path has some limitations at the
moment: it only supports a few formats, and it doesn't support
clipping or scissoring. These limitations will be addressed in future
patch series.
v2:
- Add the code that configures the WM program to
gen{6,7}_emit_wm_config() and gen7_emit_ps_config() rather than
creating separate ...enable() functions.
- Call intel_prepare_render before determining which miptrees we are
blitting from/to, because it may cause miptrees to be reallocated.
- Allow the blit to mirror X and/or Y coordinates.
- Disable blorp blits on Gen7 for now, since they aren't working yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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| 586b3894744819071bb1ad56383e3c0d9e5b7e1f |
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30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: split gen{6,7}_blorp_exec functions into manageable chunks.
This patch splits up the gen6_blorp_exec and gen7_blorp_exec
functions, which were very long, into simple component functions.
With a few exceptions, there is one function per state packet.
This will allow blit functionality to be added without significantly
complicating the code.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
v2: Rename the functions gen{6,7}_emit_wm_disable() to
gen{6,7}_emit_wm_config() (since the WM is not actually disabled
during HiZ ops; it simply doesn't have a program). Also, on gen7,
split out the configration of 3DSTATE_PS to a separate function
gen7_emit_ps_config().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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| 2c5510b71b6348b686e76ecc2c34195080d566f4 |
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30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Parameterize HiZ code to prepare for adding blitting.
This patch groups together the parameters used by the HiZ functions
into a new data structure, brw_hiz_resolve_params, rather than passing
each parameter individually between the HiZ functions. This data
structure is a subclass of brw_blorp_params, which represents the
parameters of a general-purpose blit or resolve operation. A future
patch will add another subclass for blits.
In addition, this patch generalizes the (width, height) parameters to
a full rect (x0, y0, x1, y1), since blitting operations will need to
be able to operate on arbitrary rectangles. Also, it renames several
of the HiZ functions to reflect the expanded role they will serve.
v2: Rename brw_hiz_resolve_params to brw_hiz_op_params. Move
gen{6,7}_blorp_exec() functions back into gen{6,7}_blorp.h.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_blorp.h
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