| 8621961d4334bbfd51cb9e1934c6dcbc741699a9 |
|
17-Jan-2017 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/gen6: Issue direct depth stall and flush after depth clear
instead of calling unconditionally brw_emit_mi_flush() which
does:
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_CS_STALL);
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE);
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 46b346899d98e29943f8cd74c25bcb8d2f868a49)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 7d5a98f106b0695aca305bac8eb8833324bb8fe3 |
|
17-Jan-2017 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Make depth clear flushing more explicit
Current blorp logic issues unconditional "flush everything"
(see brw_emit_mi_flush()) after each render. For example, all
blits issue this unconditionally which shouldn't be needed if
they set render cache properly so that subsequent renders do
necessary flushing before drawing.
In case of piglit:
ext_framebuffer_multisample-accuracy all_samples depth_draw small
intel_hiz_exec() is always preceded by blorb blit and the
unconditional flush looks to hide the lack of stall and flushes
in depth clears. By removing the brw_emit_mi_flush() I get gpu
hangs.
This patch adds the stalls and flushes mandated by the spec
and gets rid of those hangs.
v2 (Jason, Ken): Document the rational for separating
depth cache flush and stall on Gen7.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit e6da6943fed1228c551af1f0e1a405b6d67b41ae)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 49c24d8a241ead2f0906d8e9523ab3aba0d8a73d |
|
19-Oct-2013 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: fix noop_scissor range issue on width/height
If scissor X or Y was set to a negative value then the previous
code might have indicated noop scissors when the scissor range
actually was masking a portion of the framebuffer.
Since fb->_Xmin, _Xmax, _Ymin and _Ymax take scissors into
account, we can use these to test for a noop scissor.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 87a1cb697937fa01405b0a57470ee69b9cf19998 |
|
19-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move the hiz_op enum to blorp
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 7bd87c1e6e168b048cdf2318af8848d07caa6706 |
|
12-Jun-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Track that the stencil data was updated when clearing
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 09e041d61d367ff3a9e8492521606090050255d4 |
|
12-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use blorp for all clears
We used to use a meta path on gen8 but we haven't since c7cf17ae758. We
might as well delete the meta path since blorp works on all gens.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| c7cf17ae758eff27dee8e06cc315841b34d3fe0a |
|
01-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Enable for normal color clears
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 76732932ec3918bb9cc04ccd37bc1a8c37051683 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Drop #include of main/glheader.h.
It's never used.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 8a0c85b25853decb4a110b6d36d79c4f095d437b |
|
08-Oct-2015 |
Chad Versace <chad.versace@intel.com> |
i965/gen9: Enable rep clears on gen9
The (gen < 9) check in brw_clear() was too broad. It disabled all types
of fast color clears:
a. singlesample rep clears
b. singlesample MCS fast clears
c. multisample MCS fast clears
The MCS clears are still buggy, but the rep clear works well. So let's
enable it.
Reviewed-by: Neil Roberts <neil@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 284dcad20a9a55278c1d3dd98f53e45650b22896 |
|
20-Aug-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Fix typos in license
grep -lr 'sub license' | while read f; do \
sed --in-place -e 's/sub license/sublicense/' $f ;\
done
grep -lr 'NON-INFRINGEMENT' | while read f; do \
sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\
done
As noted by Matt, both of these changes match the MIT license text found
at http://opensource.org/licenses/MIT.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| aa1a5c0c9e0de71ecd15e7190c121d6dd98471a6 |
|
20-Aug-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Remove horizontal bars from file header comments
Why was that ever a thing?
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9 |
|
30-Apr-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 77a44512d9ed56be5e53ebf09e917b5aeeba0189 |
|
05-Jun-2015 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965: Add buffer sizes to perf debug of fast clears
When we cannot do the optimized fast clear it's important to know the buffer
size since a small buffer will have much less performance impact.
A follow-on patch could restrict printing the message to only certain sizes.
Example:
Failed to fast clear 1400x1056 depth because of scissors. Possible 5% performance win if avoided.
Recommended-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| f7819650979d1fa5339af3eacfa1af1090bf53e8 |
|
04-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable fast color clears on Skylake for now.
We're not programming the clear values yet, so this won't work.
This patch should be (effectively) reverted eventually.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 2f28a0dc23165123cf1e8b5942acad37878edd8a |
|
08-Jul-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Implement fast color clears using meta operations
This patch uses the infrastructure put in place by previous patches
to implement fast color clears and replicated color clears in terms of
meta operations.
This works all the way back to gen7 where fast clear was introduced and
adds support for fast clear on gen8. It replaces the blorp path
completely and improves on a few cases. Layered clears are now done
using instanced rendering and multiple render-target clears use a
MRT shader with rep16 writes.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| e7f65655cbddc53a95ca9d9b6f5d738e82797aac |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Delete the intel_regions.c code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| a5957f7bc5e3618243f03cf9459394f9a83e5971 |
|
31-Mar-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: glClearBuffer() should only clear a single buffer.
glClearBuffer() is currently clearing all active draw color buffers (all
buffers that have not been set to GL_NONE when calling glDrawBuffers) instead
of only clearing the one it receives as parameter. Altough brw_clear()
receives a bit mask indicating the color buffers that should be cleared,
this mask is ignored when calling brw_blorp_clear_color().
This was breaking the 'fbo-drawbuffers-none glClearBuffer' piglit test.
The patch provides the bit mask to brw_blorp_clear_color() so it can limit
clearing to the color buffers present in the mask.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76832
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 058f353a159a6e34adb6d45462a18de86685a046 |
|
15-Feb-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Account for view parameters in fast depth clears
V2: - No need for layer_multiplier; multisampled depth surfaces are IMS.
- Remove unused num_layers.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| b18871c863fabec3ed383881d2cdd0298b157b06 |
|
23-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't forget to subtract mt->first_level in minify calls.
This fixes fbo-clear-formats GL_ARB_depth_texture on Ironlake, which
regressed since commit f128bcc7c293013f4b44e4b661638333de0077c2
("i965: Drop mt->levels[].width/height.") intel_miptree_copy_slice was
calling minify(.., 7) on a 2x2 texture with mt->first_level == 7.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75292
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 98e048cf323c22688bfa465153e648005e555d12 |
|
07-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable fast depth clears.
They work fine now, too.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| f128bcc7c293013f4b44e4b661638333de0077c2 |
|
14-Feb-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop mt->levels[].width/height.
It often confused people because it was unclear on whether it was the
physical or logical, and people needed the other one as well. We can
recompute it trivially using the minify() macro, clarifying which value is
being used and making getting the other value obvious.
v2: Fix a pasteo in intel_blit.c's dst flip.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| a487ef87fe4aa8c4b8e5c0d888bfb18727c8e570 |
|
08-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Fix MESA_FORMAT_Z24_UNORM_S8_UINT vs. X8_UINT mix-up.
In commit eeed49f5f290793870c60b5b635b977a732a1eb4, Mark accidentally
renamed MESA_FORMAT_S8_Z24 to MESA_FORMAT_Z24_UNORM_X8_UINT and
MESA_FORMAT_X8_Z24 to MESA_FORMAT_Z24_UNORM_S8_UINT, reversing their
sense. The commit message was correct, but what sed commands actually
got run didn't match that.
This patch swaps the two enum names, reversing them. This should undo
the damage, but might break things if people have manually fixed a few
instances in the meantime...
Mark's commit also failed to mention renames:
s/MESA_FORMAT_ARGB2101010_UINT\b/MESA_FORMAT_B10G10R10A2_UINT/g
s/MESA_FORMAT_ABGR2101010\b/MESA_FORMAT_R10G10B10A2_UNORM/g
but those seem okay.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 8e0a0e4d30be142235c2b2439fe82935b8c67888 |
|
07-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix fast depth clear values on Broadwell.
Broadwell's 3DSTATE_CLEAR_PARAMS packet expects a floating point value
regardless of format. This means we need to stop converting it to
UNORM.
Storing the value as float would make sense, but since we already have a
uint32_t field, this patch continues shoehorning it into that. In a
sense, this makes mt->depth_clear_value the DWord you emit in the
packet, rather than the clear value itself.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| eeed49f5f290793870c60b5b635b977a732a1eb4 |
|
27-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: Change many Type P MESA_FORMATs to meet naming spec
Conversion of Type P formats as follows (w/related comment fixes):
s/MESA_FORMAT_RGB565\b/MESA_FORMAT_B5G6R5_UNORM/g
s/MESA_FORMAT_RGB565_REV\b/MESA_FORMAT_R5G6B5_UNORM/g
s/MESA_FORMAT_ARGB4444\b/MESA_FORMAT_B4G4R4A4_UNORM/g
s/MESA_FORMAT_ARGB4444_REV\b/MESA_FORMAT_A4R4G4B4_UNORM/g
s/MESA_FORMAT_RGBA5551\b/MESA_FORMAT_A1B5G5R5_UNORM/g
s/MESA_FORMAT_XBGR8888_SNORM\b/MESA_FORMAT_R8G8B8X8_SNORM/g
s/MESA_FORMAT_XBGR8888_SRGB\b/MESA_FORMAT_R8G8B8X8_SRGB/g
s/MESA_FORMAT_ARGB1555\b/MESA_FORMAT_B5G5R5A1_UNORM/g
s/MESA_FORMAT_ARGB1555_REV\b/MESA_FORMAT_A1R5G5B5_UNORM/g
s/MESA_FORMAT_AL44\b/MESA_FORMAT_L4A4_UNORM/g
s/MESA_FORMAT_RGB332\b/MESA_FORMAT_B2G3R3_UNORM/g
s/MESA_FORMAT_ARGB2101010\b/MESA_FORMAT_B10G10R10A2_UNORM/g
s/MESA_FORMAT_Z24_S8\b/MESA_FORMAT_S8_UINT_Z24_UNORM/g
s/MESA_FORMAT_S8_Z24\b/MESA_FORMAT_Z24_UNORM_S8_UINT/g
s/MESA_FORMAT_X8_Z24\b/MESA_FORMAT_Z24_UNORM_X8_UINT/g
s/MESA_FORMAT_Z24_X8\b/MESA_FORMAT_X8Z24_UNORM/g
s/MESA_FORMAT_RGB9_E5_FLOAT\b/MESA_FORMAT_R9G9B9E5_FLOAT/g
s/MESA_FORMAT_R11_G11_B10_FLOAT\b/MESA_FORMAT_R11G11B10_FLOAT/g
s/MESA_FORMAT_Z32_FLOAT_X24S8\b/MESA_FORMAT_Z32_FLOAT_S8X24_UINT/g
s/MESA_FORMAT_ABGR2101010_UINT\b/MESA_FORMAT_R10G10B10A2_UINT/g
s/MESA_FORMAT_XRGB4444_UNORM\b/MESA_FORMAT_B4G4R4X4_UNORM/g
s/MESA_FORMAT_XRGB1555_UNORM\b/MESA_FORMAT_B5G5R5X1_UNORM/g
s/MESA_FORMAT_XRGB2101010_UNORM\b/MESA_FORMAT_B10G10R10X2_UNORM/g
s/MESA_FORMAT_AL88\b/MESA_FORMAT_L8A8_UNORM/g
s/MESA_FORMAT_AL88_REV\b/MESA_FORMAT_A8L8_UNORM/g
s/MESA_FORMAT_AL1616\b/MESA_FORMAT_L16A16_UNORM/g
s/MESA_FORMAT_AL1616_REV\b/MESA_FORMAT_A16L16_UNORM/g
s/MESA_FORMAT_RG88\b/MESA_FORMAT_G8R8_UNORM/g
s/MESA_FORMAT_GR88\b/MESA_FORMAT_R8G8_UNORM/g
s/MESA_FORMAT_GR1616\b/MESA_FORMAT_R16G16_UNORM/g
s/MESA_FORMAT_RG1616\b/MESA_FORMAT_G16R16_UNORM/g
s/MESA_FORMAT_SRGBA8\b/MESA_FORMAT_A8B8G8R8_SRGB/g
s/MESA_FORMAT_SARGB8\b/MESA_FORMAT_B8G8R8A8_SRGB/g
s/MESA_FORMAT_SLA8\b/MESA_FORMAT_L8A8_SRGB/g
Conflicts:
src/mesa/drivers/dri/i965/brw_surface_formats.c
src/mesa/main/format_pack.c
src/mesa/main/format_unpack.c
src/mesa/main/formats.c
src/mesa/main/texformat.c
src/mesa/main/texstore.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 50a01d2acafb2a937e62b24258e2e777c0cd1489 |
|
21-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: Change many Type A MESA_FORMATs to meet naming standard
Update comments. Conversion of the following Type A formats:
s/MESA_FORMAT_RGB888\b/MESA_FORMAT_BGR_UNORM8/g
s/MESA_FORMAT_BGR888\b/MESA_FORMAT_RGB_UNORM8/g
s/MESA_FORMAT_A8\b/MESA_FORMAT_A_UNORM8/g
s/MESA_FORMAT_A16\b/MESA_FORMAT_A_UNORM16/g
s/MESA_FORMAT_L8\b/MESA_FORMAT_L_UNORM8/g
s/MESA_FORMAT_L16\b/MESA_FORMAT_L_UNORM16/g
s/MESA_FORMAT_I8\b/MESA_FORMAT_I_UNORM8/g
s/MESA_FORMAT_I16\b/MESA_FORMAT_I_UNORM16/g
s/MESA_FORMAT_R8\b/MESA_FORMAT_R_UNORM8/g
s/MESA_FORMAT_R16\b/MESA_FORMAT_R_UNORM16/g
s/MESA_FORMAT_Z16\b/MESA_FORMAT_Z_UNORM16/g
s/MESA_FORMAT_Z32\b/MESA_FORMAT_Z_UNORM32/g
s/MESA_FORMAT_S8\b/MESA_FORMAT_S_UINT8/g
s/MESA_FORMAT_SRGB8\b/MESA_FORMAT_BGR_SRGB8/g
s/MESA_FORMAT_RGBA_16\b/MESA_FORMAT_RGBA_UNORM16/g
s/MESA_FORMAT_SL8\b/MESA_FORMAT_L_SRGB8/g
s/MESA_FORMAT_Z32_FLOAT\b/MESA_FORMAT_Z_FLOAT32/g
s/MESA_FORMAT_XBGR16161616_UNORM\b/MESA_FORMAT_RGBX_UNORM16/g
s/MESA_FORMAT_XBGR16161616_SNORM\b/MESA_FORMAT_RGBX_SNORM16/g
s/MESA_FORMAT_XBGR16161616_FLOAT\b/MESA_FORMAT_RGBX_FLOAT16/g
s/MESA_FORMAT_XBGR16161616_UINT\b/MESA_FORMAT_RGBX_UINT16/g
s/MESA_FORMAT_XBGR16161616_SINT\b/MESA_FORMAT_RGBX_SINT16/g
s/MESA_FORMAT_XBGR32323232_FLOAT\b/MESA_FORMAT_RGBX_FLOAT32/g
s/MESA_FORMAT_XBGR32323232_UINT\b/MESA_FORMAT_RGBX_UINT32/g
s/MESA_FORMAT_XBGR32323232_SINT\b/MESA_FORMAT_RGBX_SINT32/g
s/MESA_FORMAT_XBGR8888_UINT\b/MESA_FORMAT_RGBX_UINT8/g
s/MESA_FORMAT_XBGR8888_SINT\b/MESA_FORMAT_RGBX_SINT8/g
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| bdff9a6e47c42c0ba8cec2d8b5c5438c0068f874 |
|
18-Jan-2014 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Consider only the scissor rectangle for viewport 0 for clears
noop_scissor (correctly) only examines the scissor rectangle for
viewport 0. Therefore, it should only be called when that scissor
rectangle is enabled.
v2: Remove spurious change to radeon code. Noticed by Ken.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| a9c73fb778a41b422a811c67b4aba806d4dfb7c8 |
|
13-Nov-2013 |
Courtney Goeltzenleuchter <courtney@LunarG.com> |
mesa: Update gl_scissor_attrib to support ARB_viewport_array
Update Mesa and drivers to access updated gl_scissor_attrib.
Now have an enable bitfield and array of gl_scissor_rects.
Drivers have been updated to the new scissor enable state
attribute (gl_context.scissor.EnableFlags) but still treat it
as a single boolean which is okay as mesa will only use
bit 0 when communicating with a driver that does not support
ARB_viewport_array.
v2 (idr): Rebase fixes.
v3 (idr): Small code formatting fix suggsted by Ken.
Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 877128505431adaf817dc8069172ebe4a1cdf5d8 |
|
17-Jan-2014 |
José Fonseca <jfonseca@vmware.com> |
s/Tungsten Graphics/VMware/
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 532b1fecd93fd30d3b1b101b55fd2c6e074088ad |
|
07-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix clears of layered framebuffers with mismatched layer counts.
Previously, Mesa enforced the following rule (from
ARB_geometry_shader4's list of criteria for framebuffer completeness):
* If any framebuffer attachment is layered, all attachments must have
the same layer count. For three-dimensional textures, the layer count
is the depth of the attached volume. For cube map textures, the layer
count is always six. For one- and two-dimensional array textures, the
layer count is simply the number of layers in the array texture.
{ FRAMEBUFFER_INCOMPLETE_LAYER_COUNT_ARB }
However, when ARB_geometry_shader4 was adopted into GL 3.2, this rule
was dropped; GL 3.2 permits different attachments to have different
layer counts. This patch brings Mesa in line with GL 3.2.
In order to ensure that layered clears properly clear all layers, we
now have to keep track of the maximum number of layers in a layered
framebuffer.
Fixes the following piglit tests in spec/!OpenGL 3.2/layered-rendering:
- clear-color-all-types 1d_array mipmapped
- clear-color-all-types 1d_array single_level
- clear-color-mismatched-layer-count
- framebuffer-layer-count-mismatch
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 08315233509f1fa7dc1e877aed2a8517296cf86e |
|
20-Nov-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix fast clear of depth buffers.
From section 4.4.7 (Layered Framebuffers) of the GLSL 3.2 spec:
When the Clear or ClearBuffer* commands are used to clear a
layered framebuffer attachment, all layers of the attachment are
cleared.
This patch fixes the fast depth clear path.
Fixes piglit test "spec/!OpenGL 3.2/layered-rendering/clear-depth".
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 36c3faf4bf41d6618a3b0fcd565f4907a1633a40 |
|
29-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable BLORP on Broadwell for now.
BLORP is essential. However, porting it to Gen8 is a huge amount of
work. Disabling it for now allows us to proceed with basic hardware
enablement.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 7b36137642f8946bbc85b45124fefda38ca5332e |
|
29-Jul-2013 |
Jordan Justen <jordan.l.justen@intel.com> |
i965 clear/draw: set renderbuffer attachment as needing depth resolve
Previously we would mark a renderbuffer as needing a depth resolve.
But, to support layered rendering, we need to look at the attachment
instead, since the attachment knows if layered rendering is being
used.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 9147b4049658fe2401c19e03d20220aeea0fafc6 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move front buffer rendering fields from intel_context to brw.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| a69274454b6bde265a910ca5bd3199217431f5b5 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Replace #include "intel_context.h" with brw_context.h.
brw_context.h includes intel_context.h, but additionally makes the
brw_context structure available. Switching this allows us to start
using brw_context in more places.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| bc8b62e3a07bb50727332c509115b22ae417796c |
|
02-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move contents of intel_clear.h to intel_context.h.
Having a header file for a single prototype seems rather excessive.
Plus, the actual function is in brw_clear.c, not intel_clear.c, so
there isn't even the .c/.h filename symmetry one might expect.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab |
|
01-May-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7+: Implement fast color clear operation in BLORP.
Since we defer allocation of the MCS miptree until the time of the
fast clear operation, this patch also implements creation of the MCS
miptree.
In addition, this patch adds the field
intel_mipmap_tree::fast_clear_color_value, which holds the most recent
fast color clear value, if any. We use it to set the SURFACE_STATE's
clear color for render targets.
v2: Flag BRW_NEW_SURFACES when allocating the MCS miptree. Generate a
perf_debug message if clearing to a color that isn't compatible with
fast color clear. Fix "control reaches end of non-void function"
build warning.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| cbf3462c35445e8728ec6d58ed264e16705c1254 |
|
23-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Enable fast clears on non-8x4-aligned sizes.
Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11).
The workaround was to avoid bad primitive/surface sizes, but that's worked
around as of a14dc4f92cdad6177d83f051a088a66e31a973bc. (One might note
that pre-gen7 we don't know that the right half of an 8x4 at the right
edge is actually our pixels, but we're already clobbering those pixels for
depth resolves anyway and more work would be required to avoid that).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| e56095dc2e40d6d1e37e123c694a609d16932b4a |
|
19-Mar-2013 |
Eric Anholt <eric@anholt.net> |
i965: Implement color clears using a simple shader in blorp.
The upside is less CPU overhead in fiddling with GL error handling, the
ability to use the constant color write message in most cases, and no GLSL
clear shaders appearing in MESA_GLSL=dump output. The downside is more
batch flushing and a total recompute of GL state at the end of blorp.
However, if we're ever going to use the fast color clear feature of CMS
surfaces, we'll need this anyway since it requires very special state
setup.
This increases the fail rate of some the GLES3conform ARB_sync tests,
because of the initial flush at the start of blorp. The tests already
intermittently failed (because it's just a bad testing procedure), and we
can return it to its previous fail rate by fixing the initial flush.
Improves GLB2.7 performance 0.37% +/- 0.11% (n=71/70, outlier removed).
v2: Rename the key member, use the core helper for sRGB, and use
BRW_MASK_* enums, fix comment and indentation (review by Paul).
v3: Rewrite a comment, drop a silly temporary variable (review by Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 2d3bbc576c095f0942d131db886f5661dec5680c |
|
08-Apr-2013 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace checks for hiz_mt with intel_has*hiz()
When appropriate, replace each check `hiz_mt != NULL` with either a call
to intel_miptree_slice_has_hiz() or intel_renderbuffer_has_hiz(). No
behavioral change.
This prepares for selectively enabling hiz on individual miptree slices
for Haswell.
This refactoring had several side effects.
1. To prevent new warnings about discarding the const qualifier,
I removed 'const' from some variable declarations in
intel_validate_framebuffer(). The alternative was to add const
qualifiers to multiple function signatures in the
intel_renderbuffer_has_hiz call graph. Since the dominant convention
in the Intel code is to not qualify function parameters as const,
I chose to remove rather than add const qualifiers.
2. I changed the signature of brw_emit_depth_stencil_hiz() by replacing
`struct intel_mipmap_tree *hiz_mt` with `bool hiz`. The function used
hiz_mt mostly as a boolean indicator of the presence of hiz, so the
signature change is consistent with the patch's goal.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 0af56c9d53a454477645f4537b8086120a638d3e |
|
08-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Avoid unnecessary copy when depthstencil workaround invoked by clear.
Since apps typically begin rendering with a call to glClear(), it is
likely that when brw_workaround_depthstencil_alignment() moves a
miplevel to a temporary buffer, it can avoid doing a blit, since the
contents of the miplevel are about to be erased.
This patch adds the necessary plumbing to determine when
brw_workaround_depthstencil_alignment() is being called as a
consequence of glClear(), and avoids the unnecessary blit when it is
safe to do so.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Eliminate unnecessary call to _mesa_is_depthstencil_format(). Fix
handling of depth buffer in depth/stencil format.
v3: Use correct bitfields for clear_mask. Fix handling of depth
buffer in depth/stencil format when hardware uses separate stencil.
When invalidating, make sure we still reassociate the image to the new
miptree.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| c5d5827951fb321a58cc781b4e386551035ebf1a |
|
08-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Apply depthstencil alignment workaround when doing fast clears.
Fast depth clears have the same depth/stencil alignment requirements
as other drawing operations. Therefore, we need to call
brw_workaround_depthstencil_alignment() from both the clear and
drawing paths.
Without this fix, we get image corruption if the following conditions
hold: (a) the first ever drawing operation to a depth miplevel (or the
first drawing operation after having used the texture for sampling) is
a clear, (b) the depth miplevel has a size that is eligible for fast
depth clears, and (c) the depth miplevel has an offset within the
miptree that isn't 8x8 aligned.
Fixes piglit "depthstencil-render-miplevels" tests with size 273.
NOTE: This is a candidate for stable branches
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 097b4a3b28ecab81b356b86f04a939d24b94ae77 |
|
19-Sep-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Allow fast depth clears if scissoring doesn't do anything.
A game we're working with leaves scissoring enabled, but frequently sets
the scissor rectangle to the size of the whole screen. In that case,
scissoring has no effect, so it's safe to go ahead with a fast clear.
Chad believe this should help with Oliver McFadden's "Dante" as well.
v2/Chad: Use the drawbuffer dimensions rather than the miptree slice
dimensions. The miptree slice may be slightly larger due to alignment
restrictions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-and-tested-by: Oliver McFadden <oliver.mcfadden@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 5133bd6585552a5708b294180fa9a561bf7564a6 |
|
22-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: don't clear resolve map when doing fast depth clears.
Previously, when performing a fast depth clear, we would also clear
the miptree's resolve map. This destroyed important information,
since the resolve map contains information about needed resolves for
all levels and layers of the miptree, whereas a depth clear only
applies to a single level/layer combination at a time. As a result,
resolves would sometimes fail to occur, leading to incorrect
rendering.
Fixes rendering artifacts with shadow maps in Unigine Heaven and
Unigine Sanctuary.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50270
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| b4da272a6ea58a7c81c71477d65d82651555709a |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add performance debug for fast clear fallbacks.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 94f22fbe787214580a1a13a774114d2650c166cb |
|
08-Aug-2012 |
Tapani Pälli <tapani.palli@intel.com> |
intel: use _mesa_meta_Clear with OpenGL ES 1.1 v2
Patch changes i915 and i965 drivers to use fixed function version of
meta clear when running on ES 1.1. This fixes rendering errors seen with
Google Maps, Angry Birds and Gallery3D on Android platform.
Change 88128516d43be5d25288ff5b64db63cda83c04b3 exposes all extensions
internally to be available independent of GL flavour, therefore check
against ARB_fragment_shader does not work.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50333
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 68216f35814ab8d292f37b8c0fa0a5f181b7f20d |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for fast depth clears.
Improves citybench high-res performance 3.0% +- 0.4%, n=10. Improves
Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78). No
significant difference on openarena (n=5, didn't fast clear) or nexuiz
(n=3).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 7da9795070b1af746ab85692d4b65dbe8c4f2d76 |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Rename the clear function for this driver.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 3e1656567c3d2abb91f8169806d6083e80c0a673 |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Simplify the remaining clear logic by relying on the meta clear.
The GLSL clear path doesn't need any buffer presence checks, since
those are already handled in the normal drawing path code.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 7c3e88f1fc2aa9d3740163bcf8718e6d8709a204 |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Switch blit color clears to tri clears on gen4/5.
Our understanding is that the 3D engine is supposed to be faster
anyway. We used to have more overhead in our tri clear path than we
do today, which would have led to this choice. But given that we
almost always see a depth clear along with a color clear, the path was
hardly exercised anyway.
Also, the color mask logic was broken in the presence of
GL_EXT_draw_buffers2's per-buffer colormask.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| fa15b0f3f05ed5b6e96e9eda21d75ed7e8f1466f |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead logic for non-tri depth/stencil clears.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| a3967ff441e95289a0a33a4a02ab7cd15b010a51 |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: We always have GLSL, so always use it for tri clears.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|
| 11892ea986b5fdad345ce7c09f97e0389e546509 |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
intel: Fork the intel_clear.c file between i915 and i965.
This logic is wasted on i965 when we want to just always do GLSL tri
clears.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clear.c
|