| ab1ec7de9387a453a7e013ee7bb9b3514cd5b4bb |
|
14-Dec-2016 |
Samuel Iglesias Gonsálvez <siglesias@igalia.com> |
i965/disasm: remove printing hstride and width in align16 DF source regions
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 7c5bf597ef6eb4a33c9ba24827a34cd9fdd67363 |
|
25-May-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/disasm: fix subreg for dst in Align16 mode
There is a single bit for this, so it is a binary 0 or 1 meaning
offset 0B or 16B respectively.
v2:
- Since brw_inst_dst_da16_subreg_nr() is known to be 1, remove it
from the expression (Curro)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| ca63a3ce5107435197a6272233d66c8831cd3603 |
|
17-Jun-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/disasm: print NibCtrl for instructions with execsize < 8
v2 (Curro):
- Print it also for execsize < 4.
- QtrCtrl is still in effect, so print 2 * qtr_ctl + nib_ctl + 1
- Do not read the nib ctl from the instruction in gen < 7,
the field only exists in gen7+.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 611fe6b32fae09b3ae52afd4bdb7bae29eca99df |
|
25-May-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/disasm: align16 DF source regions have a width of 2
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| fd3120d85c295eeeb3b6c9a60372506ae48f5fdb |
|
09-Dec-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/disasm: Decode dataport constant cache control fields.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 979d0aca6277975986f5f278cad0f37616c9d91f |
|
26-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: Rename brw_get_device_name/info to gen_get_device_name/info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 527f37199929932300acc1688d8160e1f3b1d753 |
|
23-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: s/brw_device_info/gen_device_info/
Generated by:
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 71d639f69ee868fbeadd0a1b8bbdd76e17398b43 |
|
19-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/disasm: Fix RC message type strings on Gen7+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| a738732abf07e6264f079bbb31adb8723b8e91e3 |
|
14-Jul-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: fix compiler warnings for 32bit build
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 75dccf5ac2af716175990ae9eac44cc2c99b7e9c |
|
05-May-2016 |
Matt Turner <mattst88@gmail.com> |
i965: Add infrastucture for sample lod-zero operations.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| c0a1cd24a8bfefcd4a4b7065cc34c21273b1ad12 |
|
03-Aug-2015 |
Connor Abbott <connor.w.abbott@intel.com> |
i965: add support for disassembling DF immediates
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 367e762a714f2a254b3891ce8691d65a2a0e4b4e |
|
29-Jul-2015 |
Connor Abbott <connor.w.abbott@intel.com> |
i965/disasm: fix disasm of 3-src doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 667408b889e2bf5f103340c2deeb04c4d99cb75b |
|
30-Apr-2016 |
Matt Turner <mattst88@gmail.com> |
i965: Merge inst_info and opcode_desc tables.
I merged opcode_desc into inst_info (instead of the other way around)
because inst_info was sorted by opcode number.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 1530e27534831a8d1c82e0a82fe15cd9c70e61e6 |
|
28-Apr-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/disasm: Wrap opcode_desc look-up in a function.
The function takes a device info struct as argument in addition to the
opcode number in order to disambiguate between multiple opcode_desc
entries for different instructions with the same opcode number.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v1]
[v2] mattst88: Put brw_opcode_desc() in brw_eu.c instead of moving it
there in a later patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v2]
[v3] mattst88: Return NULL if opcode >= ARRAY_SIZE(opcode_descs)
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| ce84a92df54c738d2c248716f0f673247d50e1a7 |
|
08-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Decode per-slot offsets.
We just never bothered to decode this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 20c8f365081801b3370b705d18a01f13c181abe9 |
|
08-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Decode "channel mask present" bit correctly.
Bit 15 means "interleave" for most messages, but for SIMD8 messages it
means "use channel masks".
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| b790232524d46ef888a3657d205aa18502b09d3f |
|
08-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Simplify the URB opcode printing with ?:.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| f36993b46962eab4446bc1964eb47149751aee26 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Clean up #includes in the compiler.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0eb3db117b56b081ee2674cc8940c193ffc3c41b |
|
02-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Use BRW_MRF_COMPR4 macro in more places.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 9ab45b4df91fadcbbec62828265644d7463b78bb |
|
15-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Don't consider control flow instructions to have sources.
And why did IFF have a destination?
I suspect that once upon a time the disassembler used this information
to know which fields to find the jump targets in. The jump targets have
moved, so the disassembler has to know how to handle these
per-generation anyway.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0865e743c18cb7ba65962d794be8387d6edc0b8a |
|
29-Jun-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Fill out instruction list.
Add some instructions: illegal, movi, sends, sendsc.
Remove some instructions with reused opcodes: msave, mrestore, push,
pop, goto. I did have some gross code for disassembling opcodes
per-generation, but there's very little meaningful overlap so it's
probably not needed.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| e386fb0dee40d0f2342b43b6750b64c8174463a9 |
|
08-Sep-2015 |
Neil Roberts <neil@linux.intel.com> |
i965/fs/skl+: Use ld2dms_w instead of ld2dms
In order to support 16x MSAA, skl+ has a wider version of ld2dms that
takes two parameters for the MCS data. The MCS data retrieved from the
ld_mcs instruction already returns 4 or 8 registers and is documented
to return zeroes for the mcsh value when the sample count is less than
16.
v2: Use get_lowered_simd_width to fall back to SIMD8 instructions when
the message length would be too long in SIMD16.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 18b194925f5f80eccb53e07609083049b981d60c |
|
26-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Print the type and writemask on null destinations.
These are often useful in debugging, and the writemask (actually
"Channel Enables") determines more than just what goes into the
destination.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 5916b073f6b60b66e86a71b11cc3dc856d780144 |
|
26-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Remove unused _addr_mode argument from src_ia1().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 8cf84a7e470dbd3b46ce4081459d2ecfab22c2d5 |
|
09-Oct-2015 |
Alejandro Piñeiro <apinheiro@igalia.com> |
i965/vec4: print predicate control at brw_vec4 dump_instruction
v2: externalize pred_ctrl_align16 from brw_disasm.c instead of adding
a copy on brw_vec4.c, as suggested by Matt Turner
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0b91bcea98c0fe201bba89abe1ca3aee4d04c56c |
|
12-Aug-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
i965: add support for textureSamples function
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
[v2: kayden-supplied code in fs_nir replacing need for logical opcode]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| a9df772e0e76254ab232876016ec09b1fadbd700 |
|
06-Nov-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add defines for all new Gen7/8 URB opcodes
Tessellation needs to emit URB reads and atomics;
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4323e78d3f6d935cb75fc20375e6730613d41119 |
|
13-Aug-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Improve disassembly of data port read messages.
We now print out the name of the message instead of its numerical
value, and label the message control and surface numbers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| bdbbec33cf23193e1c81e0ecf28f2cc793d507bf |
|
05-Nov-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Disassemble Gateway SEND messages
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| a1c070c1a7c6b37a36f591bd8caf4619e4457eae |
|
19-May-2015 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Skip swizzle disassembly when using 3-src repctrl.
... since it's always .x, and also always print the subreg offset when
using repctrl.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 19165e3b6eff3a33379af127d27c6585ffbd1028 |
|
24-Apr-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disassemble sampler message names on Gen5+.
Previously, sampler messages were decoded as
sampler (1, 0, 2, 2) mlen 6 rlen 8 { align1 1H };
I don't know how much time we've collectly wasted trying to read this
format. I can never recall which number is the surface index, sampler
index, message type, or...whatever that other number is. Figuring out
the message name from the numerical code is also painful.
Now they decode as:
sampler sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
This is easy to read at a glance, and matches the format I used for
render target formats.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 639314d40e78b5b56c3fc840b2f416e7fc519a4d |
|
15-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Make the disassembler take a device_info instead of a context
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4e9c79c847c81701300b5b0d97d85dcfad32239a |
|
15-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Make the brw_inst helpers take a device_info instead of a context
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 50db8bd1b5942a6577ab5ee399cae460fde761d4 |
|
31-Mar-2015 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
i965/disasm: Print the type after the swizzle also for 3src src operands
The disassembly currently has the swizzle after the type for 3src source
operands, and the other way around for 2src. Flip the type and swizzle
around for 3src so that the output matches 2src.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 21ff9bfe1cea8c0a51e9f607cc580df62baa3445 |
|
13-Mar-2015 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/disasm: Fix format strings
Most of the brw_inst_* api returns 64bit values. This fixes disassembly
of sampler messages, etc.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 7c3095d6b71c410fd625ead797c78a0f5376904d |
|
13-Mar-2015 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/disasm: Mark format() as being printf-style.
This allows us to get warnings from GCC when we mess up the format
strings.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 27b6ef7ecaa60ce192ec74eef2245c25ed4e703b |
|
06-Feb-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add a function to disassemble an instruction from the 4 dwords.
I used this a while back when debugging GPU hangs, and it seems like it
could be useful, so I figured I'd add it so people can use it in the
debugger.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 937ddb419da28992eb7cc516459281758ff6b720 |
|
03-Nov-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Disassemble tdr and tm registers properly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 276075f8645613bbb814cb4c930c2bafe1aadfcb |
|
09-Mar-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Disassemble vector float immediates properly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| ff966aff999ceefd61f6e3eee1f1a60b8138d4d8 |
|
22-Nov-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Fix all32h/any32h predicate disassembly.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| ca39c46c3be82be0a36316e5da32b558c4837aea |
|
18-Nov-2014 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/disasm: Properly decode branch_ctrl (gen8+)
Add support for decoding the new branch control bit. I saw two things wrong with
the existing code.
1. It didn't bother trying to decode the bit.
- While we do not *intentionally* emit this bit today, I think it's interesting
to see if we somehow ended up with the bit set. It may also be useful in the
future.
2. It seemed to be the wrong bit.
- The docs are pretty poor wrt which bit this actually occupies. To me, it
/looks/ like it should be bit 28. I am not sure where Ken got 30 from. I
verified it should be 28 by looking at the simulator code.
I also added the most basic support for GOTO simply so we don't need to remember
to change the function in the future.
v2:
Move the branch_ctrl check out of the if gen >= 6 check to make it more
readable. (Matt)
ENDIF doesn't have branch_ctrl (Matt + Ken)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| f1261db1eea0bea739d5d9e6e1f4ef8192431e26 |
|
23-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/disasm: Add missing message type for Gen7 DP untyped surface read
This is used to implement GLSL's atomicCounter() intrinsic. Previously
it *worked*, but the disassembly was bogus.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 5a559557e672f94061b06ee82072ccc82d6f3491 |
|
14-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Add BRW_OPCODE_NENOP for G45.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4fcefac7531dbf2b17c0dc133ba52505486c936e |
|
26-Aug-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Show jump count for if/iff/halt.
These instructions don't have pop count.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| fb2fddefce75078bf6b1a904a65efc46c9ee6088 |
|
24-Aug-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Disassemble JMPI's source properly.
The source can be a register as well as an immediate, and disassembling
a register as an immediate can have some strange results.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| bef7a025ebd8bbe278b2740441db34484568021c |
|
22-Aug-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Add break/cont/halt to list of has_uip().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 383eccb77e3a2e4f4788455ada9ca7b4497ec8c7 |
|
24-Aug-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Disassemble Z/NZ conditional modifiers as .z/.nz.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 6cc6c3b6473ba838b86268ce2c60dfce4d5993d5 |
|
19-Aug-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Add CSEL.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| d6d3e6027de6c9bd409f4ed0cf47e4f6c2114df3 |
|
18-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't print WE_normal in disassembly.
Dropping this helps most lines fit in an 80 column terminal. The
absence of WE_normal also helps call attention to WE_all, where
something unusual is going on.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| caf8c07dd40b26ae3f4b8f1bf4ff26bd226a3b7b |
|
18-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Don't disassemble the URB complete field on Broadwell.
It doesn't exist, so attempting to read it will trigger generation
assertions in the brw_inst API.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0b0572a2ad4c7ca8b437589291e47180c733c371 |
|
18-Nov-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/disasm: add support for pixel interpolator messages
V3: Rework for brw_inst changes
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| f55e9a7c75b1a8539a9babab011c70b6442e2e2d |
|
06-Jul-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/disasm: Disassemble indirect sends more properly
- Don't try to disassemble send's src1 as a descriptor if it's not an
immediate.
- In the same case, show src1 as an operand (makes it easier to see
bogus register regions, etc -- the hardware is very fussy)
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 503391b46f753e1f8c0bc771776a51719d0507e4 |
|
06-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Fix disassembly of the any16h/all16h predicates.
BRW_PREDICATE_ALIGN1_ANY16H was incorrectly being disassembled as
"all16h", and ALL16H would probably print as "(null)".
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 7b7f95b95236747233feb8de5781a72e357a8dc4 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Improve render target write message disassembly.
Previously, we decoded render target write messages as:
render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0
which made you remember (or look up) what the numbers meant:
1. The binding table index
2. The raw message control, undecoded:
- Last Render Target Select
- Slot Group Select
- Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...)
3. The dataport message type, again (already decoded as "RT write")
4. The write commit bit (0 or 1)
Needless to say, having to decipher that yourself is annoying. Now, we
do:
render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0
with optional "Hi" and "WriteCommit" for slot group/write commit.
Thanks to the new brw_inst API, we can also stop duplicating code on a
per-generation basis.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0e5b52e35da17a4cef77e00fdcf65048ca6c9695 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Rename msg_target to SFID.
We haven't used the name "message target" in a while - there are a lot
of things called "target", and it gets confusing. SFID ("Shared
Function ID") is the term commonly used in the modern documentation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| c4cf088f43dc52d61661970324e7850b6c07c55b |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Fix typo in RT UNORM write message.
The name of this message is "Render Target UNORM Write" (Sandybridge
PRM, Volume 4 Part 1, Page 210). Drop the bogus 'c'.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 3603dfff6fc4d03f2c691eb9019d0ade1d5dfa3b |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Use Gen6+ SFID case labels.
Most developers will recognize the Gen6+ SFID names more quickly than
the Gen4-5 ones. Given that they're the same values, just use the new
names.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4fe78f4cc2fac1781a315151add77793adc61669 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: "Handle" Gen8+ HF/DF immediate cases.
We should print something properly, but I'm not sure how to properly
print an HF, and we don't have any DFs today to test with.
This is at least better than the current Gen8 disassembler, which would
simply assert fail.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| f36bebcd5c9d3f23d611c59a97ab49e93c8850ee |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Cut piles of duplicate swizzle printing.
Making a helper function saves us from cut and pasting this four times.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| bdcbcc73dd67892247e133309c65eb4677757eb0 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Properly decode negate source modifiers on Broadwell.
This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da
to brw_disasm.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 00b72bbab5678e29b61b34cd7f7fec9c25866ce9 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Improve disassembly of atomic messages on Haswell+.
This backports the atomic message disassembly support from
gen8_disasm.c, which additionally offers support for decoding atomic
surface read/write messages, and showing SIMD modes and other details.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| eb3185f6864acf43084a3e083902d943e481f759 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Actually disassemble Gen7+ URB opcodes.
I never bothered implementing the disassembler for Gen7+ URB opcodes, so
we were just disassembling them as Ironlake/Sandybridge ones. This
looked pretty bad when running Paul's GS EndPrimitive tests, as the
"write OWord" message was decoded at ff_sync, which doesn't exist.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| aa9e23dbe81977032e8e53211b46b6daef347cb8 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Decode Broadwell's invm/rsqrtm math functions.
We don't use these yet, but we may as well disassemble them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 9a91f92596908f2934350bc115bd889f2926128a |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 156c73a899efd9618cc791447e0b16ac8735c57e |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Properly disassemble all32h/any32h align1 predicates.
While we're adding things, use symbolic constants rather than magic
numbers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 707c42cb9601c64aa8dc7ac8d277b56d0a6b34a4 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Mark ELSE as having UIP on Gen8+.
This makes brw_disasm.c able to disassemble ELSE instructions correctly
on Broadwell. (gen8_disasm.c already handles this correctly.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| df4eeed0befc39385f3baa40b4f38183b9c76363 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Properly disassemble jump targets on Gen4-5.
Previously, our dissasembly for flow control instructions looked like:
0x00000040: else(8) ip 65540D { align16 switch };
It didn't print InstCount properly for ELSE/ENDIF, and didn't even
attempt to disassemble PopCount.
Now it looks like:
0x00000040: else(8) Jump: 4 Pop: 1 { align16 switch };
which is much more readable.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 6928959d8eba05b8a7d62d8829472ddc298bc8d1 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Improve disassembly of jump targets on Gen6+.
Previously, flow control instructions generated output like:
(+f0) if(8) 12 8 null 0x000c0008UD { align16 WE_normal 1Q };
which included a dissasembly of the register fields, even though those
are meaningless for flow control instructions---those bits are reused
for another purpose.
It also wasn't immediately obvious which number was UIP and which was
JIP.
With this patch, we instead output:
(+f0) if(8) JIP: 8 UIP: 12 { align16 WE_normal 1Q };
which is much clearer.
The patch also introduces has_uip/has_jip helper functions which clear
up a some generation/opcode checking mess.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 6497890bf426699c5a03b22eadc509808f31373f |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Add support for new Gen8+ register types.
While we're at it, use proper names rather than magic numbers for the
existing fields.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 5f106b03a96360314d231ad06c8b645d316700ee |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Restyle brw_disasm.c.
brw_disasm.c basically wasn't following the Mesa coding style at all.
It used 4-space indent instead of 3-space, didn't cuddle braces, didn't
put function return types on a separate line, put extra spaces in
function calls (between the name and parenthesis), and a number of other
things.
This made it fairly obnoxious to work on, since my editor is configured
to follow Mesa style in the Mesa source repository. Fixing it to follow
a consistent style now should save time dealing with it later.
These modifications were originally generated by:
$ indent -br -i3 -npcs -ce -cs -l80 --no-tabs
with some manual changes afterwards to fit our style better.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 5e20e9a830a4f6a3956e8c1bd21f94fd53b3ceb2 |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Create an "opcode" temporary.
This saves typing brw_inst_opcode(brw, inst) everywhere.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 3d1992754f4234756704a24242a2e8e93e2069bf |
|
29-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/disasm: Eliminate opcode pointer.
opcode is just a pointer to opcode_descs; we may as well use that
directly.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 7c2946fc237616e60ed1d3bb284256a3d1183c79 |
|
26-Jun-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disassemble all of DP write message control bits on Gen6.
Prior to the new brw_inst API, the brw_instruction structure split off
bits 4 and 5 of msg_control for specific fields, and we failed to
disassemble them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 7c79608b5b8a7eb4bed9fa9d594c9bda696dd49a |
|
13-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Replace 'struct brw_instruction' with 'brw_inst'.
Use this an an opportunity to clean up the formatting of some old code
(brw_ADD, for instance).
Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| bfbe6a7210b534fede5d5f24dc55dee9a78ef49b |
|
13-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Convert brw_disasm.c to the new brw_inst API.
v2: (by Kenneth Graunke)
- Fix disassembly of Gen4-5 SEND messages to print base MRF correctly.
- Only print URB opcode on Gen5+, to match previous output (besides,
there is only one opcode AFAICT.)
- Only print the low 3 bits of msg_control, to match previous output.
(We probably should decode all the fields, but hadn't previously due
to the brw_instruction structure definition splitting out bits 4/5
for last_render_target and slot_group_select.)
- Fix 3-source MRF/GRF file decoding on Sandybridge.
- Fix compression code to use qtr_control rather than cmpt_control
(which is compaction, not compression).
Signed-off-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [v2]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 1149eedffc1a996dded9cdc55096d409e48d707b |
|
13-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Pass brw rather than gen to brw_disassemble_inst().
We will need it in order to use the new brw_inst API.
Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 17f2dd72740b2fbf0f24537465b20c10c8d982c4 |
|
15-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Mark three_source_reg_encoding[] static.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| cefa26576110962c4945ae5142a94c5a0d9da793 |
|
01-Jun-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Don't include mtypes.h in brw_disasm.c
It's not used.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4b04152db055babb8b06929a0c9ebea5c7f4fb92 |
|
16-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename brw_disasm/gen8_disassemble to brw/gen8_disassemble_inst.
We're going to use "disassemble" for the function that disassembles
the whole program.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| cce3bea2a71e5c97eb4d2da6ed1cec45d74e2322 |
|
09-May-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Align send instruction meta-information with dst.
Has been misaligned since we added instruction offset prefixes.
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| e00fe451b8bac0aa4f03e07fddee08a870f79bb0 |
|
01-May-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Disassemble the compaction control bit.
brw_disasm doesn't disassemble compacted instructions, so we uncompact
before disassembling them which would unset the compaction control bit.
Instead pass it as a separate argument.
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| f02f48929562aaef853b073dee41d4b21f4718b1 |
|
20-Apr-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Fix s/xoo/xor/ typo.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 06501b3cf07678a8d5e058627fb54cf997092931 |
|
20-Apr-2014 |
Matt Turner <mattst88@gmail.com> |
i965/disasm: Remove tables with obvious mappings.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 7e034a8d778a918854c4b4d5cbe205f1f31e7ece |
|
31-Mar-2014 |
Eric Anholt <eric@anholt.net> |
i965: Fill in a bunch of gen7/hsw data cache-related disasm.
This gets us disasm of atomic ops.
v2: Fix fallthrough on pre-gen7. (bug caught by Ilia Mirkin).
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 01d9023a9b9a50b42f7a4ef4799d0e35e0b045ca |
|
11-Mar-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix register types in dump_instructions(), again.
In commit e57d77280efcbfd6579a88f071426653287ef833, I fixed this for
destinations in the Vec4 backend, and sources in the scalar backend.
But not both types in both backends.
To prevent this mess from continuing, make the reg_encoding table
static, so only the disassembler can use it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| b823d5df0f65fd7b1a821bcb00f1270ada5bf879 |
|
08-Mar-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Disassemble 3 src instructions' rep_ctrl field.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| dafcc1b7c4bd23d9dad805d8ddd27c39c53e6a9f |
|
08-Mar-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Disassemble 3-src operands widths' correctly.
<4,1,1> isn't a real thing. We meant <4,4,1>, i.e., each component of
the whole register.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 54e91e742010728cbf6c5b8c00b6ca5019a63eb9 |
|
10-Dec-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values.
On released hardware, values 4-6 are overloaded. For normal registers,
they mean UB/B/DF. But for immediates, they mean UV/VF/V.
Previously, we just created #defines for each name, reusing the same
value. This meant we could directly splat the brw_reg::type field into
the assembly encoding, which was fairly nice, and worked well.
Unfortunately, Broadwell makes this infeasible: the HF and DF types are
represented as different numeric values depending on whether the
source register is an immediate or not.
To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to
an abstract enum that has a unique value for each register type, and
write translation functions. One nice benefit is that we can add
assertions about register files and generations.
I've chosen not to convert brw_reg::type to the enum, since converting
it caused a lot of trouble due to C++ enum rules (even though it's
defined in an extern "C" block...).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 13454fc3dea4cd4ed1676a1aaf91d49c9a811a7c |
|
10-Dec-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Decode three-source register types directly.
Three-source instructions use a different encoding for register types
(and have a much more limited set to choose from).
Previously, we translated those into BRW_REGISTER_TYPE_* values, then
reused the existing reg_encoding mapping.
Doing it directly is more straightforward and actually less code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4e95a099373c7e3f3f5f0f2854bc4eb582724a0a |
|
10-Dec-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disassemble UV types, not UB types.
UB types have never been supported as immediates. On Gen4-5, register
encoding 4 is "Reserved." On Gen6+, it means UV.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 11d9af7c0ab76c551e676c5ce0f0f369d7fc9f97 |
|
26-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't use GL types in files shared with intel-gpu-tools.
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
-e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
-e 's/GLshort/int16_t/g' \
brw_eu* brw_disasm.c brw_structs.h
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| b9af66528e5b7bd5608086557c44e6b9eb2f2d9d |
|
02-Dec-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Externalize conditional_modifier for use in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 21e92e74c84e0422a5868736f6cb3a408220a294 |
|
02-Dec-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Externalize reg_encoding for use in dump_instruction().
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 82bfb45e24c7a19031a19ad1d361c07dd3da4987 |
|
16-Nov-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Fix disassembled names of BFI1 and BFI2 instructions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 014cce3dc49f5b0bfd7fbb1940ed661c9fc7bbd7 |
|
19-Sep-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Generate code for ir_binop_carry and ir_binop_borrow.
Using the ADDC and SUBB instructions on Gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| fa958182b7e7a9a177ec45ffd39d42f15ca756b3 |
|
10-Apr-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Add support for emitting and disassembling bit instructions.
Specifically
bfe - for bitfieldExtract()
bfi1 and bfi2 - for bitfieldInsert()
bfrev - for bitfieldReverse()
cbit - for bitCount()
fbh - for findMSB()
fbl - for findLSB()
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| c71bee757b52c1e222a4e461f12a93d09998e3da |
|
21-Apr-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Print the correct dst and shared-src types for 3-src instructions.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0c16c12e4613a85792776cee51d2b0ad24ea1510 |
|
23-Apr-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Remove traces of nonexistent TAN math function.
Never existed? At least never supported. Doesn't appear in 965, G45,
or ILK documentation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 015a48743dfcf138cce5752098e01a6cfd6efefe |
|
02-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for emitting the LRP instruction.
Like MAD, this is another three-source instruction.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 7e21910f233a8ff6e2c4adaee6b4edd2f70b6c68 |
|
09-Jan-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Add opcodes for F32TO16 and F16TO32
The GLSL ES 3.00 operations packHalf2x16 and unpackHalf2x16 will emit
these opcodes.
- Define the opcodes BRW_OPCODE_{F32TO16,F16TO32}.
- Add the opcodes to the brw_disasm table.
- Define convenience functions brw_{F32TO16,F16TO32}.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| ca7d332253e237c51fdf5c88a8f7937e65e8abff |
|
23-Jan-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965/disasm: Fix horizontal stride of dest registers
The bug: The printed horizontal stride was the numerical value of the
BRW_HORIZONTAL_$N enum.
The fix: Translate the enum before printing.
Note: This is a candidate for the stable releases.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 200bb36778f841d9d80db0ddd8ce18e5fed3c5a8 |
|
12-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix disassembly of jump targets on Gen7.
Gen7 stores the JIP/UIP bits in different places.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 6a1490bc8ffd6b0259e7d36d04ac207f39a029bb |
|
06-Dec-2012 |
Eric Anholt <eric@anholt.net> |
i965: Print the flag reg updated by conditional modifiers.
This makes our output more consistent with other disasm tools, and
will be necessary when we start using f0.1.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| b7fd4b3f9419353732a061920aefdc7bcec4728d |
|
06-Dec-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add the new flag_reg_nr instruction field from IVB.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| f606a42a3cad9dad27c207864417bcb20efa5c2e |
|
06-Dec-2012 |
Eric Anholt <eric@anholt.net> |
i965: Correct the name and usage of the flag subregister number field.
We've been calling it a register number, it's actually the subregister,
and things will get confusing once we start using it if it isn't fixed.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 914d8f9f84a3539758716d676d59a1fee4cc559f |
|
04-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add a little bit of IR-level debug ability.
This is super basic, but it let me visualize a problem I had with
opt_compute_to_mrf().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| e0cd633f174ad7b106347f0443bbb2f5521b867e |
|
21-Sep-2012 |
Eric Anholt <eric@anholt.net> |
i965: Mark brw_disasm.c tables as static const.
v2: Make the strings in the tables const, too.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| bddb2edab616d30f7894cfff7071a70d273a848e |
|
12-Mar-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for gen6+ UIP/JIP on BREAK/CONT/HALT.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 2b28fd6ca603df40a5d02aac4035eced3a1d079a |
|
22-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the MAD opcode on gen6+.
v2: Fix MRF handling on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| dcdfd1905c8012fe0a90e553f2a894c12cf144cf |
|
18-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix disassembly of data port writes on Ivybridge.
msg_type moved by a bit, so the message type was being disassembled
incorrectly. In particular, render target writes were showing up as
"OWORD block write".
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| a608be5d3333244f5357c459135b17b4c2298e18 |
|
18-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix disassembly of sampler messages on Ivybridge.
Compared to sampler_gen5, simd_mode shifted by a bit and msg_type grew
by a bit. So we were printing slightly incorrect numbers.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 60982976ee14c271353b9545ca5ac085b97ab9b0 |
|
19-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add sensible disasm for the JMPI instruction.
We care about the jump distance, not that the first src is always the
ip register.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 188f0742558196367df24086c4dc9865ebd86f7e |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disassemble Ivybridge Data Port/Data Cache messages.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 53798f90e818e9bf213c3ae4298751362a5ecd50 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Finding this bit in the documentation proved challenging. It wasn't in
the SEND instruction's message descriptor section, nor the data port
message descriptor section. It turns out to be part of the Render
Target Write message's control bits, and in the documentation is named
"Last Render Target Select".
Shaders that use Multiple Render Targets should set this bit on the last
RT write, but not on any prior ones.
The GPU does update the Pixel Scoreboard appropriately, but doesn't
document this bit as directly causing a scoreboard clear.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| feaff3aeebb2eebfa93ad641e0ed286ab0409d21 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove duplicate copies of mlen & rlen from instruction decode.
After printing the details of a specific message, we always print out
the message length and response length with nice "mlen" and "rlen"
labels.
For Gen5+ URB writes, we were dumping mlen and rlen a second time:
urb 0 urb_write interleave used complete mlen 5, rlen 0 mlen 5 rlen 0
Also, for Gen6 data port messages, we were including mlen and rlen in
the tuple of undecipherable integers.
Both of these are completely redundant. So, remove them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 2e124388a4642d1e7f5154e7b83d38578c6b2789 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename BRW_MESSAGE_TARGET_* to BRW_SFID_* and document them.
When reading the data port code, it was not clear to me what these
values meant, nor where I could find them in the documentation.
Especially since the latest BSpec and older PRMs document them in
radically different places...neither of which are near the descriptions
of individual messages.
Cite the documentation, and rename them to SFID to signify that these
are Shared Function IDs that one can read about in the GPU overview,
rather than arbitrary bitfields. While we're add it, make them an enum.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 8de3314f636f57145e008697df34560d3badf41c |
|
03-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix disassembly for intdiv/intmod math functions.
The opcodes and strings were reversed. Quotient means division, and
modulus means remainder.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| e94bdbe04a4f0adb73ab92153987f0c9f48814f7 |
|
08-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add gen6 disassembly for DP render cache messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| c77855d64eae45786d2d637bd065c8a700b788e5 |
|
13-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename dp_render_target struct to gen6_dp.
This is actually just the message descriptor for Gen6+ dataport access;
it has nothing to do with the render cache. Access to the sampler cache
and constant cache also would use this struct; rename for clarity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 5dc53444c8323c1787dddbe6b67048828df9c684 |
|
23-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Correct the dp_read message descriptor setup on g4x.
It's mostly like gen4 message descriptor setup, except that the sizes
of type/control changed to be like gen5. Fixes 21 piglit cases on
gm45, including the regressions in bug #32311 from increased VS
constant buffer usage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| a9f62881a316539658845a98b856f1bf31ca44bc |
|
02-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Dump the WHILE jump distance on gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 9b1d26f78f74ba7f0d5c940f848c21b43ef69398 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for the flag register.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 1732a8bc72fe0a8eaf7449eda65eba1a017ae909 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use SENDC on the first render target write on gen6.
This is apparently required, as the thread will be initiated while it
still has dependencies, and this is what waits for those to be
resolved before writing color.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 5d99b01501128c7179cdd6aa29bc8953d0d81e75 |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add some clarification of the WECtrl field.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| feca6609390d4642418cf7aab878e654964510c4 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up IF/ELSE/ENDIF for gen6.
The jump delta is now in the part of the instruction where the
destination fields used to be, and the src args are ignored (or not,
for the new non-predicated IF that we don't use yet).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 739aec39bd25e79adce306d6cf48296b7c9e4fc0 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.
It instead sensibly appears in the src0 slot.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| bf60f3593452f6ab6340c7a8737cc74f223f2a62 |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: disasm quarter and write enable instruction control on sandybridge
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| af62060ef264998f96eb977d6e0a5de9fe2bd651 |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for gen5 sampler messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 93ba0055c325007656c14ba38302e21be3dc599f |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add AccWrCtl support on Sandybridge.
Whenever the accumulator results are needed, this bit must be set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| ffb5095d56c0f58a35e12d40bb4ffc869e4071bd |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Mention the mlen and rlen for URB reads.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0e2d0cc577270f86691d6bb84a50d11e3a6d0754 |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Adjust disasm of subreg numbers to be in units of the register type.
This makes reading the code easier when matching up to the specs,
which also use this format.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 62383ae6fe5d2ca092e8f9d8dae2ba9562e03d95 |
|
09-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for Compr4 instruction compression.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4ea71cbd0e5f622f760a01120b0ccf4baf4ee7c7 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the disasm output for da16 src widths.
This has confused me twice now. It's a fixed width of 4 (usually a
region description of <4,4,1>), not 1. If it was 1, we'd have been
skipping all over register space.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 0ecf5128a43ed1eff980825e425a030d2b71e50b |
|
21-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for dataport reads (register unspilling).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 8a3f2eb9e6c830ff953751221961f2a6c8f76661 |
|
08-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for SEND mlen/rlen on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| a3cc7585eae1dd7aa1f2257e787c784672f49831 |
|
08-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix disasm of a SEND's mlen and rlen on Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 3f906621da3647d06b7c9903f4b7367efebd82b7 |
|
29-Jun-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add decode for Sandybridge DP write messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 1c25353bc66902ed684b41bb8198b9787c0ce25b |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Parse the ff_sync URB send opcode on Ironlake disasm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 36eda76fea02130d30be6a5f0d83f04698da2853 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Dump out the correct shared function for SEND on Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| d9ea1af82c233a10adbf9b842546e9322480591b |
|
22-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for SNB MATH opcode.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 56ff30a9f97a1a7094432333906544d6138d6bf2 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the PLN instruction when possible in interpolation.
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from
brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have
to be laid out differently.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| c8ef7a09664d29dac682b953eb66efaebbdd6fd7 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Print the offset for IFF in disasm
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 280abdacf900d591ef909cf697f0c5679389c3f6 |
|
09-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Print the offsets for WHILE and BREAK in disasm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 25024d948298a9f3f3210a0b91486f79a3917b0f |
|
31-Dec-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
configs/darwin
src/gallium/auxiliary/util/u_clear.h
src/gallium/state_trackers/xorg/xorg_exa_tgsi.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 070bbd4fcd5d2b669b880b91730a7ad9d130e416 |
|
23-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix setup of immediate types for gen4 disasm.
Caught by clang.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| f5ad1d0d02cae06bff3ee120c75ad4ab458d2c7d |
|
25-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
i965: Add missing va_end.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 8288ab4518241746be9989e008b48345c7394d10 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Print out ELSE and ENDIF src1 arguments like IF does.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 1d4bace9fca64c61ccd9f4205262417fa0ae3883 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out,
and running intel-gen4disasm on it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| ce63e9929cf3515e4ad4ea54fa5227d71ae48b93 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Initial import of disasm code from intel-gen4asm.
There's a bunch of stuff from gen4asm and gpu-tools that we probably want
to make into a library instead of cargo-culting it around.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|