| ce44501ea87ff66267c9cf280e4596065ffebd46 |
|
12-Jan-2017 |
Juan A. Suarez Romero <jasuarez@igalia.com> |
nir/i965: assert first is always less than 64
This fixes a defect detected by Coverity Scan.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6bb4255f8ebb8cc048afe498e11738985d134f8a |
|
14-Dec-2016 |
Juan A. Suarez Romero <jasuarez@igalia.com> |
i965: check for dual slot attributes on any gen
Those not supporting 64 bit input vertex attributes will have the
dual_slot value as false.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 329cbe363dcc465764719d91f8f31c8606769ba4 |
|
11-Apr-2016 |
Alejandro Piñeiro <apinheiro@igalia.com> |
i965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8
gen < 8 doesn't support *64*PASSTHRU formats when emitting
vertices. So in order to provide the equivalent functionality, we need
to downsize the format to equivalent *32*FLOAT, and in some cases
(R64G64B64 and R64G64B64A64) submit two 3DSTATE_VERTEX_ELEMENTS for
each vertex element.
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 717f99b34a329d21d7b65e3193c6bf2162ad7964 |
|
15-Apr-2016 |
Alejandro Piñeiro <apinheiro@igalia.com> |
i965: return PASSTHRU surface types also on gen7
Although gen7 doesn't include surface types as a valid conversion format,
we return it, as it reflects what we want to achieve, even if we need
to workaround it on gen < 8.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c2acf97fcc9b32eaa9778771282758e5652a8ad4 |
|
16-Dec-2016 |
Juan A. Suarez Romero <jasuarez@igalia.com> |
nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes
So far, input_reads was a bitmap tracking which vertex input locations
were being used.
In OpenGL, an attribute bigger than a vec4 (like a dvec3 or dvec4)
consumes just one location, any other small attribute. So we mark the
proper bit in inputs_read, and also the same bit in double_inputs_read
if the attribute is a dvec3/dvec4.
But in Vulkan, this is slightly different: a dvec3/dvec4 attribute
consumes two locations, not just one. And hence two bits would be marked
in inputs_read for the same vertex input attribute.
To avoid handling two different situations in NIR, we just choose the
latest one: in OpenGL, when creating NIR from GLSL/IR, any dvec3/dvec4
vertex input attribute is marked with two bits in the inputs_read bitmap
(and also in the double_inputs_read), and following attributes are
adjusted accordingly.
As example, if in our GLSL/IR shader we have three attributes:
layout(location = 0) vec3 attr0;
layout(location = 1) dvec4 attr1;
layout(location = 2) dvec3 attr2;
then in our NIR shader we put attr0 in location 0, attr1 in locations 1
and 2, and attr2 in location 3 and 4.
Checking carefully, basically we are using slots rather than locations
in NIR.
When emitting the vertices, we do a inverse map to know the
corresponding location for each slot.
v2 (Jason):
- use two slots from inputs_read for dvec3/dvec4 NIR from GLSL/IR.
v3 (Jason):
- Fix commit log error.
- Use ladder ifs and fix braces.
- elements_double is divisible by 2, don't need DIV_ROUND_UP().
- Use if ladder instead of a switch.
- Add comment about hardware restriction in 64bit vertex attributes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c32a9ec5f5bd74ae03b84be4c51d8d174ddf3e17 |
|
03-Nov-2016 |
Juan A. Suarez Romero <jasuarez@igalia.com> |
i965: allow unsourced enabled VAO
The GL 4.5 spec says:
"If any enabled array’s buffer binding is zero when DrawArrays
or one of the other drawing commands defined in section 10.4 is
called, the result is undefined."
This commits avoids crashing the code, which is not a very good
"undefined result".
This fixes spec/!opengl 3.1/vao-broken-attrib piglit test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1d6fe13c138efb836a28052b16260a258d113827 |
|
10-Oct-2016 |
Kevin Strasser <kevin.strasser@intel.com> |
mesa/extensions: expose OES_vertex_half_float for ES2
Half float support already exists for desktop GL. Reuse the
ARB_half_float_vertex enable bit and account for the different enum to
enable the extension for ES2.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 61a8a55f557784c8ec17fb1758775c6f18252201 |
|
21-Oct-2016 |
Antia Puentes <apuentes@igalia.com> |
i965/gen8: Fix vertex attrib upload for dvec3/4 shader inputs
The emission of vertex attributes corresponding to dvec3 and dvec4
vertex shader input variables was not correct when the <size> passed
to the VertexAttribL* commands was <= 2.
This was because we were using the vertex array size when emitting vertices
to decide if we uploaded a 64-bit floating point attribute as 1 slot (128-bits)
for sizes 1 and 2, or 2 slots (256-bits) for sizes 3 and 4. This caused problems
when mapping the input variables to registers because, for deciding which
registers contain the values uploaded for a certain variable, we use the size
and type given to the variable in the shader, so we will be assigning 256-bits
to dvec3/4 variables, even if we only uploaded 128-bits for them, which happened
when the vertex array size was <= 2.
The patch uses the shader information to only emit as 128-bits those 64-bit floating
point variables that were declared as double or dvec2 in the vertex shader. Dvec3 and
dvec4 variables will be always uploaded as 256-bits, independently of the <size> given
to the VertexAttribL* command.
From the ARB_vertex_attrib_64bit specification:
"For the 64-bit double precision types listed in Table X.1, no default
attribute values are provided if the values of the vertex attribute variable
are specified with fewer components than required for the attribute
variable. For example, the fourth component of a variable of type dvec4
will be undefined if specified using VertexAttribL3dv or using a vertex
array specified with VertexAttribLPointer and a size of three."
We are filling these unspecified components with zeros, which coincidentally is
also what the GL44-CTS.vertex_attrib_binding.basic-inputL-case1 expects.
v2: Do not use bitcount (Kenneth Graunke)
Fixes: GL44-CTS.vertex_attrib_binding.basic-inputL-case1 test
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97287
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c538846e313c43858fb118db012b592513c0ed29 |
|
26-Oct-2016 |
Brian Paul <brianp@vmware.com> |
mesa: rename gl_client_array -> gl_vertex_array
The term "client array" is a legacy thing dating back to the pre-VBO
era when _all_ vertex arrays lived in client memory.
Nowadays, it only contains vertex array state which is derived from
gl_array_attributes and gl_vertex_buffer_binding. It's used by the
VBO module and some drivers.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 40258a13d5bf81303585eaf1859fcb85e373be3e |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->vs.prog_data pointer.
Just say no to:
- brw->vs.base.prog_data = &brw->vs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_vs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 073129c7afb955ff33a94ccb358883a7051c624a |
|
15-Aug-2016 |
Eric Anholt <eric@anholt.net> |
i965: Drop assertion about buffer offset at draw time.
Given robust access, we should just be returning zeroes if the user gives
us a base pointer that's too big, which is what was happens on a release
build. This was caught by a webgl conformance test for out-of-bounds
draws on servo.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 575c8cbb540323a8a3065b8b16db378ff763b2e6 |
|
15-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Unify vertex buffer setup
On gen >= 8 one doesn't provide ending address but number of bytes
available. This is relative to the given offset.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bdab945edde9d54dbd57659bae5fa5519a4be21f |
|
15-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/draw: Expose vertex buffer state setup
Also change the interface to use start and end offsets.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e7776fa9473af0fd1424f860323916077b991bf6 |
|
25-May-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use the buffer object size for VERTEX_BUFFER_STATE's size field.
commit 7c8dfa78b98a12c1c5 (i965/draw: Use the real size for vertex
buffers) changed how we programmed the VERTEX_BUFFER_STATE size field.
Previously, we programmed it to the size of the actual underlying BO,
which is page-aligned, and potentially much larger than the GL buffer
object. This violated the ARB_robust_buffer_access spec.
With that change, we started programming it based on the range of data
we expect the draw call to actually access - which is based on the
min_index and max_index information provided to glDrawRangeElements().
Unfortunately, applications often provide inaccurate range information
to glDrawRangeElements(). For example, all the Unreal demos appear to
draw using a range of [0, 3] when the index buffer's actual index range
is [0, 5]. Such results are undefined, and we are absolutely allowed
to restrict access to the range they specified. However, the failure
mode is usually that nothing draws, or misrendering with wild geometry,
which is kind of bad for a common mistake. And people tend to assume
the range information isn't that important when data is in VBOs.
There's no real advantage, either. ARB_robust_buffer_access only
requires us to restrict access to the GL buffer object size, not
the range of data we think they should access. Doing that allows
buggy applications to still function. (Note that we still use this
information for busy-tracking, so if they try to overwrite the data
with glBufferSubData, they'll still hit a bug.) This seems to be
safer.
We may want to provide the more strict range as a debug option,
or scan the VBO and warn against bogus glDrawRangeElements in
debug contexts. That can be done as a later patch, though.
Makes Unreal demos draw again.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6f89e51c8477f21b64d1f4420b06e407de9022ff |
|
25-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Use the correct buffer index for interleaved VBO sizes
The buffer_range_* arrays are indexed by buffer index not element index.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| aec10a1d5b4a0802f6f09d1b83c79f53ecd3d29f |
|
18-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Use the real size for index buffers
Previously, we were using the size of the whole BO which may be
substantially larger than the actual index buffer size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7c8dfa78b98a12c1c5f74d11433c8554d4c90657 |
|
18-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Use the real size for vertex buffers
Previously, we were using the size of the BO which may be substantially
larger than the actual vertex buffer size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a643bc62463efbd88e34a85cda50a19d8ace6292 |
|
19-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Use 3-channel formats for vertex fetch when possible.
For a long time, several of the 3-channel vertex formats didn't exist so we
faked them with 4-channel versions. Starting with Sandy Bridge, we can use
R16G16B16_FLOAT and 8 and 16-bit integer formats become available on
Haswell and Bay Trail.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d5b4ab2c5f700087ac09238e3cf8252aa3d31d54 |
|
18-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Properly handle rounding when dividing by InstanceDivisor
The old code always divided rounded down and then subtracted 1. What we
wanted was to divide rounded up and then subtract 1 which is equivalent to
subtracting 1 and then dividing rounded down.
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ad42ab473cb327e9f0498bda9d92cccc4279a0e8 |
|
18-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Account for BaseInstance in VBO bounds
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ad3deec8ca9813a746ac833e6a0cc2ed13286c35 |
|
18-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Use worst-case VBO bounds if brw->num_instances == 0
Previously, we only handled the "I don't know what's going on" case for
things with InstanceDivisor == 0. However, in the DrawIndirect case we can
get num_instances == 0 and we don't know what's going on with the instanced
ones either. This commit makes the worst-case bound the default and then
conservatively tightens the bound.
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8892519751f5a38e12dd64e3fef3976c53eb9e86 |
|
18-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Delay when we get the bo for vertex buffers
The previous code got the BO the first time we encountered it. However,
this can potentially lead to problems if the BO is used for multiple arrays
with the same buffer object because the range we declare as busy may not be
quite right. By delaying the call to intel_bufferobj_buffer, we can ensure
that we have the full range for the given buffer.
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a01a1eb9e48196a5dde37675c51d294b31c32728 |
|
18-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/draw: Stop relying on min_index == -1 for invalid index bounds
The vbo layer passes an index_bounds_valid flag that we should be using
instead. This also fixes a bug when min_index == -1 and basevertex != 0
where we were actually comparing min_index + basevertex == -1 which was
false and we were getting the wrong buffer-sizing path.
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 71150b73c81a58dc06057ced561d10332aecc803 |
|
15-Mar-2016 |
Alejandro Piñeiro <apinheiro@igalia.com> |
i965: get the proper vertex surface type for doubles on gen8+
This commit adds support for PASSTHRU format when pushing
double-precision attributes.
Check glarray->Doubles in order to know if we should choose a format
that does a conversion to float, or just passthru the 64-bit double.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6d5ce1b0433f4cbc5cd88b4bfeaf4cdcba6beda8 |
|
22-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make all atoms to track BRW_NEW_BLORP by default
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| cddfc2cefa93b884c40329dcb193fe4fb22143ab |
|
10-Dec-2015 |
Kristian Høgsberg Kristensen <krh@bitplanet.net> |
i965: Add support for gl_DrawIDARB and enable extension
We have to break open a new vec4 for gl_DrawIDARB. We've used up all
space in the vec4 we use for SGVS and gl_DrawIDARB has to come from its
own separate vertex buffer anyway. This is because we point the vb for
base vertex and base instance into the draw parameter BO for indirect
draw calls, but the draw id is generated by mesa in a different buffer.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 17ebb55a14b5a9aa639845fbda9330ef9421834a |
|
10-Dec-2015 |
Kristian Høgsberg Kristensen <krh@bitplanet.net> |
i965: Add support for gl_BaseVertexARB and gl_BaseInstanceARB
We already have gl_BaseVertexARB in the .x component of the SGVS vec4
and plug gl_BaseInstanceARB into the last free component (.y).
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 76732932ec3918bb9cc04ccd37bc1a8c37051683 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Drop #include of main/glheader.h.
It's never used.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 284dcad20a9a55278c1d3dd98f53e45650b22896 |
|
20-Aug-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Fix typos in license
grep -lr 'sub license' | while read f; do \
sed --in-place -e 's/sub license/sublicense/' $f ;\
done
grep -lr 'NON-INFRINGEMENT' | while read f; do \
sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\
done
As noted by Matt, both of these changes match the MIT license text found
at http://opensource.org/licenses/MIT.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| aa1a5c0c9e0de71ecd15e7190c121d6dd98471a6 |
|
20-Aug-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Remove horizontal bars from file header comments
Why was that ever a thing?
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| fb02b4ec482762ccf2a9fedf24fe6f50787932a9 |
|
13-Jul-2015 |
Neil Roberts <neil@linux.intel.com> |
i965: Swap the order of the vertex ID and edge flag attributes
The edge flag data on Gen6+ is passed through the fixed function hardware as
an extra attribute. According to the PRM it must be the last valid
VERTEX_ELEMENT structure. However if the vertex ID is also used then another
extra element is added to source the VID. This made it so the vertex ID is in
the wrong register in the vertex shader and the edge attribute is no longer in
the last element.
v2: Also implement for BDW+
v3 [by Ben]: Remove 10.5 tag. Too late.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84677
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Mark Janes <mark.a.janes@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5be455281eca77955aff52f01c6adb9281f4d747 |
|
06-Aug-2015 |
Rhys Kidd <rhyskidd@gmail.com> |
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c: In function 'brw_prepare_vertices':
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:434:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = j = 0; i < brw->vb.nr_enabled; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:557:17: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < nr_uploads; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:569:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < nr_uploads; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 680d09b072af7ea1541cfd4fbc62c83e8bd02d0d |
|
25-Jun-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Trivial formatting changes in brw_draw_upload.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2f11e92cef51c88a09bc778e2ceca4ab50cf0017 |
|
18-Jul-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().
Generated by sed; no manual changes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f11c6f09cf36909ff399353b20195a31cf0f1907 |
|
09-Jul-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Optimize batchbuffer macros.
Previously OUT_BATCH was just a macro around an inline function which
does
brw->batch.map[brw->batch.used++] = dword;
When making consecutive calls to intel_batchbuffer_emit_dword() the
compiler isn't able to recognize that we're writing consecutive memory
locations or that it doesn't need to write batch.used back to memory
each time.
We can avoid both of these problems by making a local pointer to the
next location in the batch in BEGIN_BATCH().
Cuts 18k from the .text size.
text data bss dec hex filename
4946956 195152 26192 5168300 4edcac i965_dri.so before
4928956 195152 26192 5150300 4e965c i965_dri.so after
This series (including commit c0433948) improves performance of Synmark
OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 759ed0bd03818c912e7f1fa62bafc50ef52ef291 |
|
14-Jul-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Mark constant static data as const.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 28d9e90428282a5e0a6aa31ad858a5cf514d1264 |
|
07-Apr-2015 |
Marius Predut <marius.predut@intel.com> |
i965: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 4e56a9ad46ff7fe85308ce12e21719ff2b476516 |
|
20-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Don't use brw->state.dirty.brw
Now, we only use ctx->NewDriverState.
I used this bash & sed command in the i965 directory:
for file in *.[ch] *.[ch]pp; do
sed -i -e 's/state\.dirty\.brw/ctx.NewDriverState/g' $file
done
Followed by manual changes to brw_state_upload.c.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6ed53c27efc1b3eeb987b84b997633bc9456e5aa |
|
10-Nov-2014 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Micro-optimize brw_get_index_type
With the switch-statement, GCC 4.8.3 produces a small pile of code with
a branch.
00000000 <brw_get_index_type>:
000000: 8b 54 24 04 mov 0x4(%esp),%edx
000004: b8 01 00 00 00 mov $0x1,%eax
000009: 81 fa 03 14 00 00 cmp $0x1403,%edx
00000f: 74 0d je 00001e <brw_get_index_type+0x1e>
000011: 31 c0 xor %eax,%eax
000013: 81 fa 05 14 00 00 cmp $0x1405,%edx
000019: 0f 94 c0 sete %al
00001c: 01 c0 add %eax,%eax
00001e: c3 ret
However, this could be two instructions.
00000000 <brw_get_index_type>:
000000: 2d 01 14 00 00 sub $0x1401,%eax
000005: d1 e8 shr %eax
000007: 90 nop
000008: 90 nop
000009: 90 nop
00000a: 90 nop
00000b: c3 ret
The function was also moved to the header so that it could be inlined at
the two call sites. Without this, 32-bit also needs to pull the
parameter from the stack. This means there is a push, a call, a move,
and a ret added to a two instruction function. The above code shows the
function with __attribute__((regparm=1)), but even this adds several
extra instructions. There is also an extra instruction on 64-bit to
move the parameter to %eax for the subtract.
On Bay Trail-D using Fedora 20 compile flags (-m64 -O2 -mtune=generic
for 64-bit and -m32 -march=i686 -mtune=atom for 32-bit), affects
Gl32Batch7:
32-bit: Difference at 95.0% confidence 0.818589% +/- 0.234661% (n=40)
64-bit: Difference at 95.0% confidence 0.54554% +/- 0.354092% (n=40)
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c633528cbac007a73a066f269b3c9a25daf1e21a |
|
18-Dec-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix start/base_vertex_location for >1 prims but !BRW_NEW_VERTICES.
This is a partial revert of c89306983c07e5a88c0d636267e5ccf263cb4213.
It split the {start,base}_vertex_location handling into several steps:
1. Set brw->draw.start_vertex_location = prim[i].start
and brw->draw.base_vertex_location = prim[i].basevertex.
(This happened once per _mesa_prim, in the main drawing loop.)
2. Add brw->vb.start_vertex_bias and brw->ib.start_vertex_offset
appropriately. (This happened in brw_prepare_shader_draw_parameters,
which was called just after brw_prepare_vertices, as part of state
upload, and only happened when BRW_NEW_VERTICES was flagged.)
3. Use those values when emitting 3DPRIMITIVE (once per _mesa_prim).
If we drew multiple _mesa_prims, but didn't flag BRW_NEW_VERTICES on
the second (or later) primitives, we would do step #1, but not #2.
The first _mesa_prim would get correct values, but subsequent ones
would only get the first half of the summation.
The reason I originally did this was because I needed the value of
gl_BaseVertexARB to exist in a buffer object prior to uploading
3DSTATE_VERTEX_BUFFERS. I believed I wanted to upload the value
of 3DPRIMITIVE's "Base Vertex Location" field, which was computed
as: (prims[i].indexed ? prims[i].start : prims[i].basevertex) +
brw->vb.start_vertex_bias. The latter value wasn't available until
after brw_prepare_vertices, and the former weren't available in the
state upload code at all. Hence the awkward split.
However, I believe that including brw->vb.start_vertex_bias was a
mistake. It's an extra bias we apply when uploading vertex data into
VBOs, to move [min_index, max_index] to [0, max_index - min_index].
>From the GL_ARB_shader_draw_parameters specification:
"<gl_BaseVertexARB> holds the integer value passed to the <baseVertex>
parameter to the command that resulted in the current shader
invocation. In the case where the command has no <baseVertex>
parameter, the value of <gl_BaseVertexARB> is zero."
I conclude that gl_BaseVertexARB should only include the baseVertex
parameter from glDraw*Elements*, not any internal biases we add for
optimization purposes.
With that in mind, gl_BaseVertexARB only needs prim[i].start or
prim[i].basevertex. We can simply store that, and go back to computing
start_vertex_location and base_vertex_location in brw_emit_prim(), like
we used to. This is much simpler, and should actually fix two bugs.
Fixes missing geometry in Unvanquished.
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85529
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5f34a18f96e58aff1aca2d2971fca1c91dc6931d |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete brw_state_flags::cache and related code.
It's been merged into brw_state_flags::brw for simplicity and
efficiency.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 4f24c168c87e9938f35f5ec135062408148be373 |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).
I put the BRW_NEW_*_PROG_DATA flags at the beginning so that
brw_state_cache.c can still continue using 1 << brw_cache_id.
I also added a comment explaining the difference between
BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM, as it took me a long time
to remember it.
Non-mechanical changes:
- brw_state_cache.c and brw_ff_gs.c now signal .brw, not .cache.
- brw_state_upload.c - INTEL_DEBUG=state changes.
- brw_context.h - bit definition merging.
v2: Correct the explanation of BRW_NEW_*_PROG_DATA to mention
state-based recompiles, and nix the "proper subset" claim,
as it's false. (Caught by Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ce44b2061cf59264b4f22271e8d70cdc826af6de |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.
Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache. Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.
State upload is one of the hottest paths in the driver. For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache). Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom. Broadwell, for example, has
57 state atoms, so this small savings can add up.
CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset). Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.
Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones. This one simply renames things, and was made via:
$ for file in *.[ch]; do
sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
-e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
done
Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw. It will also fix the
alphabetization issues.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bea9b8e306e8424ffacbdfc99ca2fc91f1c9912b |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Alphabetize brw_tracked_state flags and use a consistent style.
Most of the dirty flags were listed in some arbitrary order. Some used
bonus parenthesis. Some put multiple flags on one line, others put one
per line. Some used tabs instead of spaces...but only on some lines.
This patch settles on one flag per line, in alphabetical order, using
spaces instead of tabs, and sheds the unnecessary parentheses.
Sorting was mostly done with vim's visual block feature and !sort,
although I alphabetized short lists by hand; it was pretty manual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 26ee6f23a9aec6b1f392baa0e3f1f2c62c038a57 |
|
15-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Delete VAO _MaxElement code and index buffer bounds checking.
Fredrik's implementation of ARB_vertex_attrib_binding introduced new
gl_vertex_attrib_array and gl_vertex_buffer_binding structures, and
converted Mesa's older gl_client_array to be derived state. Ultimately,
we'd like to drop gl_client_array and use those structures directly.
One hitch is that gl_client_array::_MaxElement doesn't correspond to
either structure (unlike every other field), so we'd have to figure out
where to store it. The _MaxElement computation uses values from both
structures, so it doesn't really belong in either place. We could put
it in the VAO, but we'd have to pass it around everywhere.
It turns out that it's only used when ctx->Const.CheckArrayBounds is
set, which is only set by the (rarely used) classic swrast driver.
It appears that drivers/x11 used to set it as well, which was intended
to avoid segmentation faults on out-of-bounds memory access in the X
server (probably for indirect GLX clients). However, ajax deleted that
code in 2010 (commit 1ccef926be46dce3b6b5c76e812e2fae4e205ce7).
The bounds checking apparently doesn't actually work, either. Non-VBO
attributes arbitrarily set _MaxElement to 2 * 1000 * 1000 * 1000.
vbo_save_draw and vbo_exec_draw remark /* ??? */ when setting it, and
the i965 code contains a comment noting that _MaxElement is often bogus.
Given that the code is complex, rarely used, and dubiously functional,
it doesn't seem worth maintaining going forward. This patch drops it.
This will probably mean the classic swrast driver may begin crashing on
out of bounds vertex buffer access in some cases, but I believe that is
allowed by OpenGL (and probably happened for non-VBO accesses anyway).
There do not appear to be any Piglit regressions, either.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Roland Scheidegger <sroland@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6b6145204dd4a1112f6e1fe10162636141495b79 |
|
11-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Separate gl_InstanceID and gl_VertexID uploading.
We always uploaded them together, mostly out of laziness - both required
an additional vertex element. However, gl_VertexID now also requires an
additional vertex buffer for storing gl_BaseVertex; for non-indirect
draws this also means uploading (a small amount of) data. This is extra
overhead we don't need if the shader only uses gl_InstanceID.
In particular, our clear shaders currently use gl_InstanceID for doing
layered clears, but don't need gl_VertexID.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| fbb353bc13a8924f9c6cd8c2572d299e3c4b9162 |
|
08-Aug-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Expose gl_BaseVertex via a vertex attribute.
Now that we have the data available, we need to expose it to the
shaders. We can reuse the same vertex element that we use for
gl_VertexID, but we need to back it by an actual vertex buffer.
A hardware restriction requires that vertex attributes coming from a
buffer (STORE_SRC) must come before any other types (i.e. STORE_0).
So, we have to make gl_BaseVertex be the .x component of the vertex
attribute. This means moving gl_VertexID to a different component.
I chose to move gl_VertexID and gl_InstanceID to the .z and .w
components, respectively, to make room for gl_BaseInstance in the .y
component (which would also come from a buffer, and therefore be
STORE_SRC).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 87b10c4a7161905e3a9dc2b2ddc77fbf6908ebd5 |
|
08-Aug-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Refactor Gen4-7 VERTEX_BUFFER_STATE emission into a helper.
We'll need to emit another VERTEX_BUFFER_STATE for gl_BaseVertex;
pulling this into a helper function will save us from having to deal
with cross-generation differences in that code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| fdbabf22e183d478cd076215052fa877b125629b |
|
08-Aug-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make gl_BaseVertex available in a buffer object.
This will be used for GL_ARB_shader_draw_parameters, as well as fixing
gl_VertexID, which is supposed to include gl_BaseVertex's value.
For indirect draws, we simply point at the indirect buffer; for normal
draws, we upload the value via the upload buffer.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c89306983c07e5a88c0d636267e5ccf263cb4213 |
|
08-Aug-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Calculate start/base_vertex_location after preparing vertices.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 864c463485aafaa2802b18a7427f8b75dc96e3ef |
|
03-Sep-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404
Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
c5bdf9be1eca190417998d548fd140c1eca37a54
Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
6f56e1424d923fd80c84090fbf4506c9eaaffea1
Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
88e3d404dad009d8cff5124cf8acee7daeaceb64
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 88e3d404dad009d8cff5124cf8acee7daeaceb64 |
|
10-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Create a macro for setting a dirty bit.
This will make it easier to extend dirty bit handling to support
compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3d826729dabab53896cdbb1f453c76fab1c7e696 |
|
29-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use unreachable() instead of unconditional assert().
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 99442bc7b20e4d76a5bdff72821e86a7ff5942ab |
|
06-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Stop setting up a 1:1 "attrib" member in our vertex inputs.
It's just the array index, so we can just go look at the array and see
which element we are.
No significant performance difference (n=140)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9a5d19d680323dfb9705c6c5ac10ac30d9ccc842 |
|
06-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Skip a bunch of IB BO refcount twiddling.
Improves cairo performance on glamor by 1.64828% +/- 1.04742% (n=65).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3b579882903c577daa1af286a5e0bf5bc122a34d |
|
24-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Massively simplify the intel_upload implementation.
The implementation kept a page-sized area for uploading data, and
uploaded chunks from that to a 64kb-sized streamed buffer. This wasted
cache footprint (and extra state tracking to do so) when we want to just
write our data into the buffer immediately.
Instead, build it around an interface like brw_state_batch() that just
gets you a pointer to BO memory to upload your stuff immediately.
Improves OpenArena on HSW by 1.62209% +/- 0.355299% (n=61) and on BYT by
1.7916% +/- 0.415743% (n=31).
v2: Rebase on Mesa master, drop old prototypes. Re-do performance
comparison on a kernel that doesn't punish CPU efficiency
improvements.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 512c88f826f597daeb8bac82eea793b4c2f90dfe |
|
05-Mar-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop special case for edgeflag thanks to Marek's change to core.
As of 780ce576bb1781f027797039693b98253ee4813e, we end up with R8_SSCALED
anyway.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b8b4e280b47888898143b09404e71a51663ac59c |
|
03-Mar-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix indentation in brw_upload_indices().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 051edcc144aca314d207200c46bc88b4efa1e56c |
|
03-Mar-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Consolidate code for setting brw->ib.start_vertex_offset.
This was set identically in three places.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dca350201e00c7cf1cfb009158f4abf27fbc96d2 |
|
06-Feb-2014 |
Marek Olšák <marek.olsak@amd.com> |
mesa: allow buffers to be mapped multiple times
OpenGL allows a buffer to be mapped only once, but we also map buffers
internally, e.g. in the software primitive restart fallback, for PBOs,
vbo_get_minmax_index, etc. This has always been a problem, but it will
be a bigger problem with persistent buffer mappings, which will prevent
all Mesa functions from mapping buffers for internal purposes.
This adds a driver interface to core Mesa which supports multiple buffer
mappings and allows 2 mappings: one for the GL user and one for Mesa.
Note that Gallium supports an unlimited number of buffer and texture
mappings, so it's not really an issue for Gallium.
v2: fix unmapping in xm_dd.c, remove the GL errors there
v3: fix the intel driver (by Fredrik)
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 83daa88035af978c5158cfe5a196df45ce1555c1 |
|
23-Dec-2013 |
Eric Anholt <eric@anholt.net> |
i965: Move the remaining driver debug over to stderr.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5c0d7dbcb9575bd8126d4d4ef83753664b848d27 |
|
04-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework vertex uploads for Broadwell.
v2: Emit a dummy 3DSTATE_VF_SGVS packet when not needed.
v3: Add WARN_ONCE and perf_debugs requested by Eric Anholt.
v4: Program 3DSTATE_SGVS even in the no-elements case so gl_VertexID
continues working. Fix 3DSTATE_VF_INSTANCING to not use an
element index to access the buffers array. Some ARB_draw_indirect
prep work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1c5e2965a0de296240dd8f5af12482164416b7f1 |
|
26-Aug-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove CACHED_BATCH support altogether.
Using an unoptimized variant of glamor spending 50% of its CPU time in
brw_draw_prims() (and hitting the cache *very* frequently):
N Min Max Median Avg Stddev
x 200 29200 40500 34900 34750 958.43256
+ 200 31000 40300 34700 34622 916.35941
No difference proven at 95.0% confidence
Similarly, no difference on GLB2.7:
N Min Max Median Avg Stddev
x 63 64.1 71.36 70.69 70.113175 1.6782026
+ 63 63.6 71.18 70.75 70.223651 1.6044186
No difference proven at 95.0% confidence
v2: Rebase on master (by anholt)
v3: Add a missing BEGIN_BATCH(3) to aa_line_parameters -- CACHED_BATCH
didn't have the asserts about batchbuffer usage that ADVANCE_BATCH
does, so we started assertion failing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 877128505431adaf817dc8069172ebe4a1cdf5d8 |
|
17-Jan-2014 |
José Fonseca <jfonseca@vmware.com> |
s/Tungsten Graphics/VMware/
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a7bdd4cba8ddcab8dff59ecaaa7efbd436c6c307 |
|
26-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop trailing whitespace from the rest of the driver.
Performed via:
$ for file in *; do sed -i 's/ *//g'; done
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e03994bf47f9741a7a3a6181eb4f4d0cf286f70f |
|
27-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
Revert "i965: Move brw_emit_query_begin() to the render ring prelude."
This reverts commit a4bf7f6b6e612626c4e4fc21507ac213a7ba4b00.
It breaks occlusion queries on Gen4-5. Doing this right will likely
require larger changes, which should be done at a future date.
Some Piglit tests still passed due to other bugs; fixing those revealed
this problem.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a4bf7f6b6e612626c4e4fc21507ac213a7ba4b00 |
|
16-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move brw_emit_query_begin() to the render ring prelude.
Without hardware contexts, the pipeline statistics registers are
free-running and include data from every 3D application running.
In order to find out the contributions of one particular context, we
need to take a snapshot at the start and end of each batch.
Previously, we emitted the PIPE_CONTROL necessary to capture
PS_DEPTH_COUNT when drawing primitives. Special tracking ensured it
happened only on the first draw of the batch, rather than on every draw.
Moving this to brw_new_batch increases symmetry, since the final
snapshot has always been in brw_finish_batch, which is just a few lines
below. It should be basically equivalent.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8bd45a7e7ed8be3f5bb13689d249fc886cf73067 |
|
31-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add a warning if something ever hits a bug I noticed.
We'd have to map the VBO and rewrite things to a lower stride to fix it.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7a95bb0a80075c7708f03cc0115177d8ed3070cb |
|
07-Nov-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: add support for UNSIGNED_INT_10F_11F_11F_REV vertex attribs
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c298f5ff5681dd7c3cf0bf7c37a6f22430deeb91 |
|
04-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Try to avoid stalls on the GPU when doing glBufferSubData().
On DOTA2, framerate on dota2-de1.dem in windowed mode on my laptop
improves by 7.69854% +/- 0.909163% (n=3). In a microbenchmark hitting
this code path (wall time of piglit vbo-subdata-many), runtime decreases
from 0.8 to 0.05 seconds.
v2: Use out of range start/end instead of separate bool for the active
flag (suggestion by Jordan), fix double-upload in the stalling path.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 060a49a8966d923ad9c02d6f200baacb7ff081d4 |
|
04-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Drop intel_bufferobj_source().
Since src_offset was always 0, it wasn't doing anything for us beyond
intel_bufferobj_buffer().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e6893b99adcd6d9fb1bd49067883f66cc5603fe7 |
|
12-Aug-2013 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.
I didn't have a BYT at hand for testing.
v2: Don't check (brw->gen == 7) in gen7 functions. (chadv)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f4e5c235de7baf333150ba3202eb7b2ec4c432fa |
|
04-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Mark a few brw_draw_upload.c functions as non-static
We will reuse these for Broadwell.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a16d47465ecdbaef0548207c1bc037493a67ebec |
|
18-Jul-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965/hsw: Change L3 MOCS of 3DSTATE_VERTEX_BUFFERS
Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 794de2f3873bcedc78300b3ba69656adc755894c |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::is_<platform> flags to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b15f1fc3c6b3b9dc4422940c412f80e581c9900d |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::perf_debug to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 329cd6a9b145d5b3b5a2acca1b6c2019d01c9355 |
|
20-Jun-2013 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Be more careful with the interleaved user array upload optimization
The checks to determine when the data can be uploaded in an interleaved
fashion can be tricked by certain data layouts. For example,
float data[...];
glVertexAttribPointer(0, 4, GL_FLOAT, GL_FALSE, 16, &data[0]);
glVertexAttribPointer(1, 4, GL_FLOAT, GL_FALSE, 16, &data[4]);
glDrawArrays(GL_POINTS, 0, 1);
will hit the interleaved path with an incorrect size (16 bytes instead
of 32 bytes). As a result, the data for attribute 1 never gets
uploaded. The single element draw case is the only sensible case I can
think of for non-interleaved-that-looks-like-interleaved data, but there
may be others as well.
To fix this, make sure that the end of the element in the array being
checked is within the stride "window." Previously the code would check
that the begining of the element was within the window.
NOTE: This is a candidate for stable branches.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7a9f4d3e7114ca709658a620644ad897bdda41e7 |
|
29-May-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Fix glColorPointer(GL_FIXED)
When a gl_client_array is created with glColorPointer,
gl_client_array::Normalized is true. This caused the translation from the
gl_client_array's type to a BRW_SURFACEFORMAT to assertion fail.
Fixes the spinning cube's color in Android 4.2's ApiDemos.apk,
"Graphics > OpenGL ES".
Fixes assertion failure in mesa-demos/src/egl/opengles1/tri_x11 on Haswell
and Ivybridge:
brw_draw_upload.c:287: get_surface_type: Assertion `0' failed.
No Piglit regressions on Haswell.
Note: This is a candidate for the 9.1 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42182
Issue: AXIA-2954
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 394edb5af5161f664c0c3b4eaba9be4e30f3c138 |
|
06-Apr-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Require kernel 2.6.39 for relaxed relocation support.
Chris Wilson's relaxed relocation patch landed in March 2011. Anyone
running pre-3.0 kernels probably isn't going to get the latest Mesa
anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 11766b1bbb730d2f22a23d8293c67b138b364fce |
|
24-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add perf debug for a corner case.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 936a3ca6fdbf166ee89d410653f7948de3282bdc |
|
24-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Fix access mode of index buffer rebase.
It doesn't matter with our current implementation of MapBufferRange,
but it was wrong -- the result pointer is read by intel_upload_data().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 016928b163634aece5a3e911dde6b643d491f025 |
|
24-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Fix indentation of index buffer rebase code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1a316af0343b1c1b345d6209a687ce858b47c438 |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Pass in the glarray to get_surface_type.
Dereffing all the values in the two callers was just pointless, and
the function isn't inlined so there was actual code impact.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 80aeda2784bc1e31a2047a1959139fbc40abf5c8 |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Remove nonsense comment.
vb.inputs_read has never been a thing, even in the initial import.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 23e5503348739fd313e0b00892006b165e961d8d |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Remove NDEBUG undef that was snuck in.
If you want debug, set --enable-debug in your config flags.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8fe43b6dc96c36bc45332c67d8f84849b5060800 |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: reuse _mesa_sizeof_type for index buffer types.
The core Mesa code has just one more case than this (GL_BITMAP), so I
don't see any cause to special-case it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b859a12f217042544450083d36b55f8391ca2909 |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Reuse precalculated ib_type_size value.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9aa02a205d886b27325428785a63be7f8b8ae5ec |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Drop debug check for knowing the size of a type.
This was added in b93684f5f311f89c965960ab42bfea71a397b180, but there's
no need for it -- get_size has to succeed, and it has an assert for us
in debug builds.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5ae3c207918e10282f53402ae276b31b2235c2dc |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Stop worrying about alignment of vertex data.
For our current types, the required alignment is actually just 1 byte.
When we get doubles, we have to worry (those have to be aligned to the
natural size), but we don't have doubles yet and they'll just be a
special case.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2a7a5062c9821bb986ed50e866c27ec26c4a41af |
|
23-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Use the glarray _ElementSize that Mesa tracks for us.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a60c567fcf29f5d2a41222a8826fee2cb0eb4458 |
|
04-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Support GL_FIXED and packed vertex formats natively on Haswell+.
Haswell and later support the GL_FIXED and 2_10_10_10_rev vertex formats
natively, and don't need shader workarounds.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1b37fc40fc1d443e7ab9f930f78af9a32525698a |
|
17-Dec-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix gl_VertexID when there are no other vertex inputs.
brw_emit_vertices contains special case logic to handle the case where
a vertex shader doesn't read any inputs. This special case logic was
incorrectly activating in the case were the only vertex input is
gl_VertexID. As a result, if a shader used gl_VertexID but used no
other inputs, then all vertices got a gl_VertexID of zero.
Fixes oglconform test "ubo-usage advanced.transform_feedback".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 23f4411c41f96a1b755259c4a6b23747e95a5ece |
|
22-Nov-2012 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: support 2_10_10_10 formats in get_surface_type.
Always use R10G10B10A2_UINT; Most of the other formats we'd like
don't actually work on the hardware. Will emit w/a for scaling,
sign recovery and BGRA swizzle in the VS.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f9a08f7f0f9f65546db4c7388e445fa39f0842c6 |
|
22-Nov-2012 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: implement get_size for 2_10_10_10 formats
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1e08d5452eaf80d63e626119142facc6c549a58e |
|
31-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965: Fix uploading user vertex arrays with basevertex set.
If the index buffer is full of values like "0 1 2 3", but basevertex is 4, we
need to upload at least vertex data for elements 4 5 6 7. Whether we also
upload 0 1 2 3 is a question of whether there are VBOs present or not -- see
the code setting start_vertex_bias in brw_draw_upload.c.
Fixes piglit draw-elements*base-vertex user_varrays
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 369419e847d4a3aeac9386b13204f09c689900da |
|
27-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't replicate data for zero-stride arrays when copying to VBOs.
When copy_array_to_vbo_array encountered an array with src_stride == 0
and dst_stride != 0, we would replicate out the single element to the
whole size (max - min + 1). This is unnecessary: we can simply upload
one copy and set the buffer's stride to 0.
Decreases vertex upload overhead in an upcoming Steam for Linux title.
Prior to this patch, copy_array_to_vbo_array appeared very high in the
profile (Eric quoted 20%). After the patch, it disappeared completely.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3d2b4291c2e448fd51c14fc1ff52ceaef00788cc |
|
27-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't bother trying to extend the current vertex buffers.
This essentially reverts the following:
commit c625aa19cb53ed27f91bfd16fea6ea727e9a5bbd
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Feb 18 10:37:43 2011 +0000
intel: extend current vertex buffers
While working on optimizing an upcoming Steam title, I broke this code.
Eric expressed his doubts about this optimization, and noted that the
original commit offered no performance data.
I ran before and after benchmarks on Xonotic and Citybench, and found
that this code made no difference. So, remove it to reduce complexity
and make future work simpler.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 459b28aba7c4ef0afe8d23dd2953e236d1bf7aed |
|
18-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965: Merge brw_prepare_query_begin() and brw_emit_query_begin().
This is a leftover from when we had to split those two functions due to
the separate BO validation step.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7f9e1a7720f5e7b464c39e3640e8ed64687e9645 |
|
21-Sep-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add a comment explaining one of the brw_draw_upload.c loops.
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0334e8dc25d09e3254e61d5d122b4fd7bfbd627a |
|
21-Sep-2012 |
Eric Anholt <eric@anholt.net> |
i965: Remove broken non-interleaved-to-interleaved upload code.
This failed when all the uploads to occur were uniform-type vertex data (like
glColor4f being active across a DrawArrays), because it would upload 1 element
instead of 1 element per vertex. There was no citation for how this code
helped any particular application, and it breaks ETQW, so just remove it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47170
NOTE: This is a candidate for the 9.0 and 8.0 branches.
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 815d9d405c69bb07d550ae9f79283dcdc7466e2c |
|
25-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix primitive restart on Haswell.
Haswell moved the "Cut Index Enable" bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0xffffffff.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 628dfe9511c15cc265b103e4752e3ee31b04602b |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop the old sw fallback for position array being disabled.
This code has been in the driver since the first commit. I think it was
trying to stop rendering from happening with a disabled position array. Core
mesa has since had changes to deal with disabled position arrays correctly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 04a11b5f5e22155e5816e2da560b485eb0eaaec9 |
|
28-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for edge flags.
Fixes the 3 new piglit edgeflag tests.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40707
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b3367f56d880550befb31a0100c448e1d607915f |
|
28-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Convert EdgeFlagPointer values appropriately for the VS on gen4.
Fixes piglit gl-2.0/edgeflag.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3588098ed85bbd6bacac5a8dd3774569f1314783 |
|
27-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: enable ARB_instanced_arrays extension
Set the step_rate value when drawing to implement
ARB_instanced_arrays for gen >= 4.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f9389fbfb204995a650047949c48ab2b2703bfcf |
|
13-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: add flag to enable cut_index
When brw->prim_restart.enable_cut_index is set, the cut index
will be enabled when uploading index_buffer commands.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c59bdee12ebc14fb97e33b8ef9df666422dafba5 |
|
27-Feb-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable PrimitiveID upload.
We currently don't support gl_PrimitiveID, and I believe asking the
hardware to generate it results in vertex cache invalidations.
This could result in slowdowns for applications that use gl_InstanceID,
which would be counter-productive. Just turn it off for now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dca6a28a14f22d77273d79d44f57b0d853c0242d |
|
31-Oct-2011 |
Mathias Fröhlich <Mathias.Froehlich@web.de> |
mesa: Make gl_program::InputsRead 64 bits.
Make gl_program::InputsRead a 64 bits bitfield.
Adapt the intel and radeon driver to handle a 64 bits
InputsRead value.
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1c65abb211e6a3df8c46180ae3242486ee97dc8d |
|
09-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gl_VertexID and gl_InstanceID.
The compiler setup for these VF-uploaded attributes looks a little
cheesy with mixing system values and real VBO-sourced attributes. It
would be nice if we could just compute the ATTR[] map to GRF index up
front and use it at visit time instead of using ir->location in the
ATTR file. However, we don't know the reg_offset at
visit(ir_variable *) time, so we can't do the mapping that early.
Fixes piglit vertexid test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9472f6677672ac89d6addba025b33287670da9e9 |
|
09-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace a should-never-happen fallback with asserts where it matters.
We only allow 16 vec4s of attributes in our GLSL/ARB_vp programs, and
1 more element will get used for gl_VertexID/gl_InstanceID. So it
should never have been possible to hit this fallback, unless there was
another bug. If you do hit this, you're probably using gl_VertexID
and falling back to swrast won't work for you anyway.
This also updates the limits for gen6+.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 29e2bc8b13be0f7ec48f8514e47322353e041365 |
|
01-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for integral vertex attributes.
When a vertex shader input attribute is declared with an integral type
(e.g. ivec4), we need to ensure that the generated vertex shader code
addresses the vertex attribute register using the proper register
type. (Previously, we assumed all vertex shader input attributes were
floating-point).
In addition, when uploading vertex data that was specified with
VertexAttribIPointer, we need to instruct the vertex fetch unit to
convert the data to signed or unsigned int, rather than float. And
when filling in the implied w=1 on a vector with less than 4
components, we need to fill it in with the integer representation of 1
rather than the floating-point representation of 1.
Fixes piglit tests vs-attrib-{ivec4,uvec4}-precision.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c83bfeabc6af82f061d53b8b5923ee26f14efb58 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move index buffer upload to emit() time.
It's consumed by the brw_emit_index_buffer() code at emit() time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 78a010127f3eb600fb7b145bc562b62a77af5a34 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Do a hack job of merging VB prepare()/emit() together.
I don't really want to touch this impenetrable code in this series, so
just call the one function from the other, since no other atom cares
about them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| eaf4d3e6e2493a6e0b20d1205a5fb33ce500c9c2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the validated BO list, now that it's unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ddc348d83eff8c12ff0e6c245c32fa65120e7f4a |
|
27-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Make sure to upload the data for a collection of Stride == 0 arrays.
Commit d631c19db47181129811080bfa772b210d762d4d avoided this problem
by forcing the driver to get the min/max index, but that commit was
broken, so just fix the driver problem (confusion between "do I need
to upload any data?" and "do I need the index bounds in order to
upload any data?").
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0d636213d491f88726155e12c3b445a88e0f1cd8 |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Only map the necessary buffer range in brw_prepare_indices
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 28249bd260f4c52badf3eb61ade2744604b21bca |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Eliminate dd_function_table::MapBuffer
Replace all calls to dd_function_table::MapBuffer with appropriate
calls to dd_function_table::MapBufferRange, then remove all the cruft.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b2184da684fc20849b5e6e554f0a0f92d2872ce9 |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Fix incorrect access parameter passed to MapBuffer
The code previously passed GL_DYNAMIC_DRAW for the access parameter.
By inspection, I believe that all drivers would treat this as
GL_READ_WRITE because it's not GL_READ_ONLY and it's not
GL_WRITE_ONLY.
It appears the i965 code wants GL_WRITE_ONLY (it's about to write a
bunch of data in, never read data), while the arrayelt code is
GL_READ_ONLY (just dereffed as arguments to CALL_Whatever*v).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Keith Whitwell <keithw@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 12d924c5ae14a1c6a05a3dcae29b77e7668e227d |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Remove target parameter from dd_function_table::MapBuffer
No driver used that parameter, and most drivers ended up with a bunch
of unused-parameter warnings because it was there.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 56f0c00f125ee75caeadc1c9e8cab8a488635e5e |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Remove target parameter from dd_function_table::UnmapBuffer
No driver used that parameter, and most drivers ended up with a bunch
of unused-parameter warnings because it was there.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 797522f1c9c0f4aa75e4c9c854e79c44ed374169 |
|
13-Jul-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename CMD_VERTEX_(BUFFER|ELEMENT) to 3DSTATE_VERTEX_...S.
This makes our code use the same names as the documentation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a5a36d9b158a317daa1cf10a6b6ed2bed6b22750 |
|
11-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't try to continue space before the start of a VBO.
This loop is trying to see if all the buffers to be uploaded happen to
be the same increment from the start of the 3DSTATE_VERTEX_BUFFERS
currently loaded in the hardware. However, we might be at a smaller
offset than the previous set of VERTEX_BUFFERS, so we can't reuse
because that packet made the first entry be its starting offset (you
can't access outside the given bounds).
Fixes piglit ARB_vertex_buffer_object/elements-negative-offset.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5c2c60175d0e5da9b0e9688538b84dedf05107de |
|
11-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add missing state flag for vertex elements on current VS program.
Fixes a missing 3DSTATE_VERTEX_ELEMENTS on topogun.trace.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 4176025d463e7733dac19788b45b6472b65d62d4 |
|
08-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_FIXED vertex attributes.
This sadly requires work in the VS to rescale them, because the
hardware doesn't support this format natively.
Fixes arb_es2_compatibility-fixed-type and gtf/fixed_data_type.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 62b79b4bb9d8a4a8679c3d1e1f5455ce33d7b90a |
|
20-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set Address Modify Enable in VERTEX_BUFFER on Ivybridge.
Otherwise, Ivybridge seems to ignore the newly supplied data, giving us
rubbish for vertices.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f703ba8c42e924ee6d5e4308c3888e434d8ba98c |
|
12-Apr-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Revert "i965: Reinstate max-index paranoia"
This reverts commit b4cbd2b312d53a50603e2cda925711bc9def4517.
It looked like a safe sanity check. It missed the issue of the start of
the buffer not being at 0, but even that was not enough to explain why
setting the max vertex index caused glyphs to be dropped from the game
'Achron'.
Instead, the issue appears to be related to the use of the vertex bias
and so we would need to re-emit the max-index every time we adjusted the
bias, so re-emitting the relocations and defeating the original
optimisation.
Reported-and-tested-by: Thomas Jones <thomas.jones@utoronto.ca>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35163
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5ae1d195061b5f01d85b8f6d48d89d7995b07f4f |
|
09-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use ffs() on a 32-bit int value instad of ffsll().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9d31138f53c0bee9193af73850ab6febddd29f51 |
|
03-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Fix extending VB packets
Computation of the delta of this array from the last had a silly little
bug and ignored any initial delta==0 causing grief in Nexuiz and
friends.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1546291e5b8d3ac02f5bee38252f9d479bcf95cc |
|
03-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Align index to type size and flush if the type changes
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b93684f5f311f89c965960ab42bfea71a397b180 |
|
03-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Prevent using a zero sized (or of unknown type) vertex array
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 900a5c91eeb3acae7ee0ad331154531c4dba96e1 |
|
01-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Use negative relocation deltas to minimse vertex uploads
With relaxed relocation checking in the kernel, we can specify a
negative delta (i.e. pointing outside of the target bo) in order to fake
a range in a large buffer. We only then need to upload the elements used
and adjust the buffer offset such that they correspond with the indices
used in the DrawArrays.
(Depends on libdrm 0209428b3918c4336018da9293cdcbf7f8fedfb6)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9fa380ccdcf987430b9bff8e5216869e05b0aaea |
|
01-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Undo 'continuation of vb packets'
This breaks nexuiz for unknown reason; disable until a true fix can be
found.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 69b3f24658b74f15b622adda6464a6fcb87f4ee6 |
|
01-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Fix uploading of shortened vertex packets
... handle all cases and not just the interleaved upload.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6ddfb322f58c7e00db73e25689ee55ffa1111bd9 |
|
24-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Upload all vertices used
... and take advantage of start_vertex_bias to trim to [min_index,
max_index] where possible (i.e. when we need to upload all arrays).
Fixes half_float_vertex(misc.fillmode.wireframe)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34595
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5ce0f7f10908a0636900bae783cb426a6c607673 |
|
24-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Reset the buffer offset after releasing reference to packed upload
Fixes oglc/vbo(basic.bufferdata)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 135ccb2daecb7792dfb17e66ab0acb79a97f78c8 |
|
24-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Unmap the correct pointer after discontiguous upload
Fixes piglit/fbo-depth-sample-compare:
==14722== Invalid free() / delete / delete[]
==14722== at 0x4C240FD: free (vg_replace_malloc.c:366)
==14722== by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695)
==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd
==14722== at 0x4C244E8: malloc (vg_replace_malloc.c:236)
==14722== by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256)
==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3adc108b4a7460ef5d92c0f5f0ee655d4ca6cb32 |
|
22-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Trim the interleaved upload to the minimum number of vertices
... should have no impact on a properly formatted draw operation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b4cbd2b312d53a50603e2cda925711bc9def4517 |
|
22-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Reinstate max-index paranoia
Don't trust the applications not to reference beyond the end of the
vertex buffers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3377faffcdc7227bd27381894c87c7600547744f |
|
22-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Zero the offset into the vbo when uploading non-interleaved
Fixes regression from 559435d9152acc7162e4e60aae6591c7c6c8274b.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9e872a5865c66ed0a518dd1c6c54e72f3afa71f1 |
|
22-Feb-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.
Fixes regression in scissor-stencil-clear and 5 other tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a43f20e0699f0b60d1e1e3e7a0693192f8d2895d |
|
21-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Remove spurious duplicate ADVANCE_BATCH
... a leftover from a bad merge.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c625aa19cb53ed27f91bfd16fea6ea727e9a5bbd |
|
18-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: extend current vertex buffers
If the next vertex arrays are a (discontiguous) continuation of the
current arrays, such that the new vertices are simply offset from the
start of the current vertex buffer definitions we can reuse those
defintions and avoid the overhead of relocations and invalidations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a07e4811794051dc65187d17b7f85e340e61854e |
|
18-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Use specified alignment for writes into the upload buffer
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d9e591391d490c83ce301aa568a2e0afe4cc3c0a |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Clean up brw_prepare_vertices()
Use a temporary glarray variable to replace the numerous input->glarray.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3630d5b69afcecc3142d2c4897835175886f4bd8 |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: combine short memcpy using a temporary allocated buffer
Using a temporary buffer for large discontiguous uploads into the common
buffer and a single buffered upload is faster than performing the
discontiguous copies through a mapping into the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dfc6c96e5c470f6136cad26b753c024538fd09a0 |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: upload normal arrays as interleaved
Upload the non-vbo arrays into a single interleaved buffer object, and
so need to just emit a single vertex buffer relocation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 94d73d700e804ce78c214c58e84382c81dcb8280 |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: interleaved vbo
If the user passed in several arrays interleaved in the same vbo, only
emit a single vertex buffer and relocation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 559435d9152acc7162e4e60aae6591c7c6c8274b |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: emit one vb packet per vbo
Track reuse of the vertex buffer objects and so minimise the number of
vertex buffers used by the hardware (and their relocations).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| abb51097566c401344b22a7ee9d699f002a1977f |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: upload transient indices into the same discontiguous buffer
As we now pack the indices into a common upload buffer, we can reuse a
single CMD_INDEX_BUFFER packet and translate each invocation with a
start vertex offset.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 60bb3e5614a533ff886bf1ddb6341ff34f75c886 |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: suppress repeat-emission of identical vertex elements
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8a9e67b8df9836408270a4bc3660ec45b622ae56 |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Buffered upload
Rather than performing lots of little writes to update the common bo
upon each update, write those into a static buffer and flush that when
full (or at the end of the batch). Doing so gives a dramatic performance
improvement over and above using mmaped access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| abb37861d9f3310fe2d16194d893682092f41087 |
|
08-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Combine vb upload buffer with the general upload buffer
Reuse the new common upload buffer for uploading temporary indices and
rebuilt vertex arrays.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e476e122207e6195a16a8c7d2cab90eeba227934 |
|
08-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Pack dynamic draws together
Dynamic arrays have the tendency to be small and so allocating a bo for
each one is overkill and we can exploit many efficiency gains by packing
them together.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 45ba7afbd15b28ffd61548ee46334ff4527a7cde |
|
29-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Trim the trailing NOOP from 3DSTATE_INDEX_BUFFER
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 43873b53c4d15f10f0321c770b1b8bd537cc226d |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't rebase the index buffer to min 0 if any arrays are in VBOs.
There was a check to only do the rebase if we didn't have everything
in VBOs, but nexuiz apparently hands us a mix of VBOs and arrays,
resulting in blocking on the GPU to do a rebase.
Improves nexuiz 800x600, high-settings performance on my Ironlake 41%
(+/- 1.3%), from 14.0fps to 19.7fps.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 527a9a4de218cae89d7faf92788f88ce1f9387b6 |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use intel->gen >= 6 instead of IS_GEN6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f5bd48cf673456ffea730f28c9b95c6883399162 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use R16G16B16A16_FLOAT for 3-component half-float.
The RGBX version isn't supported as a vertex input type, but since we
force the last channel's value anyway, this should be fine. The only
potential risk I see is in the limiter on VBO reads past the end of
the buffer forcing the whole vertex to 0 when the A channel lands past
the end.
Fixes piglit draw-vertices-half-float.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1489f108f4a9b53b42d3d4123da64ccdb7aafdde |
|
21-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix up some Sandybridge define checks for the structure rebase.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ff3997904ab988824e744fdbecde6eb79d9bf40f |
|
04-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Reconnect the index/vertex setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 32f2fd1c5d6088692551c80352b7d6fa35b0cd09 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace _mesa_malloc, _mesa_calloc and _mesa_free with plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 96f2f0daeadd5bd2d8433e31a1b122c2bd709390 |
|
18-Jan-2010 |
Dave Airlie <airlied@linux.ie> |
i965: add support for ARB_half_float_vertex
enables the extension on i965 and adds support to the draw upload for
the vertex format.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5203b7227ccb6b618fa42f08434d4a3cf123dca2 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop batchbuffer cliprect_mode tracking
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c67bb15d4e3da430d511444bd7d159ccb0c84b73 |
|
29-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
intel: Silence compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-GEM support.
This really isn't supported at this point. GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3d36d6b4cf735e93a6ae5eadf28e671252fb5303 |
|
13-Nov-2009 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/mesa_7_6_branch'
|
| 5f305b1db925c819ddeb29a75f6fbad6500a2d11 |
|
11-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix VBO last-valid-offset setup on Ironlake.
Instead of doing math based on the (broken for VBO && offset != 0)
input->count number, just use the BO size. Fixes assertion failure in ETQW.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e9b17d6477f99838fc7f261ea1b8d47eea12f42f |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: be clear that the Fallback field is a boolean, not a bitfield
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 755161b88843f3cfead9a02e076d1a04687d9082 |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()"
This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c.
It turns out the i965 driver uses the intel->Fallback field as a boolean,
not as a bitmask. The intelFallback() function is a no-op in the i965
driver. It would have been nice if there were some comments about this.
I'll fix that next...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 43dc91f8bbb69499a6a0326a78e434b313f73c2c |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: be clear that the Fallback field is a boolean, not a bitfield
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f9e334cb32152fd342ac6b1dd4776215af6e1d49 |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()"
This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c.
It turns out the i965 driver uses the intel->Fallback field as a boolean,
not as a bitmask. The intelFallback() function is a no-op in the i965
driver. It would have been nice if there were some comments about this.
I'll fix that next...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ab9d1011f5549502a4b960c2067cde69856a2719 |
|
23-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| 8810b8f67135185d1044746bb861fe2ff997626c |
|
23-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix hacked Fallback usage in brw_prepare_vertices()
Setting intel->Fallback = 1 clobbered any fallback state that was already
set. Not sure where this hack originated (the git history is a little
convoluted). Define and use a new BRW_FALLBACK_DRAW bit instead. This
shouldn't break anything and could potentially fix some bugs (but no
specific ones are known).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ce3801ab87ef6eb29e5b81c2acfdd102f7b9c0ae |
|
14-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| f3be27c0cf8a4c47230f31d9d66bde7340ffb204 |
|
11-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix the last valid address setting for the index buffer.
Again, last valid address, not first invalid address. Fixes regression
in 255e5be265133280293bbfd8b2f9b74b2dec50bb that the kernel now catches
and caused piglit draw_elements_base_vertex to fail.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a82da7fa263c7fb6b902285994136890e6dc3278 |
|
11-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix the bounds emitted in the vertex buffer packets.
It's the address of the last valid byte, not the address of the first
invalid byte.
This should also fix problems with rendering with the new sanity checks in
the kernel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7bf63473623e01933adc0e8f4464eda8f2860564 |
|
09-Sep-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| 0c309bb494b6ee1c403442d1207743f749f95b6e |
|
09-Sep-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
Conflicts:
Makefile
configs/default
progs/glsl/Makefile
src/gallium/auxiliary/util/u_simple_shaders.c
src/gallium/state_trackers/glx/xlib/xm_api.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/intel/intel_context.h
src/mesa/drivers/dri/intel/intel_pixel.c
src/mesa/drivers/dri/intel/intel_pixel_read.c
src/mesa/main/texenvprogram.c
src/mesa/main/version.h
|
| b2de02852381dccea6cb9bdca049d5629cca80ef |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: #include clean-ups
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 00aac1d29a7ca06d1f1ac429371d9a6774873389 |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: use _mesa_is_bufferobj()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8de625c7cf639c583e8bf43acb1214010989bb64 |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix incorrect test for vertex position attribute
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 63b3fa2bcecc75a116ce651da435d205ccd43584 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Assert that the offset in the VBO is below the VBO size.
This avoids sending a bad buffer address to the GPU due to programmer error,
and is permitted by the ARB_vbo spec. Note that we still have the opportunity
to dereference past the end of the GPU, because we aren't clipping to a
correct _MaxElement, but that appears to be harder than it should be. This
gets us the 90% solution.
Bug #19911.
(cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9eca0e5350377148976e0d1200f98bd20ac28197 |
|
30-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Don't emit bad packets when no VBs are referenced.
It appears that sometimes Mesa (and I suppose a VS could as well) emits
a program which references no vertex data, and thus we end up with
nr_enabled == 0 even though some VBs are enabled. We'd end up emitting
VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs.
Bug #22945 (wine with an uncompiled VS)
(cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7e26bdb849b75f4aeb69cf8b1fdffbc461265490 |
|
03-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Calculate enabled[] and nr_enabled once and re-use the values.
The code duplication bothered me.
(cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 213ac4bb5de1cef601e0677ef2e5ca1779851e28 |
|
24-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set the max index buffer address correctly according to the docs.
It's the last addressable byte, not the byte after the end of the buffer.
(cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| cab307ce6b32d2ffdb0eb3bb5bae93c6fb9305fb |
|
15-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: rename var: s/tmp/vs_inputs/
(cherry picked from commit 840c09fc71542fdfc71edd2a2802925d467567bb)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b9789948e0b5c5fad7952ea5b731c675d50a4f58 |
|
15-Aug-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: disable bounds checking on arrays with stride 0
if stride is 0 we cannot use count as max index for bounds checking,
since the hardware will simply return 0 as data for indices failing
bounds check. If stride is 0 any index should be valid hence simply
disable bounds checking in this case.
This fixes bugs introduced with e643bc5fc7afb563028f5a089ca5e38172af41a8.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 255e5be265133280293bbfd8b2f9b74b2dec50bb |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Avoid re-uploading the index buffer when we don't need to.
No performance difference proven at 95% confidence with my GLSL demo (n=10).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e643bc5fc7afb563028f5a089ca5e38172af41a8 |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use _MaxElement instead of index-calculated min/max for VBO bounds.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d7430d942f6c7950a92367aeb13b80cf76ccad78 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Assert that the offset in the VBO is below the VBO size.
This avoids sending a bad buffer address to the GPU due to programmer error,
and is permitted by the ARB_vbo spec. Note that we still have the opportunity
to dereference past the end of the GPU, because we aren't clipping to a
correct _MaxElement, but that appears to be harder than it should be. This
gets us the 90% solution.
Bug #19911.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d1fbfd0f962347e4153db3852292d44de5aea863 |
|
30-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Don't emit bad packets when no VBs are referenced.
It appears that sometimes Mesa (and I suppose a VS could as well) emits
a program which references no vertex data, and thus we end up with
nr_enabled == 0 even though some VBs are enabled. We'd end up emitting
VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs.
Bug #22945 (wine with an uncompiled VS)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9b9cb30d128fc5f1ba77287696ecd508e640efde |
|
03-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Calculate enabled[] and nr_enabled once and re-use the values.
The code duplication bothered me.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b72dea5441e8e9226dabf1826fa3bc129c7bc281 |
|
24-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set the max index buffer address correctly according to the docs.
It's the last addressable byte, not the byte after the end of the buffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 840c09fc71542fdfc71edd2a2802925d467567bb |
|
15-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: rename var: s/tmp/vs_inputs/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e7aef006e50d0b859c621267af8376f5a0f43445 |
|
06-Apr-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use GTT maps when available to upload vertex arrays and system VBOs.
This speeds up OA on my GM45 by 21% (more than the original CPU cost of
the upload path). We might still be able to squeeze a few more percent out
by avoiding repeatedly mapping/unmapping buffers as we upload elements into
them.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 36daee1c7bec44b9d3641f056c84b3b2f39fabd9 |
|
26-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: asst. casts to silence warnings
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dab586b0755bffa7c4da0fdc571e0f504f4066c2 |
|
23-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: enable GL_EXT_vertex_array_bgra
Simply a matter of choosing the right surface/vertex format for GLubyte/GL_BGRA arrays.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2fc9d671e0be77676818da51cd3b35b52af79421 |
|
12-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix VB refcount leak on aperture overflow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix check_aperture calls to cover everything needed for the prim at once.
Previously, since my check_aperture API change, we would check each piece of
state against the batchbuffer individually, but not all the state against the
batchbuffer at once. In addition to not being terribly useful in assuring
success, it probably also increased CPU load by calling check_aperture many
times per primitive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c157cfc6376f7469ab272b18868183e5ff9ac754 |
|
07-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Add ARB_occlusion_query support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 94d3a30df759bb7c2724fdcee9e89a350d3a4d8b |
|
08-Oct-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Fix a potential assertion failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d533da2db873942b3f8676a754b8be3c9718bedf |
|
24-Sep-2008 |
Eric Anholt <eric@anholt.net> |
i965: Cope with batch getting flushed in the middle of batchbuffer emits.
This isn't required for GEM (at least, yet), but the check_aperture code
for non-GEM results in batch getting flushed during emit. brw_state_upload
restarts state emits, but a bunch of the state emit functions were assuming
that they would be called exactly once, after prepare and before new_batch.
Bug #17179.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 35fd72756a05463568d94862f4fcd234903e1204 |
|
08-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track move of bo_exec from drivers to bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 687cd467b3461691a6fd03d3bc38c01ed79c06fd |
|
21-Aug-2008 |
Eric Anholt <eric@anholt.net> |
i965: use dri_bo_subdata in vertex upload to get pwrite used.
Otherwise, we would ping-pong objects to GTT and back as we did pwrite on
indices (flushed and mapped to GTT) and mapped for vertices (moved back to
CPU domain).
Fixes bug #17180.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
|
11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dbf3c5247c90bd35c0b2002e3b972a2dd4c8b130 |
|
04-Jun-2008 |
Keith Packard <keithp@keithp.com> |
Merge commit 'origin/master' into drm-gem
Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.h
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h
src/mesa/drivers/dri/intel/intel_ioctl.c
|
| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ab50ddaa9173ae108833db0edb209045788efc41 |
|
07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 17adf04e5c1da72a51815f3fdb9de2f3a8149c1a |
|
06-May-2008 |
Dave Airlie <airlied@panoply-rh.(none)> |
i965: fix googleearth in classic mode.
In classic mode googleearth triggered a case where vbos weren't getting accounted properly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| fda4895d26eec6d810da51a6c023a5459230ff6a |
|
18-Apr-2008 |
Dave Airlie <airlied@panoply-rh.(none)> |
i965: fix vb aperture space check
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e92e3848e7c8c1481e785973d8609072f2f5db21 |
|
18-Apr-2008 |
Dave Airlie <airlied@panoply-rh.(none)> |
965: fix vb upload size check
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2abcc512a3ce81bc11ff2b45a2208d3400a2385d |
|
03-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert brw_draw_upload to managing dri_bos, not gl_buffer_objects.
This helps us avoid a bunch of mess with gl_client_arrays that we filled
with unused data and confused readers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0907c639c8509cda4507b28c1399813a09a81c5e |
|
02-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove dead structure in brw_draw_upload.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7b8892f50482359625e36005c2b460a921ff796c |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Move temporary vbo array storage into the function using it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c86ec87830dba86b257ccddc832b746af955eb05 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove dead brw_vertex_element members.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 4e13067d0f95b280da3fef2deb7e59466ea73818 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Add a wrapper around interleaved copy_array_to_vbo_array for profiling.
If compiled with optimization, it shouldn't appear at all, and helps me for
now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| df44fefced61d35c302907cb716fa0f9337ae526 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Avoid overloaded use of the term 'input' for clarity.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 931685e243af52271d4cdc0ddc8ea153036dee42 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Replace VEP/VBP state structures with inline batch emits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 540faf5f91057ef311999afc5a6366bebe7dec33 |
|
11-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove an open-coded memcpy.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a04b632350e5d0e9994fc667afc59407a39da0ba |
|
10-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:
- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
(copybuffers, clears).
All callers should now be fixed to use one of these states for any batchbuffer
emits. Thanks to Keith Whitwell for pointing out the failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5a49e84fcd858a1ad9c0ad839ccbe93504593cd0 |
|
09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Clarify a bit of index buffer upload code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bea6b5fe5aa3138cec8d057766ae48da4aa57dee |
|
20-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Enable EXT_framebuffer_object.
To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c0b4257aa9ba783674ccf7162799385734dff211 |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Move to using shared texture management code.
This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support. It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3fe9d5cbb7c680c6fb88a2eba678b28a2a06949e |
|
15-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Merge intel_buffer_objects to shared.
965 gains fixed TTM typing of the buffer object buffers and unused PBO
functions, and 915 gains buffer size == 0 fixes from 965.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 84a076079d3a038115a39b1c283b46a574591e07 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] warnings cleanup
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 77e0523fb7769df4bf43747e136b1653b2421b97 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0fc9efd8f0b1b6c4e3525a50e3478e5aef72531a |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
Replace bmBufferOffset usage in batchbuffer setup with OUT_RELOC.
This is in preparation for 965 TTM.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e886ae4c58bc98897d6901e3f30deea008bc7f8a |
|
28-Sep-2007 |
Eric Anholt <eric@anholt.net> |
Revert "WIP 965 conversion to dri_bufmgr."
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e.
Somehow I ended up with my branch's save-this-while-I-work-on-master commit
actually on master.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b2f1aa2389473ed09170713301b042661d70a48e |
|
27-Sep-2007 |
Eric Anholt <eric@anholt.net> |
WIP 965 conversion to dri_bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 38c30a81844214b030c9c637f9cf97bd2bf19cde |
|
26-Sep-2007 |
Eric Anholt <eric@anholt.net> |
[965] Remove AUB file support.
This code existed to dump logs of hardware access to be replayed in simulation.
Since we have real hardware now, it's not really needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ea07a0df9a2f689b8f5acaf92c40bbbd602cab3c |
|
14-Sep-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: align the address of the first element within
the index buffer. (fix#11910)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b59657ad965f9471574e914b861bb1d2a17d772e |
|
02-Feb-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Merge branch 'vbo-0.2'
Conflicts:
src/mesa/main/texcompress_s3tc.c
src/mesa/tnl/t_array_api.c
|
| 47d463e954efcd15d20ab2c96a455aa16ddffdcc |
|
02-Feb-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Modify assert to reflect rebase criteria
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5368ae5ec329ddad5963d55b17cd4eccbc83d32f |
|
01-Feb-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Correct usage/meaning of max_index parameter.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 893526b8a823fe1b88f2b46376155afb91c84016 |
|
30-Jan-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Use new rebase helper. Remove other rebase code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 869b8ad499717eda4a1be04de4e516134123402c |
|
21-Jan-2007 |
Eric Anholt <eric@anholt.net> |
Add _mesa_ffsll() for compatibility on OSes without ffsll(), and use it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6a3fdc3a1ea6c306d9543791bf172dd1052d7382 |
|
16-Jan-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Merge branch 'master' of git+ssh://keithw@git.freedesktop.org/git/mesa/mesa into vbo-0.2
Conflicts:
src/mesa/array_cache/sources
src/mesa/drivers/dri/i965/brw_context.c
src/mesa/drivers/dri/i965/brw_draw.c
src/mesa/drivers/dri/i965/brw_fallback.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/i965/brw_vs_tnl.c
src/mesa/drivers/dri/mach64/mach64_context.c
src/mesa/main/extensions.c
src/mesa/main/getstring.c
src/mesa/tnl/sources
src/mesa/tnl/t_save_api.c
src/mesa/tnl/t_save_playback.c
src/mesa/tnl/t_vtx_api.c
src/mesa/tnl/t_vtx_exec.c
src/mesa/vbo/vbo_attrib.h
src/mesa/vbo/vbo_exec_api.c
src/mesa/vbo/vbo_save_api.c
src/mesa/vbo/vbo_save_draw.c
|
| f58ec215c5669f36c2649acc9cbeda7383b86879 |
|
21-Nov-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Gary Wong's fix for 64 bit cleanness of vertex program inputs bitmask.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f2eb6434ab1cf72e938956c82d2f530368a6be4a |
|
31-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
cleanup code, compiles with vbo changes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| efef291dc71eb57f90785a26957f4b3e01733156 |
|
30-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
checkpoint - remove dead files, otherwise untested
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a2c50b0f4ad16855cf8a2ff2ab4029342f4297dd |
|
13-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Upload of interleaved arrays currently assumes that position is the
first element in the interleaved group. Add a test to catch cases
where this isn't true and use per-array uploads instead. Fixes compiz
glitches on x64.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|