| 726c32790eddcad9c19e4c1d1c740ab74424dad7 |
|
21-Jan-2017 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine the Gen6 SF and Clip viewport atoms.
The next patch will make the guardband calculation dependent on the
transformation matrix. Instead of computing it in both atoms, just
combine them into a single atom.
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit 89ad7f1be6a607b33ffb388516b5d0547b491c33)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9854a3ba8bd34b36737753f2ec7c61b06d64da4c |
|
12-Dec-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
main: use new driver flag for conservative rasterization state
Suggested by Marek.
v2: Use new driver flag (Marek)
v3: Fix i965 comments (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e9a25e024757c8daa0da86d064afd446824160dc |
|
01-Oct-2016 |
Nanley Chery <nanley.g.chery@intel.com> |
i965: Move gen8_disable_stages to brw_upload_initial_gpu_state
3DSTATE_WM_CHROMAKEY isn't programmed anywhere else.
3DSTATE_WM_HZ_OP is programmed, then cleared by blorp during a
HZ op, so repeatedly clearing it after every blorp execution is
redundant.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 477ea60b68d3e9a16d1f4947f95e3e7ce20e6f67 |
|
01-Oct-2016 |
Nanley Chery <nanley.g.chery@intel.com> |
i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_state
This packet is non-pipelined and doesn't ever change across emissions.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c596f47b80fab873d4509a03a427b3a2b464854f |
|
20-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: remove unused BRW_STATE_INTERPOLATION_MAP flag
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 91d61fbf7cb61a44adcaae51ee08ad0dd6b2a03b |
|
20-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: rewrite brw_setup_vue_interpolation()
Here brw_setup_vue_interpolation() is rewritten not to use the InterpQualifier
array in gl_fragment_program which will allow us to remove it.
This change also makes the code which is only used by gen4/5 more self contained
as it now has its own gen5_fragment_program struct rather than storing the map
in brw_context. This means the interpolation map will only get processed once
and will get stored in the in memory cache rather than being processed everytime
the fs changes.
Also by calling this from the fs compile code rather than from the upload code
and using the interpolation assigned there we can get rid of the
BRW_NEW_INTERPOLATION_MAP flag.
It might not seem ideal to add a gen5_fragment_program struct however by the end
of this series we will have gotten rid of all the brw_{shader_stage}_program
structs and replaced them with a generic brw_program struct so there will only
be two program structs which is better than what we have now.
V2: Don't remove BRW_NEW_INTERPOLATION_MAP from dirty_bit_map until the following
patch to fix build error.
V3 - Suggestions by Jason:
- name struct gen4_fragment_program rather than gen5_fragment_program
- don't use enum with memset()
- create interp mode set helper and simplify logic to call it
- add assert when calling function to show prog will never be NULL for
gen4/5 i.e. no Vulkan
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e512941537fbc25e97ecd778433e130769e2c6ec |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->tes.prog_data pointer.
Just say no to:
- brw->tes.base.prog_data = &brw->tes.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_tes_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 82c97ac710e31bea1f954060950f8b9faf2fb4d6 |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->tcs.prog_data pointer.
Just say no to:
- brw->tcs.base.prog_data = &brw->tcs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_tcs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 40258a13d5bf81303585eaf1859fcb85e373be3e |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->vs.prog_data pointer.
Just say no to:
- brw->vs.base.prog_data = &brw->vs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_vs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9d6ca7c3d091e1ab71ce2f75bf4f13dc8844d801 |
|
26-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Only emit 1 viewport when possible.
In core profile, we support up to 16 viewports. However, in the
majority of cases, only 1 of them is actually used - we only need
the others if the last shader stage prior to the rasterizer writes
gl_ViewportIndex.
Processing all 16 viewports adds additional CPU overhead, which hurts
CPU-intensive workloads such as Glamor. This meant that switching to
core profile actually penalized Glamor to an extent, which is
unfortunate.
This patch tracks the number of relevant viewports, switching between
1 and ctx->Const.MaxViewports if gl_ViewportIndex is written. A new
BRW_NEW_VIEWPORT_COUNT flag tracks this. This could mean re-emitting
viewport state when switching, but hopefully this is offset by doing
1/16th of the work in the common case. The new flag is also lighter
weight than BRW_NEW_VUE_MAP_GEOM_OUT, which we were using in one case.
According to Eric Anholt, x11perf -copypixwin10 performance improves by
11.5094% +/- 3.10841% (n=10) on his Skylake.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 856e0bd707d2ead26eb3a04be08885487850be38 |
|
18-Jun-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: create populate key functions for tcs and tes
These will be used by the on disk shader cache.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| bea048752ea95d5e074891f2131f54d6e0760538 |
|
30-Aug-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Merge gen7_clip_state atom into gen6_clip_state atom.
The original motivation was that gen6_clip_state ignored _NEW_POLYGON
as it didn't care about early culling. The only other change was that
Gen6 ignored BRW_NEW_TES_PROG_DATA as it doesn't have tessellation
shaders, but listening to this is harmless as it'll never be signalled.
Now that we've added _NEW_POLYGON for is_drawing_lines/points, we can
merge the two as the distinction is meaningless.
This actually fixes a bug, though: Gen8+ was using the gen6_clip_state
atom because it doesn't care about early culling, but it also needs
BRW_NEW_TES_PROG_DATA, which was missing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 786108e7b27e4728353d69ff60aa046987859d8e |
|
01-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Upload surface state for non-coherent framebuffer fetch.
This iterates over the list of attached render buffers and binds
appropriate surface state structures to the binding table block
allocated for shader framebuffer read.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a738732abf07e6264f079bbb31adb8723b8e91e3 |
|
14-Jul-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: fix compiler warnings for 32bit build
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4db98f8beb990676be0833dda6c37566d0283911 |
|
22-Jun-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine 3DSTATE_STREAMOUT emitters and genX_sol_state atoms.
They're basically the same. Let's avoid the code duplication.
v2: Fix SO_BUFFER_ENABLE stuff to only happen on Gen < 8 (caught
by Jason Ekstrand).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b6f250d7f2f704c8681aaa2a158d1a39851b8494 |
|
27-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Send the minimal number of STATE_BASE_ADDRESS packets.
STATE_BASE_ADDRESS stalls the whole pipeline, and the documentation
cautions us to emit it as little as possible for better performance.
We recently put some hacks in BLORP to try and avoid emitting it
if it was already set correctly. However, this wasn't quite minimal:
if BLORP is the first operation (i.e. glClear()), then it would emit
it, and subsequent draw calls would emit it again.
This caused a small drop in performance in GPUTest Triangle when
switching from Meta to BLORP.
Unlike most packets, STATE_BASE_ADDRESS isn't influenced by GL state:
it needs to be emitted once per batch, before most other commands, or
whenever we change the program cache BO. It's also valid in both the
3D and compute pipelines, which makes it even more unique.
This patch removes it from the atom mechanism and instead directly
calls it as part of every draw, compute dispatch, or BLORP operation.
We introduce a new flag indicating that STATE_BASE_ADDRESS has already
been emitted this batch, and if so, skip doing it again. When we make
a new program cache BO, we simply reset the flag, so the next operation
will emit it again. When we flush/reset the batch, we reset the flag.
This guarantees that we'll emit STATE_BASE_ADDRESS only when we have to.
It's also less code than the old atom mechanism.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 97179c606c998b4f6810b4dc1c5007c848cda4ee |
|
27-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine Gen4-7 and Gen8+ state base address emitters.
We're about to start calling it directly, and this means the callers
won't have to think about generations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7b70a12e1c6dffc63fbcec6a89af3e02ba9a1a1d |
|
27-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move Gen4-5 programs to brw_upload_programs() too.
This way all the programs are in one place again, and it also should
make some future STATE_BASE_ADDRESS related changes possible.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 65a5af6dd0550e93a5250582147689a1ddef9ffa |
|
22-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Introduce state flag for blorp
In the past, BLORP has clobbered all BRW_NEW_* state flags, to trigger
re-emission of the entire 3D pipeline on the next draw. However, there
are some packets BLORP simply leaves alone, so there's no need to
re-emit them. Trying to reduce the set of dirty bits flagged after
BLORP runs is tricky.
Instead, we introduce a BRW_NEW_BLORP flag. This should be set on any
atom which emits a packet that BLORP also emits. When BLORP runs, it
will flag BRW_NEW_BLORP, causing those packets to get re-emitted.
This also makes it easy to avoid re-emitting specific atoms - we can
simply drop the BRW_NEW_BLORP flag on those.
To start, we assume that all packets need to be re-emitted. This is the
safest approach and closest to the existing code's behavior. Many of
these are obviously not required, and can be dropped in subsequent
patches.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f275c61c30cbd389f9dac5223cc3904b3fe11e3e |
|
10-Feb-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split brw_upload_texture_surfaces into compute/render atoms.
When uploading state for the compute pipeline, we don't want to
look at VS/TCS/TES/GS/FS programs, as they might be stale, and
aren't relevant anyway. Likewise, the render pipeline shouldn't
look at CS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f8ac314cc2353f439e6a917db4e3aeaf47e2093e |
|
17-Jan-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Implement compute sampler state atom.
Fixes a number of GLES31 CTS failures and hangs on various hardware:
ES31-CTS.texture_gather.plain-gather-depth-2d
ES31-CTS.texture_gather.plain-gather-depth-2darray
ES31-CTS.texture_gather.plain-gather-depth-cube
ES31-CTS.texture_gather.offset-gather-depth-2d
ES31-CTS.texture_gather.offset-gather-depth-2darray
ES31-CTS.layout_binding.sampler2D_layout_binding_texture_ComputeShader
ES31-CTS.layout_binding.sampler2DArray_layout_binding_texture_ComputeShader
ES31-CTS.explicit_uniform_location.uniform-loc-types-samplers
ES31-CTS.compute_shader.resources-texture
Some of them were actually passing by luck on some generations even
though we weren't uploading sampler state tables explicitly for the
compute stage, most likely because they relied on the cached sampler
state left from previous rendering to be close enough.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92589
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93312
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93325
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93407
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93725
Reported-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 22ac1f692228d8c44155bfa637c8e34356c7e0b7 |
|
23-Dec-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Add state bit to trigger re-emission of color calculator state.
This will be used on Gen8+ to make sure that the color calculator
state pointers are re-emitted when switching back to the 3D pipeline
after some GPGPU workload due to a hardware workaround. There are
other state bits already defined that could be used to achieve the
same effect but they all cause a ton of unrelated state to be
re-emitted (e.g. BRW_NEW_STATE_BASE_ADDRESS), so just define a new
one, state bits are cheap.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 74b83fe368eab77da4ef0ea6eaeea54514d6dfc9 |
|
02-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add the TCS/TES state upload atoms to the gen7_atoms list.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 794eb9d7270456ab3d2cadbaf302192eca7f4dbc |
|
08-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Handle mix-and-match TCS/TES with separate shader objects.
GL_ARB_separate_shader_objects allows the application to mix-and-match
TCS and TES programs separately. This means that the interface between
the two stages isn't known until the final SSO pipeline is in place.
This isn't a great match for our hardware: the TCS and TES have to agree
on the Patch URB entry layout. Since we store data as per-patch slots
followed by per-vertex slots, changing the number of per-patch slots can
significantly alter the layout. This can easily happen with SSO.
To handle this, we store the [Patch]OutputsWritten and [Patch]InputsRead
bitfields in the TCS/TES program keys, introducing program recompiles.
brw_upload_programs() decides the layout for both TCS and TES, and
passes it to brw_upload_tcs/tes(), which store it in the key.
When creating the NIR for a shader specialization, we override
nir->info.inputs_read (and friends) to the program key's values.
Since everything uses those, no further compiler changes are needed.
This also replaces the hack in brw_create_nir().
To avoid recompiles, brw_precompile_tes() looks to see if there's a
TCS in the linked shader. If so, it accounts for the TCS outputs,
just as brw_upload_programs() would. This eliminates all recompiles
in the non-SSO case. In the SSO case, there should only be recompiles
when using a TCS and TES that have different input/output interfaces.
Fixes Piglit's mix-and-match-tcs-tes test.
v2: Pull the brw_upload_programs code into a brw_upload_tess_programs()
helper function (requested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 239a4bdcd44529e9495d9e68cf5a157421753b3c |
|
18-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Upload HS push constants whenever default tess. levels change.
When using tessellation on OpenGL without a TCS, default values for
gl_TessLevelOuter/gl_TessLevelInner are provided via the API.
Core Mesa will flag ctx->DriverFlags.NewDefaultTessLevels whenever those
values change. We add a corresponding BRW_NEW_DEFAULT_TESS_LEVELS flag
and hook it up to HS push constants (which will be used to upload these
default values to the autogenerated TCS).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f46dbfaed914e0e3463f3a28fc877695cd7e7834 |
|
18-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Consolidate BRW_NEW_TESS_{CTRL,EVAL}_PROGRAM flags.
For several reasons, I don't think it's particularly useful to have
separate flags:
1. Most of the time, tessellation shaders are paired, so both will be
replaced at the same time.
2. The data layout is tightly coupled. Both need to agree on the number
of per-patch slots in the VUE map. Even adding extra TCS outputs
that aren't read by the TES will trigger the need for recompiles.
3. The TCS is optional from an API perspective, but required by the
hardware whenever tessellation is enabled. So, atoms that deal with
the TCS must check brw->tess_eval_program (BRW_NEW_TESS_EVAL_PROGRAM?)
rather than brw->tess_ctrl_program to tell whether tessellation is
enabled.
So, not only is it unlikely to be useful, it's a bit confusing to get
right. Simply using one flag for both simplifies this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8498cb4a45e8ed53a2ee2b35d3c2cbb9963e1756 |
|
15-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Only call brw_upload_tcs/tes_prog when using tessellation.
If there's no evaluation shader, tessellation is disabled. The upload
functions would just bail. Instead, don't bother calling them.
This will simplify the optional-TCS case a bit, as brw_upload_tcs can
assume that we're doing tessellation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 24be658d13b13fdb8a1977208038b4ba43bce4ac |
|
17-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation control shaders.
The TCS is the first tessellation shader stage, and the most
complicated. It has access to each of the control points in the input
patch, and computes a new output patch. There is one logical invocation
per output control point; all invocations run in parallel, and can
communicate by reading and writing output variables.
One of the main responsibilities of the TCS is to write the special
gl_TessLevelOuter[] and gl_TessLevelInner[] output variables which
control how much new geometry the hardware tessellation engine will
produce. Otherwise, it simply writes outputs that are passed along
to the TES.
We run in SIMD4x2 mode, handling two logical invocations per EU thread.
The hardware doesn't properly manage the dispatch mask for us; it always
initializes it to 0xFF. We wrap the whole program in an IF..ENDIF block
to handle an odd number of invocations, essentially falling back to
SIMD4x1 on the last thread.
v2: Update comments (requested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a5038427c3624e559f954124d77304f9ae9b884c |
|
10-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation evaluation shaders
The TES is essentially a post-tessellator VS, which has access to the
entire TCS output patch, and a special gl_TessCoord input. Otherwise,
they're very straightforward.
This patch implements SIMD8 tessellation evaluation shaders for Gen8+.
The tessellator can generate a lot of geometry, so operating in SIMD8
mode (8 vertices per thread) is more efficient than SIMD4x2 mode (only
2 vertices per thread). I have another patch which implements SIMD4x2
mode for older hardware (or via an environment variable override).
We currently handle all inputs via the pull model.
v2: Improve comments (suggested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 86a6eda9bcbf00da550beffcfaba9e20f62ef84a |
|
01-Oct-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation shader push constant support.
Based on a patch by Chris Forbes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c59d1b1fd1ac5dca3b769f42fe0e42a11c10d4b8 |
|
10-Oct-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation shader sampler support.
Based on code by Chris Forbes and Fabian Bieler.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f34c04fda69c6fc91e60633d41108e488af1f88a |
|
01-Oct-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation shader surface support.
This is brw_gs_surface_state.c copy and pasted twice with search and
replace.
brw_binding_table.c code is similarly copy and pasted.
v2: Drop dword_pitch related fields.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 228d5a3f75086e92aaa01619a55d6c8ac7841e0e |
|
08-Dec-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Hook up L3 partitioning state atom.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 353abb294b10aa18bf98a772b380ccbed318c239 |
|
26-Nov-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define and use REG_MASK macro to make masked MMIO writes slightly more readable.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2405b75bc9c6b9fa9583e926bca313ed89911bc7 |
|
03-Sep-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define state flag to signal that the URB size has been altered.
This will make sure that we recalculate the URB layout anytime the URB
size is modified by the L3 partitioning code.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 42ca675cc91af7ee06e2a47daa57d5d65bdd1c80 |
|
09-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add state bits for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 80ea18d1a184606bd3cf6e90296e129f0c7f100e |
|
09-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add backend structures for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7a1735680007a78b0a56107871e4afdc33985604 |
|
30-Sep-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Create new files for HS/DS/TE state upload code.
For now, this just splits the existing code to disable these stages into
separate atoms/files. We can then replace it with real code.
v2: Bump the render atoms in this patch so it compiles (in my branch,
I'd bumped it in an earlier patch). 61 seems to be the minimum
that works, which doesn't match the old value + the number of atoms
I added in this patch, so apparently we had some slop before.
v3: Actually disable the DS unit on Gen8+.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ecb5e0a9861679846a5dbae2a8511b0e624f8f6e |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine BRW_NEW_*_BINDING_TABLE dirty bits.
A while back, we moved to directly emitting the Gen7+ state when
constructing the binding tables. These flags are only used on
Gen4-6, which emit all the binding table pointers at once.
We gain nothing by having separate flags, so combine them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5bfe2835c2e0d3b7b3f11063f6120103f228676b |
|
15-Oct-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Setup pull constant state for compute programs
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7b391142e9da6186221a9eb39977e487f079ef72 |
|
30-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Upload UBO/SSBO surfaces
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 63d7b33f516815ce3f9b3bb1b26a39f1545a4446 |
|
24-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Setup surface binding for gl_NumWorkGroups
This will only be setup when the prog_data uses_num_work_groups
boolean is set.
At this point nothing will set uses_num_work_groups, but soon code
will set it when emitting code for the intrinsic that loads
gl_NumWorkGroups.
We can't emit this surface information earlier at the start of the
DispatchCompute* call because we may not have generated the program
yet. Until we generate the program, we don't know if the
gl_NumWorkGroups variable is accessed.
We also can't emit the surface as part of the brw_cs_state atom,
because we might not need the surface if gl_NumWorkGroups is not used
by the program.
Lastly, we cannot emit the surface later (after state upload) in the
DispatchCompute* call, because it needs to be run before the
brw_cs_state atom is emitted, since it changes the surface state.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| df221f65e26199a74bc259d3f94e70637b843afa |
|
29-Aug-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Simplify handling of VUE map changes.
The old code was disasterously complex - spread across multiple atoms
which may not even run, inspecting the dirty bits to try and decide
whether it was necessary to do checks...storing VS information in
brw_context...extra flagging...
This code tripped me and Carl up very badly when working on the
shader cache code. It's very fragile and hard to maintain.
Now that geometry shaders only depend on their inputs and don't have
to worry about the VS VUE map, we can dramatically simplify this:
just compute the VUE map coming out of the geometry shader stage
in brw_upload_programs. If it changes, flag it. Done.
v2: Also check vue_map.separable.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| dfdeb94a5aedf838fe1f180fd68a7b5b2a3d7e99 |
|
19-Mar-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Implement DriverFlags.NewShaderStorageBuffer
We use the same dirty state for SSBOs and UBOs because they share the
same infrastructure.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b01d0473917ba15de3aa146006bfef5836d10e93 |
|
12-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Emit texture surfaces to enable CS sampling
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2c3007652d5177fe6d018de67be8209a1c3f1b83 |
|
08-Sep-2015 |
Rhys Kidd <rhyskidd@gmail.com> |
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c: In function 'set_3src_control_index':
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c:805:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < ARRAY_SIZE(gen8_3src_control_index_table); i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c: In function 'set_3src_source_index':
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c:839:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < ARRAY_SIZE(gen8_3src_source_index_table); i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_state_dump.c: In function 'dump_sampler_state':
mesa/src/mesa/drivers/dri/i965/brw_state_dump.c:382:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size / 16; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_state_upload.c: In function 'brw_pipeline_state_finished':
mesa/src/mesa/drivers/dri/i965/brw_state_upload.c:801:13: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (i != pipeline) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function 'intel_gen7_hiz_buf_create':
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1544:47: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int level = mt->first_level; level <= mt->last_level; ++level) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function 'intel_gen8_hiz_buf_create':
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1638:44: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int level = mt->first_level; level <= mt->last_level; ++level) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function 'intel_miptree_alloc_hiz':
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1771:44: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int level = mt->first_level; level <= mt->last_level; ++level) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1775:33: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int layer = 0; layer < mt->level[level].depth; ++layer) {
^
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 06ada493fbc22e99867e14f26f1a511b343e3759 |
|
24-Sep-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Setup push constant data for uniforms
brw_upload_cs_push_constants was based on gen6_upload_push_constants.
v2:
* Add FINISHME comments about more efficient ways to push uniforms
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 47f9b07e4cf79a8249c6f9f09148a6a0b4fabacc |
|
20-Jul-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Hook up image state upload.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 190756482e62cb57e2bc8c798181e5f0171726fb |
|
15-Apr-2015 |
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> |
i965: Enable hardware-generated binding tables on render path.
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.
Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.
v2: - Use MOCS in binding table pool alloc for GEN8
- Fix spurious offset when allocating binding table pool entry
and start from zero instead.
v3: - Include GEN8 fix for spurious offset above.
v4: - Fixup wrong packet length in enable/disable hw-binding table
for GEN8 (Ville).
- Don't invoke HW-binding table disable command when we dont
have resource streamer (Chris).
v5: - Reorder the state cache invalidate flush so it happens in-between
enabling hw-generated binding tables and the previous sw-binding
table GPU state (Chris).
v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables().
- Adhere to coding guidelines and make comments more informative.
Cc: kenneth@whitecape.org
Cc: syrjala@sci.fi
Cc: chris@chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9 |
|
30-Apr-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 41b6db225f42a5d81beec1b4455ec7b504e2416d |
|
17-Jun-2015 |
Kevin Rogovin <kevin.rogovin@intel.com> |
i965: Use _mesa_geometric_ functions appropriately
Change references to gl_framebuffer::Width, Height, MaxNumLayers
and Visual::samples to use the _mesa_geometry_ convenience functions
for those places where the geometry of the gl_framebuffer is needed
(in contrast to the geometry of the intersection of the attachments
of the gl_framebuffer).
This patch is to pave the way to enable GL_ARB_framebuffer_no_attachments
on Gen7 and higher in i965.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| eeee212e53feac673ea4ac0345fe493418b187df |
|
27-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Upload atomic buffer state for compute shaders
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 0e0e23ef537c9add672ff322f34e129a07edc55e |
|
22-Apr-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Emit pipeline select when changing pipelines
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5f70b49d4bffaaa073d6cc2a958ec655c201fd10 |
|
12-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Emit state base address
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6b1b484b60890380a5899517a4e91a674be0c4a2 |
|
29-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Upload brw_cs_state
v3:
* Add defines. Misc cleanup suggestions. (Ken)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 932045061b5850368e8a4a5b3e6609eba6ed8d66 |
|
29-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Emit compute shader code and upload programs
v2:
* Don't bother checking for 'gen > 5' (krh)
* Populate sampler data in key (krh)
v3:
* Drop no8 support, and simplify code in several places (Ken)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f002176d5d3b982787e8109a419de929fd77a2b7 |
|
25-Jan-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROG
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6ee4dac1ef7db88b1fd5b27b215fb8baa7bc9c66 |
|
11-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.
Also add code to brw_upload_state to set it when the compute program
changes.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 22ccdf12dd7b5db6eb0c8f2b03c3516f8376fdad |
|
20-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Remove brw->state.dirty
We now use brw->NewGLState and brw->ctx.NewDriverState instead.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7ecf3530d87e88971fd77d35ac23c5383630d35b |
|
20-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Don't use brw->state.dirty.mesa
Now, we only use brw->NewGLState.
I used this bash & sed command in the i965 directory:
for file in *.[ch] *.[ch]pp; do
sed -i -e 's/brw->state\.dirty\.mesa/brw->NewGLState/g' $file
done
Followed by manual changes to brw_state_upload.c.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4e56a9ad46ff7fe85308ce12e21719ff2b476516 |
|
20-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Don't use brw->state.dirty.brw
Now, we only use ctx->NewDriverState.
I used this bash & sed command in the i965 directory:
for file in *.[ch] *.[ch]pp; do
sed -i -e 's/state\.dirty\.brw/ctx.NewDriverState/g' $file
done
Followed by manual changes to brw_state_upload.c.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 20ef23b22721961c93b73700f619179d33747554 |
|
08-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Add compute pipeline with empty atom lists
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a8e39e19032d077a4adf7e451c608f3f139a05e2 |
|
20-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Only upload render programs for render state uploads
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d70f4e6daf4a548eb6debaa2a1646fea21e5fbf3 |
|
08-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Create separate dirty state bits for each pipeline
When clearing the state for a pipeline, we will save changed state for
the other pipelines.
v3:
* Adjust brw_upload_pipeline_state
* Don't pull pipeline state bits into common state bits
* Don't clear pipeline state bits
* Adjust 'clear' phase
* brw_clear_dirty_bits is now brw_render_state_finished
* Move cross-pipeline state flagging to brw_pipeline_state_finished
* Move pipeline clears to brw_pipeline_state_finished
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| db119550725d438c928c50382a2a675b37c24a66 |
|
08-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Support multiple pipelines in brw->num_atoms
brw->num_atoms is converted to an array, but currently just an array
of length 1.
Adds brw_copy_pipeline_atoms which copies the atoms for a pipeline,
and sets brw->num_atoms[p] for pipeline p.
v2:
* Rename brw->atoms[] to render_atoms
* Rename brw_add_pipeline_atoms to brw_copy_pipeline_atoms
* Rename brw_pipeline_first_atom to brw_get_pipeline_atoms
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 736a31d46252187a04a7b5c0119e3ba9be2418cb |
|
18-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Rename brw_clear_dirty_bits to brw_render_state_finished
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2c02baa4870cf08592ac64a576fd6a73262892fb |
|
08-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Rename brw_upload_state to brw_upload_render_state
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9d32d358500733249d3c0264c7458c2e5a65f515 |
|
27-Feb-2015 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/skl: Disable partial resolve in VC
Recomendation [sic] is to set this field to 1 always. Programming it to default
value of 0, may have -ve impact on performance for MSAA WLs.
Another don't suck bit which needs to get set.
The patch wasn't as well tested as I would have liked, primarily I don't have
perf numbers for it, but it's getting to a point where it is in danger of being
lost.
v2: v1 was a mix of two patches. Since 0x7004 is masked, we only need to set it
once at initialization and make sure the pma workaround doesn't set the mask bit
(which it doesn't).
Move LRI to init gpu state (Ken)
Add a comment.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4a6c6c49a7236b1471df143a697195f0c11eb23c |
|
11-Feb-2015 |
Carl Worth <cworth@cworth.org> |
i965: Perform program state upload outside of atom handling
Across the board of the various generations, the intial few atoms in
all of the atom lists are basically the same, (performing uploads for
the various programs). The only difference is that prior to gen6
there's an ff_gs upload in place of the later gs upload.
In this commit, instead of using the atom lists for this program state
upload, we add a new function brw_upload_programs that calls into the
per-stage upload functions which in turn check dirty bits and return
immediately if nothing needs to be done.
This commit is intended to have no functional change. The motivation
is that future code, (such as the shader cache), wants to have a
single function within which to perform various operations before and
after program upload, (with some local variables holding state across
the upload).
It may be worth looking at whether some of the other functionality
currently handled via atoms might also be more cleanly handled in a
similar fashion.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 0b499abb51c80867ad034f2a6d9fcb1e86d021cc |
|
10-Jan-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Do Sandybridge workaround flushes before each primitive.
Sandybridge requires the post-sync non-zero workaround in a ton of
places, and if you ever miss one, the GPU usually hangs.
Currently, we try to track exactly when a workaround flush is
necessary (via the brw->batch.need_workaround_flush flag). This is
tricky to get right, and we've botched it several times in the past.
This patch unconditionally performs the post-sync non-zero flush at the
start of each primitive's state upload (including BLORP). We drop the
needs_workaround_flush flag, and drop all the other callers, as the
flush has already been performed.
We have no data to indicate that simply flushing all the time will
hurt performance, and it has the potential to help stability.
v2: Add post-sync workaround to initial GPU state upload to be extra
cautious (suggested by Chad Versace).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 14aadbe8270845750ce0c62cf511fb5b1bcefd0f |
|
11-Nov-2014 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Store the atoms directly in the context
Instead of having an extra pointer indirection in one of the hottest
loops in the driver.
On Bay Trail-D using Fedora 20 compile flags (-m64 -O2 -mtune=generic
for 64-bit and -m32 -march=i686 -mtune=atom for 32-bit), affects
Gl32Batch7:
32-bit: Difference at 95.0% confidence 1.98515% +/- 0.20814% (n=40)
64-bit: Difference at 95.0% confidence 1.5163% +/- 0.811016% (n=60)
v2 (Ken): Cut size of array from 64 to 57 to save memory.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 916516b251071ad2b64ef6201f95cebec5010af6 |
|
03-Dec-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make INTEL_DEBUG=state ignore state flags with a count of 1.
There are too many state flags to fit in one terminal screen, even with
a very tall terminal. Everything is flagged once, so a value of 1 means
that it hasn't ever happened again, and thus isn't terribly interesting.
Skipping those makes it easier to see the interesting values.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ae45a5a28d8c8a48e7353e37da2ce28a6f2bdef4 |
|
03-Dec-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Compute VS attribute WA bits earlier and check if they changed.
BRW_NEW_VERTICES is flagged every time we draw a primitive. Having
the brw_vs_prog atom depend on BRW_NEW_VERTICES meant that we had to
compute the VS program key and do a program cache lookup for every
single primitive. This is painfully expensive.
The workaround bit computation is almost entirely based on the vertex
attribute arrays (brw->vb.inputs[i]), which are set by brw_merge_inputs.
The only thing it uses the VS program for is to see which VS inputs are
actually read. brw_merge_inputs() happens once per primitive, and can
safely look at the currently bound vertex program, as it doesn't change
in the middle of a draw.
This patch moves the workaround bit computation to brw_merge_inputs(),
right after assigning brw->vb.inputs[i], and stores the previous WA bit
values in the context. If they've actually changed from the last draw
(which is uncommon), we signal that we need a new vertex program,
causing brw_vs_prog to compute a new key.
Improves performance in Gl32Batch7 by 13.6123% +/- 0.739652% (n=166)
on Haswell GT3e. I'm told Baytrail shows similar gains.
v2: Introduce a new BRW_NEW_VS_ATTRIB_WORKAROUNDS dirty bit, rather
than reusing BRW_NEW_VERTEX_PROGRAM (suggested by Chris Forbes).
This prevents unnecessary re-emission of surface/sampler related
atoms (and an SOL atom on Sandybridge).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5f34a18f96e58aff1aca2d2971fca1c91dc6931d |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete brw_state_flags::cache and related code.
It's been merged into brw_state_flags::brw for simplicity and
efficiency.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4f24c168c87e9938f35f5ec135062408148be373 |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).
I put the BRW_NEW_*_PROG_DATA flags at the beginning so that
brw_state_cache.c can still continue using 1 << brw_cache_id.
I also added a comment explaining the difference between
BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM, as it took me a long time
to remember it.
Non-mechanical changes:
- brw_state_cache.c and brw_ff_gs.c now signal .brw, not .cache.
- brw_state_upload.c - INTEL_DEBUG=state changes.
- brw_context.h - bit definition merging.
v2: Correct the explanation of BRW_NEW_*_PROG_DATA to mention
state-based recompiles, and nix the "proper subset" claim,
as it's false. (Caught by Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ce44b2061cf59264b4f22271e8d70cdc826af6de |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.
Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache. Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.
State upload is one of the hottest paths in the driver. For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache). Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom. Broadwell, for example, has
57 state atoms, so this small savings can add up.
CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset). Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.
Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones. This one simply renames things, and was made via:
$ for file in *.[ch]; do
sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
-e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
done
Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw. It will also fix the
alphabetization issues.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e563c33d57f779b34d885c561b731b3eb8eb25b7 |
|
26-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move CACHE_NEW_SAMPLER to BRW_NEW_SAMPLER_STATE_TABLE.
This flag signifies that we've emitted a new SAMPLER_STATE table.
Given that we haven't cached those in years, CACHE_NEW_SAMPLER isn't
a great name. Putting it in the BRW_NEW_* hierarchy would make more
sense; BRW_NEW_SAMPLER_STATE_TABLE better reflects its actual purpose.
When this flag is raised, the pointer to the SAMPLER_STATE table has
changed, so we need to re-issue any packets which point to it (unit
state on Gen4-5, 3DSTATE_SAMPLER_STATE_POINTERS on Gen6, and the
per-stage variants on Gen7+).
Saves 2 * sizeof(void *) bytes per context, as we remove useless
aux_compare/aux_free function pointers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 66ebfad3cd123b6e23e28bdf17cda203b7c99a30 |
|
26-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move CACHE_NEW_*_VP flags to BRW_NEW_*_VP.
We've been streaming these out for ages, so they basically have nothing
to do with brw_state_cache.c.
Saves 6 * sizeof(void *) bytes per context, as we won't have useless
aux_compare/aux_free functions for them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4d67b6ab9aa11428eb998377805c0f94cac099ea |
|
26-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fold the gen7_cc_viewport_state_pointer atom into brw_cc_vp.
These always happen together; the extra atom just means another item to
iterate through, flags to check, and a call through a function pointer.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f421db70ba5b987891458b98ae3b0d0ddc586315 |
|
26-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.
On Gen4-5, unit state is specified as indirect state, rather than
commands. If any unit state changes, we upload it via brw_state_batch
and arrange for 3DSTATE_PIPELINED_POINTERS to be re-emitted, which
updates pointers to all unit state at once.
Since there's only one command and state atom (brw_psp_urb_cs) that
needs to know about this, there's no benefit to having six separate
flags. We can combine CACHE_NEW_*_UNIT into a single flag.
We also haven't cached these in a long time, so it doesn't make sense
to use the "CACHE_NEW_" prefix. Instead, use the "BRW_NEW_" prefix.
This also saves 12 * sizeof(void *) bytes of memory per context, as
we remove useless aux_compare/aux_free functions for each CACHE bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7423cc891b4d6fcc63bfeb79cc1d711ce81122bd |
|
22-Oct-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement the PMA stall fix.
Certain non-promoted depth cases typically incur stalls. In very
specific cases, we can enable a workaround which improves performance.
Improves performance in GLBenchmark 2.7 TRex by 1.17762% +/- 0.448765%
(n=75) at 1280x720 on Broadwell GT3.
Haswell has this feature as well, but we can't currently write registers
from userspace batches (and we'd incur additional software batch
scanning overhead as well), so we haven't enabled it. Broadwell allows
us to write CACHE_MODE_1. Backporters beware: the formula and flushing
incantation differs between Haswell and Broadwell.
v2: Move pma_stall_bits from brw->state to brw itself (requested by
Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c442745981ff307c7d45db4f059728912cda8220 |
|
01-Oct-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Have mesa flag BRW_NEW_TEXTURE_BUFFER when a TexBO binding changes
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| be5df289416f7b4b24811722cea8da9a3fe75ee3 |
|
01-Oct-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add new dirty flag for new TexBOs.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a114f452aee29db752f895edff2b1062518c30a3 |
|
27-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use ~0ull when flagging all BRW_NEW_* dirty flags.
~0 is 0xFFFFFFFF, which only covers the first 32 bits. We need all 64.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5105f9a7ae66001537e8dbf6acf40faf736430e5 |
|
26-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix INTEL_DEBUG=state to work with 64-bit dirty bits.
This will keep INTEL_DEBUG=state working when we add BRW_NEW_* bits
beyond 1 << 31. We missed doing this when widening the driver flags
from uint32_t to uint64_t.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| fbebd5e4a5ccb44ae005a8be18c85ea45c66307f |
|
26-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete CACHE_NEW_BLORP_CONST_COLOR_PROG.
Unused since krh rewrote fast clears to use meta.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 3a4aee34a24a7af7cc2f2a75ca4f5eae533b6f88 |
|
07-Aug-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/gen6/gs: upload ubo and pull constants surfaces.
Uniforms declared as uniform blocks are stored in ubo surfaces and need to
be pulled from the geometry shader program so make sure we upload them first
and do the same for pull constants.
This fixes all piglit tests that use uniform blocks:
bin/shader_runner tests/spec/glsl-1.50/uniform_buffer/gs-*
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 66ec61c49f0e57ebe237de3ee5610c7fda972e9c |
|
30-Jul-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/gen6/gs: Enable texture units and upload sampler state.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 406e04113fb23c514cc63bdab9a46476261d6f10 |
|
02-Jul-2014 |
Samuel Iglesias Gonsalvez <siglesias@igalia.com> |
i965/gs: Reuse gen6 constant push buffers setup code in gen7+.
The code required for gen6 and gen7+ is almost the same, so reuse it.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 96012dfe80121c5d6f5f9c87149aa4ed1da567cb |
|
03-Jul-2014 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/gen6/gs: Setup constant push buffers for gen6 geometry shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| bc383cb55b9d342a77b44328cb4acb5bbdf4a80c |
|
01-Jul-2014 |
Samuel Iglesias Gonsalvez <siglesias@igalia.com> |
i965/gen6/gs: use brw_gs_prog atom instead of brw_ff_gs_prog
This is needed to support user-provided geometry shaders, since the
brw_ff_gs_prog atom in gen6 only takes care of implementing transform feedback
for vertex shaders.
If there is no user-provided geometry shader the implementation falls back to
the original code.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c89306983c07e5a88c0d636267e5ccf263cb4213 |
|
08-Aug-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Calculate start/base_vertex_location after preparing vertices.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 864c463485aafaa2802b18a7427f8b75dc96e3ef |
|
03-Sep-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404
Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
c5bdf9be1eca190417998d548fd140c1eca37a54
Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
6f56e1424d923fd80c84090fbf4506c9eaaffea1
Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
88e3d404dad009d8cff5124cf8acee7daeaceb64
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d035d50e0527ed2a471c5536bf327d7980167b2e |
|
07-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
mesa: Convert NewDriverState to 64-bits
i965 will have more than 32 bits when BRW_STATE_COMPUTE_PROGRAM is added.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8e27a4d2b3e4e74e9a77446bce49607433d86be3 |
|
11-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Modify state upload to allow 2 different sets of state atoms.
The set of state atoms for compute shaders is currently empty; it will
be filled in by future patches.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 373143ed9187c4d4ce1e3c486b5dd0880d18ec8b |
|
11-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Modify dirty bit handling to support 2 pipelines.
The hardware state for compute shaders is almost entirely orthogonal
to the hardware state for 3D rendering. To avoid sending unnecessary
state to the hardware, we'll need to have a separate set of state
atoms for the compute pipeline and the 3D pipeline. That means we
need to maintain two separate sets of dirty bits to determine which
state atoms need to be run.
But the dirty bits are not completely independent; for example, if
BRW_NEW_SURFACES is flagged while doing 3D rendering, then not only do
we need to re-run 3D state atoms that depend on BRW_NEW_SURFACES, but
we also need to re-run compute state atoms that depend on
BRW_NEW_SURFACES. But we'll also need to re-run those state atoms the
next time the compute pipeline is run.
To accomplish this, we record two sets of dirty bits, one for each
pipeline. When bits are dirtied (via SET_DIRTY_BIT() or
SET_DIRTY_ALL()) we set them to the dirty state in both pipelines.
When brw_state_upload() is run, we clear the dirty bits just for the
pipeline that was run.
Note that since the number of pipelines is known at compile time to be
2, the compiler should unroll the loops in SET_DIRTY_BIT() and
SET_DIRTY_ALL().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6f56e1424d923fd80c84090fbf4506c9eaaffea1 |
|
10-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Create a macro for setting all dirty bits.
This will make it easier to extend dirty bit handling to support
compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 88e3d404dad009d8cff5124cf8acee7daeaceb64 |
|
10-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Create a macro for setting a dirty bit.
This will make it easier to extend dirty bit handling to support
compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 60c5f9716c90090f41e0796e93cc60a297fa883b |
|
26-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Track the number of samples in the drawbuffer.
This keeps us from having to emit the nonpipelined state packet on every
FBO binding.
-4.42003% +/- 1.09961% effect on cairo-perf-trace runtime on glamor (n=110).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| feb3d8dacd587683ded706049d696d1904cb87cd |
|
03-Mar-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop intel_check_front_buffer_rendering().
This was being applied in a subset of the places that
intel_prepare_render() was called, to set the same flag that
intel_prepare_render() was setting.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4c4e0ed64bceca57e19c0a9f53aae77d795aa937 |
|
05-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes:
- 48-bit relocations
- Thread count is specified as U/2-1 instead of U-1.
- An extra DWord (DW9) with clip planes, URB entry output length/offsets
- We need to program the "Expected Vertex Count" (VerticesIn)
v2: Set the number of binding table entries so they can be prefetched
(requested by Eric Anholt).
v3: Add a WARN_ONCE for a missing workaround.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a0d4311072267aa5427eb2cacd820e96f114eba0 |
|
04-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update multisampling state for Broadwell.
On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x). It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.
Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN. With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.
Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7. This patch, however, does not implement 2x
and 16x.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2fce1e3c6982ddb53cc60b84af64594c49e9e869 |
|
06-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update BLEND_STATE for Broadwell.
v2: Allow logic ops on all surface types. The UNORM restriction was
lifted with Haswell and I simply hadn't noticed. Also, add missing
BRW_NEW_STATE_BASE_ADDRESS dirty bit. Both caught by Eric Anholt.
v3: Fix swapped per-RT DWord pairs. Eliminates bizarre hacks.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 460e0df3308f896741c884cac427c13a0e187354 |
|
06-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update SF_CLIP_VIEWPORT for Broadwell.
It has additional fields to support clipping to the viewport even if
guardband clipping is enabled.
v2: Update for viewport array changes.
v3: No, seriously, update for viewport array changes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 990aaf87c4740e0225db9f4395541938571727cd |
|
04-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update SOL state for Broadwell.
Unlike on Gen7, we can directly set the offset via the state packet.
We also -have- to: the kernel SOL reset code won't work anymore.
v2: Fix copy and paste mistake in buffer stride setup; drop stale
comment (caught by Eric Anholt). Add a perf_debug for missing
MOCS setup.
v3: Rebase on Paul Berry's changes to CurrentVertexProgram.
v4: Fix SO Write Offset handling. We need to set bits 20 and 21 so the
hardware both loads and saves the offset. There's also a
restriction that 3DSTATE_SO_BUFFER can only be programmed once per
buffer between primitives, so the "reset to zero" code needed
reworking. Fixes most of the transform feedback Piglit tests.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| fd91ab662d64746ceaddc6de9c5d684ac725799f |
|
29-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update the code that disables unused shader stages for Broadwell.
v2: Also disable 3DSTATE_WM_CHROMAKEY for safety.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 3d3c351cfbeb7c948c474213662499d10447ffab |
|
02-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update 3DSTATE_CLIP for Broadwell.
Broadwell's winding order, polygon fill, and viewport Z test fields have
moved to DWord 1 of 3DSTATE_RASTER.
v2: Add a perf_debug for a future optimization and improve commit
message (both suggested by Eric Anholt).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5c0d7dbcb9575bd8126d4d4ef83753664b848d27 |
|
04-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework vertex uploads for Broadwell.
v2: Emit a dummy 3DSTATE_VF_SGVS packet when not needed.
v3: Add WARN_ONCE and perf_debugs requested by Eric Anholt.
v4: Program 3DSTATE_SGVS even in the no-elements case so gl_VertexID
continues working. Fix 3DSTATE_VF_INSTANCING to not use an
element index to access the buffers array. Some ARB_draw_indirect
prep work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 08a471495935665c55f2968e310d6e20193b02f1 |
|
03-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update STATE_BASE_ADDRESS for Broadwell.
v2: Fix missing "change" bit on instruction state base address
(caught by Haihao Xiang).
v3: Add a perf_debug for missing MOCS setup, requested by Eric.
v4: Fix buffer sizes. The value, specified at bit 12 and up, is
actually measured in 4k pages. We need to round up to the
next multiple of 4k.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v3]
Reviewed-by: Matt Turner <mattst88@gmail.com> [v4]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f3c6d6f1e151f6a44a76038dccebe4434038dcb1 |
|
30-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
v2: Fix setting of GEN8_PSX_ATTRIBUTE_ENABLE after rebases.
v3: Add missing binding table entry counts. Don't worry about alpha
testing or alpha to coverage when setting the "Kill Pixel" bit;
those are specified in 3DSTATE_PS_BLEND (caught by Eric Anholt).
Drop unused _NEW_BUFFERS. Tidy comments.
v4: Rebase on Paul Berry's changes to CurrentFragmentProgram.
v5: Re-enable line stippling. It doesn't crash or anything.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v3]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 20d9286f71253004a91acbcf4c257e84ee7df077 |
|
29-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rework 3DSTATE_VS for Broadwell.
v2: Remove incorrect MOCS shifts; rename urb_entry_write_offset to
urb_entry_output_offset to closer match the documentation.
v3: Only emit a non-zero constant buffer read length when active.
v4: Add missing binding table counts (caught by Eric).
v5: Rebase on Paul Berry's changes to CurrentVertexProgram.
v6: Drop bogus SBE read length/offset field code. We were programming
the wrong values, and our 3DSTATE_SBE code overrides any value we
put here anyway with the correct one.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v4]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c96686a6cc0f53965b99a55046d1c55a867f93b3 |
|
30-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add the new 3DSTATE_PS_BLEND state packet.
v2: Only set GEN8_PS_BLEND_HAS_WRITEABLE_RT if color buffer writes are
enabled (caught by Eric Anholt).
v3: Set non-blending flags (writeable RT, alpha test, alpha to coverage)
for integer formats too. +14 Piglits.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 17768bb7b428f367e351bf9bfa480bd0d4e57442 |
|
30-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.
v2: Use stencil->_WriteEnabled instead of setting
GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE twice (suggested by Eric).
v3: Mask stencil->WriteMask and stencil->ValueMask with 0xff. The field
is only 8-bits, so we'd trip the new SET_FIELD assertion when core
Mesa gave us a value like 0xFFFFFFFF. The Gen7 code uses structure
field widths to implicitly do this truncation. Fixes Piglit tests.
v4: Use uint32_t for dw1/dw2, not uint8_t. Worst. Typo. Ever.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 90fff1354b81ab880f1d2c2945c374ad6d8fe44f |
|
01-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update SF, SBE, and RASTER state for Broadwell.
The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.
v2: Set Force URB Read Offset bit. Eventually the URB read offset
should be set in 3DSTATE_VS, but that will require some refactoring.
v3: Rebase on viewport array changes.
v4: Improve comments about URB read length/offset overrides.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2184b519cd2cbb7163d4757afb8d8dc193864c4d |
|
29-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Duplicate gen7_atoms to gen8_atoms.
It's going to diverge significantly. Starting out with a copy allows
future patches to change atoms one by one.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 43e77215b13b2f86e461cd8a62b542fc6854dd1c |
|
22-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7: Use to the correct program when uploading transform feedback state.
Transform feedback may come from either the geometry shader or the
vertex shader, so we can't use
ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] to find the current
post-link transform feedback information. Fortunately we can use
ctx->TransformFeedback.CurrentObject->shader_program.
Cc: 10.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 877128505431adaf817dc8069172ebe4a1cdf5d8 |
|
17-Jan-2014 |
José Fonseca <jfonseca@vmware.com> |
s/Tungsten Graphics/VMware/
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| fb6d9798a0c6eefd512f5b0f19eed34af8f4f257 |
|
11-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Ensure that all necessary state is re-emitted if we run out of aperture.
Prior to this patch, if we ran out of aperture space during
brw_try_draw_prims(), we would rewind the batch buffer pointer
(potentially throwing some state that may have been emitted by
brw_upload_state()), flush the batch, and then try again. However, we
wouldn't reset the dirty bits to the state they had before the call to
brw_upload_state(). As a result, when we tried again, there was a
danger that we wouldn't re-emit all the necessary state. (Note: prior
to the introduction of hardware contexts, this wasn't a problem
because flushing the batch forced all state to be re-emitted).
This patch fixes the problem by leaving the dirty bits set at the end
of brw_upload_state(); we only clear them after we have determined
that we don't need to rewind the batch buffer.
Cc: 10.0 9.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a7bdd4cba8ddcab8dff59ecaaa7efbd436c6c307 |
|
26-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop trailing whitespace from the rest of the driver.
Performed via:
$ for file in *; do sed -i 's/ *//g'; done
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5809512b17d3216045b612d359f97759644945f1 |
|
20-Oct-2013 |
Francisco Jerez <currojerez@riseup.net> |
i965: Implement ABO surface state emission.
The maximum number of atomic buffer objects is somewhat arbitrary, we
can change it in the future easily if it turns out it's not enough...
v2: Add comments with the relevant mesa dirty bits. Fix usage of
BRW_NEW_UNIFORM_BUFFER in the GS ABO state atom.
v3: Update binding table layout diagrams.
v4: Resolve conflicts with the recent dynamic surface index assignment changes.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ddc8decdb211f905bad5c903a38cd3cbbf62418d |
|
28-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move DriverFlag initialization to brw_init_state().
Configuring which dirty flags we want sounds like a job for
brw_init_state().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 220c1e5610faf228e342153e544a3ce9040301a1 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move state setup from brwCreateContext to brw_init_state().
This seems like a better place for it, and helps clean up
brwCreateContext (which is full of a lot of random stuff).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d31b928b93694de0a1408f36acb675485fea5973 |
|
26-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove the brw_context::emit_state_always flag.
This was always set to false, and is only used for debugging.
To enable it, simply change the if (0) block and recompile.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4b0488ef4e3e4562c8e383282e0d2db183dfc5c1 |
|
02-Sep-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Add some missing bits to {mesa,brw,cache}_bits[].
These data structures are used for debug output, so it wasn't hurting
anything that there were missing bits. But it's good to keep things
up to date.
This patch also adds static asserts so that the {brw,cache}_bits[]
arrays are the proper size, so that we don't forget to add to them in
the future. Unfortunately there's no convenient way to assert that
mesa_bits[] is the proper size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 79d9c6b7ffe32c146835d27431a66aaf413836fd |
|
27-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Add a state atom to set up geometry shader state.
v2: Do not attempt to share the code that uploads
3DSTATE_BINDING_TABLE_POINTERS_GS, 3DSTATE_SAMPLER_STATE_POINTERS_GS,
or 3DSTATE_GS with VS.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
v3: Add _NEW_TRANSFORM to gen7_gs_state.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4cc692e355e1f2a15c0d3613aec5dfc3a8bf8935 |
|
25-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Implement support for geometry shader samplers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4ec2604422fc820e35d8de7f1dd91500a270ff5a |
|
22-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: make the state atom for compiling Gen7 geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Use "unsigned" rather than "GLuint".
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 130f0f78bebea8e0666479bfa4e4221245801aaa |
|
25-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Implement support for geometry shader surfaces.
This patch implements pull constant upload, binding table upload, and
surface setup for geometry shaders, by re-using vertex shader code
that was generalized in previous patches.
Based on work by Eric Anholt <eric@anholt.net>.
v2: Update ditry bits for brw_gs_ubo_surfaces to account for commit
77d8fbc (mesa: add & use a new driver flag for UBO updates instead of
_NEW_BUFFER_OBJECT).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 27eecefc670c8b9e75f8520df7c9c7846923bf20 |
|
27-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Allocate push constant space for use by GS.
Previously, we would always use the same push constant allocation
regardless of what shader programs were being run: the available push
constant space was split into 2 equal size partitions, one for the
vertex shader, and one for the fragment shader.
Now that we are adding geometry shader support, we need to do
something smarter. This patch adjusts things so that when a geometry
shader is in use, we split the available push constant space into 3
nearly-equal size partitions instead of 2.
Since the push constant allocation is now affected by GL state, it can
no longer be set up by brw_upload_initial_gpu_state(); instead it must
be set up by a state atom.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 32e16e23377ecbba7783e33428ebb4575b874fe5 |
|
24-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: rename legacy gs structs and functions to ff_gs.
"ff" is for "fixed function". This frees up the name "gs" to refer to
user-defined geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 158dcdc0e2ec99ee527a633bef7b236a73688231 |
|
22-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Add brw->geometry_program.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c6e572275b60f0221691b9b97650b9b41b89a5a2 |
|
27-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split the brw_samplers atom into separate FS/VS stages.
This allows us to avoid uploading the VS sampler state table if only the
fragment program changes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2b7f876a6ad62ad9a93c0df15cb4be1fcc61d380 |
|
26-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make upload_sampler_state_table a virtual function.
This allows us to coalesce the brw_samplers and gen7_samplers atoms.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 637e6a0aa8e5920965a0720673e11622786e86ed |
|
04-Aug-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: add missing BRW_NEW_INTERPOLATION_MAP to state dump
Makes this flag appear in the output for INTEL_DEBUG=state
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9f51499d28f80cbbafa4c1489637e1a6a68d9345 |
|
06-Jul-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965 Gen4/5: Introduce 'interpolation map' alongside the VUE map
The interpolation map (in brw->interpolation_mode) is a new auxiliary
structure alongside the post-GS VUE map, which describes the
interpolation modes for each VUE slot, for use by the clip and SF
stages.
This patch introduces a new state atom to compute the interpolation map,
and adjusts the program keys for the clip and SF stages, but it is not
actually used yet.
[V1-2]: Signed-off-by: Olivier Galibert <galibert at pobox.com>
V3: Updated for vue_map changes, intel -> brw merge, etc. (Chris Forbes)
V4: Compute interpolation map as a new state atom rather than tacking it
on the front of the clip setup
V5: Rework commit message, make interpolation_mode_map a struct.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a9d33dbbdd0d58240e9c15181237a9ac7f99932d |
|
04-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::NewGLState to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5d8186ac1a22afbaa6ed68e0fb67d1f150f798cb |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::hw_ctx to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b00d61151dba9904197ad3b5156b182dcca8a152 |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit the depth/stencil state pointer directly, not via atoms.
See two commits ago for the rationale. This allows us to delete the
whole gen7_cc_state.c file.
This does move these commands before the depth stall flushes from
brw_emit_depthbuffer, which may be a problem. The documentation for
3DSTATE_DEPTH_BUFFER mentions that depth stall flushes are required
before changing any depth/stencil buffer state, but explicitly lists
3DSTATE_DEPTH_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER,
and 3DSTATE_CLEAR_PARAMS. It does not mention this particular packet
(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS).
No observed Piglit regressions on Sandybridge or Ivybridge.
Together with the last two commits, this makes a cairo-gl benchmark
faster by 0.324552% +/- 0.258355% on Ivybridge. No statistically
significant change on Sandybridge. (Thanks to Eric for the numbers.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8ab15bacf4eea44ba4c028fde741467328aa7461 |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit the CC state pointer directly rather than via atoms.
See the previous commit for the rationale.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| da1a896b0f95611e506df46e37a8d2b07e1ddd78 |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit the BLEND_STATE pointer directly rather than via atoms.
Previously, we would:
1. Emit the new indirect state.
2. Flag CACHE_NEW_BLEND_STATE.
3. Rely on later state atoms to notice CACHE_NEW_BLEND_STATE and emit a
pointer to the new indirect state.
This is rather cumbersome: it requires two state atoms instead of one,
and there's a strict ordering dependency in the list. Plus, the code
gets spread across two functions (or even files in the case of Gen7+).
Gen7+ has a packet to update just the blend state pointer, so it makes a
lot of sense to simply emit that right away. Gen6 has a combined packet
which updates blending, the color calculator, and depth/stencil state;
however, each can still be modified independently.
This drops the Gen6 micro-optimization where we tried to only emit one
packet that changed all three states. State updates are pretty cheap.
CACHE_NEW_BLEND_STATE is no longer necessary, so drop it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 3dacb7d40b3a15be1133deaac55b993e8b7809dc |
|
11-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
Revert "i965: Disable unused pipeline stages once at startup on Gen7+."
This reverts commit 6c966ccf07bcaf64fba1a9b699440c30dc96e732.
Apparently causes GPU hangs.
Conflicts:
src/mesa/drivers/dri/i965/brw_state.h
src/mesa/drivers/dri/i965/brw_state_upload.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| fc800f0c60a21bc895d1db55a41fb99c306e1544 |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Allocate push constant L3 space once at startup on Gen7+.
We always allocate the maximum amount of space and never change it, so
it makes sense to do it once. Programming it on startup also lets us
skip re-programming it from BLORP.
This removes a tiny amount of overhead from our drawing loop.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6c966ccf07bcaf64fba1a9b699440c30dc96e732 |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable unused pipeline stages once at startup on Gen7+.
This removes a tiny bit of code from our drawing loop.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d671eb140f05d4974cebf6e6643282a8a7ce45db |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit invariant state once at startup on Gen6+.
Now that we have hardware contexts, we can safely initialize our GPU
state once at startup, rather than needing a state atom with the
BRW_NEW_CONTEXT flag set.
This removes a tiny bit of code from our drawing loop.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 233de8e8d3a78f1ec0eb4d0b16ab35ad19e0fade |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Change return type of check_state() to bool.
The existing code already returned a boolean; this just clarifies that.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 650d5de6eab2e8dc76d33c07c147f1a03888d4b1 |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove unused second parameter of brw_print_dirty_count().
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 64a87f29ce29d3c2e01b7fd79386bf6ace454f62 |
|
17-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Kill software primitive counting entirely.
Now that we have hardware contexts, we don't need to continually
reprogram the GS_SVBI_INDEX registers. They're automatically saved and
restored with the context, so they can just increment over time. We
only need to reset them when starting transform feedback.
There's also no reason to delay until the next drawing operation; we can
just emit the packet immediately. However, this means we must drop the
initialization in brw_invariant_state, as BeginTransformFeedback may
occur before the first drawing in a context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 06cd89a88ccbb1c8bc65348596714b4874c37f86 |
|
21-May-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Fix build failure
meta.h should be included in brw_state_upload.c to get access to
function _mesa_meta_in_progress().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b96f93c4536674d6cce99ffa191d49f0df238f9b |
|
18-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Create a BRW_NEW_META_IN_PROGRESS state flag.
This will allow us to disable statistics during meta operations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 77d8fbcfd4b79fa022c021ed52bda157d72e1ca9 |
|
26-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: add & use a new driver flag for UBO updates instead of _NEW_BUFFER_OBJECT
v2: move the flagging from intel_bufferobj_data to intel_bufferobj_alloc_buffer
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d883d008780b61e9233cb7979cfaa8ef90d7b3b7 |
|
15-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: remove _NEW_PACKUNPACK
No driver checks the flag. Nobody uses it.
I also removed the FLUSH_VERTICES calls, because PixelStorei has no effect
on rendering.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 99bd76d834e0c771274f327e1efe9b089ff273d4 |
|
15-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: convert _NEW_RASTERIZER_DISCARD to a driver flag
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b95cbe5e800e95d888d148e20e6a4e34c8857a9e |
|
15-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa,i965: use NewDriverState to communicate TFB state changes with the driver
_NEW_TRANSFORM_FEEDBACK is not used by core Mesa, so it can be removed.
Instead, an new private flag is added to i965 to serve the same purpose.
If you're new to this:
* When creating a context. you can set private dirty flags
in gl_context::DriverFlags, eg.:
ctx->DriverFlags.NewStateX = BRW_NEW_STATE_X;
* When StateX is changed, core Mesa does:
ctx->NewDriverState |= ctx->DriverFlags.NewStateX;
* When you have to draw, read and clear ctx->NewDriverState.
* Pros: not touching NewState, the driver decides the mapping between
GL states and hw state groups, unlimited number of flags in core Mesa
(still limited number of flags in the driver though)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b29dc25572986ef7fba870cdec8b8d2594a97723 |
|
06-Apr-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove the BRW_NEW_INPUT_DIMENSIONS flag.
When I removed the proj_attrib_mask optimization, I also removed the
last consumer of this bit without realizing it.
Since nobody uses it, there's no point in flagging it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b99ad7f02c5561b179d59418a64c2756c1d77f16 |
|
13-Mar-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove BRW_NEW_WM_INPUT_DIMENSIONS dirty bit.
This was only produced by the brw_wm_input_dimensions atom, which was
removed in the previous commit. So there's no need for the dirty bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d198546bac26256d92d6d4e1f2b0b12206416881 |
|
13-Mar-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete brw_vs_constval.c and the brw_wm_input_sizes atom.
This was only used to compute proj_attrib_mask, which was removed by the
previous commit. That makes this dead code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 463ef47b1672003bdf0737fdc63c4ffa985291f1 |
|
18-Feb-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Store the geometry output VUE map in brw_context.
Currently, the GPU pipeline has one active VUE map in effect at any
given time--the one representing the layout of vertex data coming from
the vertex shader. However, when geometry shaders are added, they
will have their own independent VUE map. Later pipeline stages (clip,
sf, fs) will need to consult the geometry shader VUE map if a geometry
shader is in use, and the vertex shader VUE map otherwise.
This patch adds a new field to brw_context, vue_map_geom_out, which
contains the VUE map that should be used by later pipeline stages. It
also adds a new state flag, BRW_NEW_VUE_MAP_GEOM_OUT, which is
signalled whenever the contents of the VUE map changes.
Since we don't support geometry shaders yet, vue_map_geom_out is
currently set only by the brw_vs_prog state atom.
v2: Don't set vue_map_geom_out in do_vs_prog--that's redundant and
possibly problematic for precompiles. Only set it in
brw_upload_vs_prog. Also, make a copy instead of using a
pointer--this makes it possible to detect when the VUE map hasn't
changed, so we can avoid redundant state uploads.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 3d7c09e8b023e44b2b6ac24fcfa836683da54dd4 |
|
06-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing dirty bits to INTEL_DEBUG=state arrays.
These are more recent additions, and no one remembered to update the
INTEL_DEBUG=state code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b9c5997bb392a53d3787954b93da92ae5929daf8 |
|
06-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Reorganize brw_bits to match the order in brw_context.h.
This reorders the "brw_bits" array in brw_state_upload.c to match the
order of the #defines in brw_context.h.
Otherwise, it's really hard to see if any are missing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b9a66da258f5be17d68d8e8466fb2e2fa6ad76e8 |
|
24-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Remove some stale comments about the brw_constant_buffer atom.
These have been wrong since f428255bde93a452a7cdd48fba21839c99beb6cb
back in 2009!
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9ba6f4733ce6e1b07f8a932590bdbb6cf0702f5d |
|
21-Sep-2012 |
Eric Anholt <eric@anholt.net> |
intel: Mark some file-local code as static.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 815d9d405c69bb07d550ae9f79283dcdc7466e2c |
|
25-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix primitive restart on Haswell.
Haswell moved the "Cut Index Enable" bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0xffffffff.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 993c52d0be5bdf0e30e64ab4c6e1347c5dcb8e3b |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Replace general sw fallback support with a manual check for rendermode.
There were no other cases that set it any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 25d2bf3845e9a6faaef8d808c1255ec57dc71dba |
|
20-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965: Bind UBOs as surfaces like we do for pull constants.
v2: Comment fix, drop extraneous parens (review by Kenneth)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8f37ea414fca66d03f6f4460d6b7730411abb2a2 |
|
18-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Remove TODO comments that are no longer relevant.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5a7942c2f1e3af4daedd92c1ddf21fa6a0e4e752 |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Rename the original binding table to mention that it's the WM now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f9c3ea32cd9b243050ee16f10d6eb9d9c8b3a8ea |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the gen6 GS binding table to a separate table.
Improves VS state change microbenchmark performance by 7.08729% +/-
1.22289% (n=10) on gen7, because we don't upload the 64 dwords of
unused binding table any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 07e00b3040d6da381595c65db5afe597f20d99fc |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the VS binding table to a separate table.
This is a step toward making the samplers/binding tables reflect
sampler uniform mappings instead of embedding those in the programs.
No significant performance difference on the microbenchmark (n=10).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e9cfaed1a50665690534ef3d89c4ad37a3e34bed |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Skip checking if we need a GS program for now.
We always say no. Improves VS state change microbenchmark performance
7.68747% +/- 1.40826% (n=10).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7b36c68ba6899c7f30fd56b7ef07a78b027771ac |
|
26-Jan-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Rewrite the HiZ op
The HiZ op was implemented as a meta-op. This patch reimplements it by
emitting a special HiZ batch. This fixes several known bugs, and likely
a lot of undiscovered ones too.
==== Why the HiZ meta-op needed to die ====
The HiZ op was implemented as a meta-op, which caused lots of trouble. All
other meta-ops occur as a result of some GL call (for example, glClear and
glGenerateMipmap), but the HiZ meta-op was special. It was called in
places that Mesa (in particular, the vbo and swrast modules) did not
expect---and were not prepared for---state changes to occur (for example:
glDraw; glCallList; within glBegin/End blocks; and within
swrast_prepare_render as a result of intel_miptree_map).
In an attempt to work around these unexpected state changes, I added two
hooks in i965:
- A hook for glDraw, located in brw_predraw_resolve_buffers (which is
called in the glDraw path). This hook detected if a predraw resolve
meta-op had occurred, and would hackishly repropagate some GL state
if necessary. This ensured that the meta-op state changes would not
intefere with the vbo module's subsequent execution of glDraw.
- A hook for glBegin, implemented by brwPrepareExecBegin. This hook
resolved all buffers before entering
a glBegin/End block, thus preventing an infinitely recurring call to
vbo_exec_FlushVertices. The vbo module calls vbo_exec_FlushVertices to
flush its vertex queue in response to GL state changes.
Unfortunately, these hooks were not sufficient. The meta-op state changes
still interacted badly with glPopAttrib (as discovered in bug 44927) and
with swrast rendering (as discovered by debugging gen6's swrast fallback
for glBitmap). I expect there are more undiscovered bugs. Rather than play
whack-a-mole in a minefield, the sane approach is to replace the HiZ
meta-op with something safer.
==== How it was killed ====
This patch consists of several logical components:
1. Rewrite the HiZ op by replacing function gen6_resolve_slice with
gen6_hiz_exec and gen7_hiz_exec. The new functions do not call
a meta-op, but instead manually construct and emit a batch to "draw"
the HiZ op's rectangle primitive. The new functions alter no GL
state.
2. Add fields to brw_context::hiz for the new HiZ op.
3. Emit a workaround flush when toggling 3DSTATE_VS.VsFunctionEnable.
4. Kill all dead HiZ code:
- the function gen6_resolve_slice
- the dirty flag BRW_NEW_HIZ
- the dead fields in brw_context::hiz
- the state packet manipulation triggered by the now removed
brw_context::hiz::op
- the meta-op workaround in brw_predraw_resolve_buffers (discussed
above)
- the meta-op workaround brwPrepareExecBegin (discussed above)
Note: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43327
Reported-by: xunx.fang@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44927
Reported-by: chao.a.chen@intel.com
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 28cfa1fa213fe7ba6e5b57e61da663a6c3bf0c13 |
|
11-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't reallocate push constant URB space on new VS programs.
The gen7_urb atom depends on CACHE_NEW_VS_PROG and CACHE_NEW_GS_PROG,
causing gen7_upload_urb() to be called when switching to a new VS
program.
In addition to partitioning the URB space between the VS and GS,
gen7_upload_urb() also allocated space for VS and PS push constants.
Unfortunately, this meant that whenever CACHE_NEW_VS was flagged, we'd
reallocate the space for the PS push constants. According to the BSpec,
after sending 3DSTATE_PUSH_CONSTANT_ALLOC_PS, we must reprogram
3DSTATE_CONSTANT_PS prior to the next 3DPRIMITIVE.
Since our URB allocation for push constants is entirely static, it makes
sense to split it out into its own atom that only subscribes to
BRW_NEW_CONTEXT. This avoids reallocating the space and trashing
constants.
Fixes a rendering artifact in Extreme Tuxracer, where instead of a snow
trail, you'd get a bright red streak (affectionately known as the
"bloody penguin bug").
This also explains why adding VS-related dirty bits to gen7_ps_state
made the problem disappear: it made 3DSTATE_CONSTANT_PS be emitted after
every 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet.
NOTE: This is a candidate for the 7.11 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38868
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6a26005c1e298ec205c339b1b53b3dff6e1fd03c |
|
08-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correct misspellings of "invariant".
$ dict invarient
No definitions found for "invarient", perhaps you mean:
gcide: Invariant
wn: invariant
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8f0baace9854c5a476e348f31a7c45d6366e7532 |
|
10-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Move SOL stage disable to gen7_sol_state.c
We'll be growing more code in here as we actually enable the unit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9cfa8a74ce484d5305b6581608b66b1cc53bc88b |
|
22-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Rename BRW_NEW_WM_SURFACES to BRW_NEW_SURFACES.
The surface states tracked by BRW_NEW_WM_SURFACES are no longer used
for just WM. They are also used for vertex texturing and transform
feedback. To avoid confusion, this patch renames BRW_NEW_WM_SURFACES
to BRW_NEW_SURFACES.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f8328c998b4d68c62ba939165390c2c22c5b5740 |
|
19-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Ensure correct transform feedback indices on new batch.
We don't currently have kernel support for saving GPU registers on a
context switch, so if multiple processes are performing transform
feedback at the same time, their SVBI registers will interfere with
each other. To avoid this situation, we keep a software shadow of the
state of the SVBI 0 register (which is the only register we use), and
re-upload it on every new batch.
The function that updates the shadow state of SVBI 0 is called
brw_update_primitive_count, since it will also be used to update the
counters for the PRIMITIVES_GENERATED and
TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 12498553462c7807034814cf843d86d52c407380 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965/gen6: Manipulate state batches for HiZ meta-ops [v4]
A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.
v2:
Do not special-case the 3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit
for HiZ in gen6_upload_depth_stencil(). The HiZ meta-op sets
ctx->Depth.Test, just read the value from that.
v3:
Add a new dirty flag, BRW_STATE_HIZ, for brw_tracked_state. Flag it
immediately before and after executing the HiZ operation in
gen6_resolve_slice(). Add the flag to the the dirty bits for the
following state packets:
gen6_clip_state
gen6_depth_stencil_state
gen6_sf_state
gen6_wm_state
v4:
- Add BRW_NEW_STATE_HIZ to the dirty bit table in brw_state_upload.c.
This is needed for INTEL_DEBUG=state.
- Align brw dirty bit for gen6_depth_stencil_state.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9ae10e9cbdfce6404a3d86188f2897d8f5d0dcb2 |
|
10-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make Gen6+ renderbuffer surface updates not depend on NEW_COLOR.
NEW_COLOR is only needed on Gen4-5 as brw_update_renderbuffer_surfaces
only uses ctx->Color when intel->gen < 6.
This should reduce unnecessary state updates.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d46dfed9585e7e8a26993e7f67faffe8e2641939 |
|
10-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Reorder state atom lists so all the surface state is together.
Not strictly necessary, but seems like a good idea.
Suggested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 32dfa6e5ef3d1fb703ec34942c55408be22e7ec3 |
|
28-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move and rename "wm sampler" fields to just "sampler".
brw_wm_samplers actually enables any active samplers regardless of what
pipeline stage is using them, so it doesn't make much sense for it to be
WM-specific. So, rename it to "brw_samplers."
To properly generalize it, move sampler_count and sampler_offset from
brw_context::wm to a new brw_context::sampler that can be shared without
looking strange.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 91043c21f9b82054060311aabb617dd6e5058602 |
|
07-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Clean up code for VS pull constant surface creation.
Like for the WM pull constants, we can merge the former prepare/emit
stages into one tracked state atom. Furthermore, the code that used to
handle the binding table was removed in the last commit, leaving some
rather silly looking short functions that can easily be folded in.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e7c29c5de82f6de3d30ed1143d9672dd2e25f0e7 |
|
31-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use a single binding table for all pipeline stages.
Although the hardware supports separate binding tables for each pipeline
stage, we don't see much advantage over a single shared table.
Consider the contents of the binding table:
- Textures (16)
- Draw buffers (8)
- Pull constant buffers (1 for VS, 1 for WM)
OpenGL's texture bindings are global: the same set of textures is
available to all shader targets. So our binding table entries for
textures would be exactly the same in every table.
There are only two pull constant buffers (not many), and although draw
buffers aren't interesting to the VS, it shouldn't hurt to have them in
the table. The hardware supports up to 254 binding table entries, and
we currently only use 26.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4a42bd3931d6298ab9a84b76957ce5d83d289f69 |
|
02-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split brw_wm_surfaces state into renderbuffer and texture atoms.
First, the texturing setup code is relevant for all pipeline stages,
while renderbuffer surfaces are only used by the WM.
Secondly, renderbuffer and texture setup depends on a different set of
dirty bits. There's no reason to walk the array of textures when
changing draw buffers, or vice-versa.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a7d0fa209b444e3c7ad9358f1d31e3f638c20e40 |
|
02-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine the two WM pull constant tracked state atoms.
These were only split for historical reasons: brw_wm_constants used to
be the "prepare" step, while brw_wm_constant_surface was "emit". Now
that both happen at emit time, it makes sense to combine them.
Call the newly combined state atom "brw_wm_pull_constants" to indicate
help distinguish it from the Gen6+ atoms that handle push constants.
Finally, remove the BRW_NEW_WM_CONSTBUF dirty bit entirely now that it's
never flagged nor used.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f3e9ccb3bcd174a0b55cae6f9c56835145558e89 |
|
04-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename gen6_*_constants tracked state atoms to "push_constants".
When reading the "brw_wm_constants" and "gen6_wm_constants" atoms
side-by-side, I initially failed to notice the crucial difference:
the Gen6 atoms are for Push Constants, while brw_wm_constants handles
Pull Constants. (Gen4/5 Push Constants are handled by "brw_curbe.")
Renaming these should clarify the code and save me from constant
confusion over the fact that "gen6_wm_constants" isn't just a newer
version of "brw_wm_constants."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6ba9090ea05e817bd38c1fcc63c53168b16593c7 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).
These fields control how many entries the hardware prefetches into the
state cache, so they only impact performance, not correctness. However,
it's not clear how to use this in a way that's beneficial.
According to the documentation, kernels "using a large number" of
entries may wish to program this to zero to avoid thrashing the cache;
it's unclear how many is too many. Also, Ironlake's WM was missing this
feature entirely---the count had to be zero.
The dirty bit tracking to handle this complicates the surface state
and binding table setup; removing it should simplify things and make
future refactoring easier. So just set 0 for the number of entries
rather than trying to compute and track it.
Appears to have no impact on Nexuiz and OpenArena on Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c3e3903a9089043b280c461a72dab5158dc25d32 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use new vtable entries for surface state updating functions.
Now that we have vtable entries in place, we should use them. This
allows us to drop the cut and pasted Gen7 brw_tracked_state atoms as
they now do exactly the same thing as their brw_wm_surface_state
counterparts.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2649ff4d909fb4f1f1f4c06534170e0d3b4bcc73 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the memcpy()ed atoms array now that everything is emit()-based.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 35c7e8cebeaae67c80254224cda46ee17f6d5868 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Merge brw_validate_state() and brw_upload_state() together.
They were called back-to-back at this point.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 68c813e8eaf46594b1a3c4b0f49ff6edd9d60c75 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove state upload code for calling prepare() now that there are none.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 26cfca825d7cdba753d138172285b5c2adf25c4b |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove some old texturing debug code.
It caught one possible bug I recall in my time working on the driver,
and we haven't been setting it for non-fixed-function since the new FS
backend came along. The bug it caught was likely a confusion about
sampler mappings, which we have tests for these days.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c4aaf85285fc9484e95e9cda89db9cc6923259f4 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move unit state setup to emit() time.
It is only needed in time for brw_psp_urb_cbs(), which is also an emit().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| eaf4d3e6e2493a6e0b20d1205a5fb33ce500c9c2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the validated BO list, now that it's unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6e160d01f2c6667cba89e5fa806f9e4b01ca8ced |
|
19-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove copy and pasted gen7_wm_constants state atom.
Now that this is identical to gen6_wm_constants, just use that instead.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a09c5c2e3053c48a33134cf28229105bfef52e6f |
|
19-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Reissue PIPELINE_POINTERS and BINDING_TABLE_POINTERS on SBA change.
This was a requirement we didn't run into until we started using
STATE_BASE_ADDRESS for instruction data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a98dd64af750fb6dae54b2dc02e0c5a3711156af |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Stop caching the combined depth/stencil region in brw_context.c.
This was going to get in the way of separate depth/stencil (which
wants to know about both, and whether they are the same rb), and also
wasn't a sufficient flag for the fix in the following commit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 3f44043da37bcd0c481ceddf4f878ddb3419b763 |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix SAMPLER_STATE on Ivybridge.
Most of this code copied from brw_wm_sampler_state.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b2b6cc662271d611462532222ef2fcc30042bd0f |
|
28-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update SURFACE_STATE for Ivybridge.
I'm still not happy with the amount of code duplication here, but it
will have to do for now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8c8985bdd714f43a96ce922a7c0284d50aec3d1a |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add depth buffer support on Ivybridge.
This also disables the HiZ and separate stencil buffers. We still need
to implement stencil.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| bc08d4ebb832769aacb4aecaaf1e490f97c53d65 |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Upload sampler state pointers on Ivybridge.
Since we currently only support sampling in the fragment shader, we only
bother to emit the PS variant. In the future we'll need to emit others.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 706dbf85f15d42c320481dabe2a3db0c2cbbebb8 |
|
22-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Upload binding table pointers on Ivybridge.
Ivybridge uses per-stage commands to update binding table pointers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e0e2c045965f7bd4becae3dce8394f8455184e0d |
|
22-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split BRW_NEW_BINDING_TABLE dirty bit into one per stage.
Ivybridge can update each stage's binding table pointer independently,
so we want separate dirty bits. Previous generations can simply
subscribe to all three dirty bits and emit as usual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| bac10b58de69108bdb2cc3358733e2648ab7c5d2 |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Explicitly disable unused pipeline stages on Ivybridge.
This may not be strictly necessary, but seems wise.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6b2010df7d55ad9feacbbcf708a83a66cdf91aaf |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge VS state.
Copied from gen6_vs_state.c; reuses create_vs_constant_bo from there.
The 3DSTATE_VS command is identical but 3DSTATE_CONSTANT_VS is not.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 18402fbf79e96d7afb6b690906a7656f01a92b9d |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge Viewport state setup.
SF and CLIP viewport state has been combined into SF_CLIP_VIEWPORT;
SF_CLIP and CC state pointers can now be uploaded independently.
Some portions of the hardware documentation refer to separate upload
commands for SF and CLIP; these are outdated and incorrect.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 81fd03fe56372c5c702bf257e821cea71ee25448 |
|
28-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge Clip state setup.
Copied from gen6_clip_state.c.
This enables early culling and sets the necessary fields. Otherwise, it
is entirely the same, so I doubt this patch is strictly necessary for a
functional driver.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 24d0ed72c1817b624e3021b12a0987b2c5edd71b |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge CC state setup.
The state itself still seems to be the same; the only change is that
each part (CC, BLEND, DEPTH_STENCIL) can now be uploaded independently.
Thus, we still rely on the code in gen6_cc.c to set up the state.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a924d69b57a82c02f2d4fba3fc0b31bf6a4f744e |
|
03-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge WM/PS state setup.
Copied from gen6_wm_state.c.
The main change from Sandybridge seems to be that 3DSTATE_WM was split
into two separate state packet commands: 3DSTATE_WM and 3DSTATE_PS.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7d608d0c331c101088273655708965fb9f1be56e |
|
05-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge SF/SBE state setup.
Copied from gen6_sf_state.c.
The main change from Sandybridge seems to be that 3DSTATE_SF was split
into two separate state packet commands: 3DSTATE_SF and 3DSTATE_SBE
("setup backend"). The bit-offsets are even the same - only the DWords
numbers have shuffled around a bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8832920c298f4e13ffd5e53feeba509be69edb16 |
|
27-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge URB space partitioning, including push constants.
Currently this always reserves 16kB for push constants, regardless of
how much space is needed, and partitions it evenly betwen the VS and FS.
This is probably not ideal, but is straightforward.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 235fa21a0950150bcb78851e2d0cd2deeb1536f8 |
|
03-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split out tracked state atoms for Ivybridge.
Currently, gen7_atoms is a verbatim copy of gen6_atoms; future commits
will update it to contain gen7-specific state.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a82a43e8d99e1715dd11c9c091b5ab734079b6a6 |
|
23-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Use the dynamic state base address to reduce relocations.
Now that all the dynamic state is streamed through the top of the
batchbuffer, we can cut out many of our relocations to that state by
using the base address.
Improves 3DMMES taiji performance 3.3% +/- 0.4% (n=15).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 855f56ca13c1003396a81da1a110357d624a2101 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Move scissor state to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 5c742ea1ee0cea031cb99651155d0c7521f42b4e |
|
23-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move sampler state to state streaming.
Overall, across this series since the last set of numbers, gen6 3DMMES
taiji performance has dropped 0.8% +/- 0.3% (n=15), probably due to
the increased reissuing of state from some of the state objects that
otherwise never changed, and increased occurrence of the per-batch
overhead as we've increased how much we put in the batch BO without
increasing the batch BO's size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d67c08319fda7d0f2df98d60b64c8cc2f3e06c44 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the CC VP to state streaming.
This is in a way a revert of f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f.
The tiny win that had will be overwhelmed by the win of using the gen6
dynamic state base address.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 32cc0c9d8de343f699e80e7e416ea0d7e3121a42 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Stream the VS push constants.
Improves 3DMMES taiji demo performance by 10.1% +/- 0.9% (n=15).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ea004a3aed89ec02bb5f2356479cd038d41f73c1 |
|
08-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Pack the tracked state atoms into separate arrays for prepare/emit.
Improves performance of a hacked-up scissor-many (to reuse a small set
of scissors instead of blowing out the cache, and then to run 100x
more iterations so it actually took some time) by 3.6% +/- 1.2% (n=10)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8ea6e98c7be6483514769b03ffa6c6f4f7b2e0be |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Micro-optimise check_state
Replace the intermediate tests due to the logical or with the bitwise
or.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| aac120977d1ead319141d48d65c9bba626ec03b8 |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Move repeat-instruction-suppression to batchbuffer core
Move the tracking of the last emitted instructions into the core
batchbuffer routines and take advantage of the shadow batch copy to
avoid extra memory allocations and copies.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f6f04ae29c25ec93ee7e28bd8525e43332262e28 |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing DEFINE_BITS for brw dirty bits.
These are only used for debugging, but should be there.
Found by inspection.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c78b48d80867a3c065eea61a3f6a9751827dd93f |
|
23-Jan-2011 |
Brian Paul <brianp@vmware.com> |
i965: remove _NEW_ACCUM
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 59fa8600d8efa803a4f86a41beaca78f7be41d7c |
|
28-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
Revert "i965: upload multisample state for fragment program change"
This reverts commit de6fd527a545f8344e074312544517d05573fb72.
Revert this workaround as it seems the real trouble is caused by
lineloop, which doesn't require GS convert on sandybridge actually.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| de6fd527a545f8344e074312544517d05573fb72 |
|
23-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: upload multisample state for fragment program change
This makes conformance tests stable on sandybridge D0 to track
multisample state before SF/WM state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ed492e954480326930e83ff62da3f35f0548d774 |
|
07-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix comment about gen6_wm_constants.
This is the push constant buffer, not the pull constants.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 519835de04f39ef8aee61f6ef38e347958d7c52c |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set up the constant buffer on gen6 when it's needed.
This was slightly confused because gen6_wm_constants does the push
constant buffer, while brw_wm_constants does pull constants.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 4b6b0bf24a043035d7ada0c966e01df6327dc529 |
|
28-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix scissor state on sandybridge
Fix incorrect scissor rect struct and missed scissor state pointer
setting for sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 73578ba9c4938db3a23198c3a2ddf843cfc4f700 |
|
10-Sep-2010 |
Eric Anholt <eric@anholt.net> |
mesa: Remove SGI_color_matrix.
Another optional ARB_imaging subset extension.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| cc4925bfe6915010caf03e5aa041ba1fdf0a422f |
|
25-Aug-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary header.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 556f19415a5210aacd52d652b8aae6e58c44e4ed |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up WM push constant setup on gen6.
Fixes glsl-algebraic-add-add-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 527a9a4de218cae89d7faf92788f88ce1f9387b6 |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use intel->gen >= 6 instead of IS_GEN6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 0f59b9a95d21dc79e98bce4ece3eab19e32ca80a |
|
12-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Update gen6 paths for the streaming rework.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 178414eba402f9087ea505e7ef19f1becdd7a36d |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove caching of surface state objects.
It turns out that computing a 56 byte key to look up a 20-byte object
out of a hash table was some sort of a bad idea. Whoops.
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
after:
[ 0] gl firefox-talos-gfx 34.761 34.784 0.17% 5/6
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 73de09f265cb1c66d70fd9eb92021882bfbbbef6 |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Convert the binding table to streamed indirect state.
This slightly reduces reduces cairo-gl firefox-talos-gfx runtime on my
Ironlake:
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 38.236 38.383 0.43% 5/6
after:
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
It turns out the cost of caching these objects and looking them up in
the cache again is greater than the cost of just computing the object
again, particularly when the overhead of having a separate BO to pin
is removed.
(Those that are paying close attention will note that this is a
reversal of the path I was moving the driver in a couple of years ago.
The major thing that has changed is that back then all state was
recomputed when we wrapped the streaming state buffer, including
recompiling our precious programs. Now, we're uncaching just the
objects that are cheap to compute, and retaining caching of expensive
objects)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 118a47623a11a374df371d52ed0294224e6a62dc |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Split constant buffer setup from its surface state/binding state.
This was bothering me when redoing the binding tables.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the CC VP state immediately on state change.
The cache lookup of these two little floats was .12% of total CPU time
on firefox-talos-gfx because we did it any time commonly-changed state
changed. On the other hand, updating the CC VP bo immediately whenver
CC VP state changes is a .07% overhead due to putting a driver hoook
in glEnable().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c791f8a1e532834ae7a517c042e9efe262b62233 |
|
01-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set up the SNB sampler state pointers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 591a996ab6a8ef96a46e88317071330d94c4138f |
|
21-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Move PIPELINE_SELECT to the top of gen6 3d pipeline setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ab8c37fe18e0367e8718774198a0d0086fde0cf9 |
|
21-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Untested Sandybridge WM packets.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 737fac7ba220e4a2d66a8e2100ae0af620c274df |
|
21-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Hook up remaining Sandybridge state packets besides WM.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 70be48dff6bb68c61285641e4d976bfd53e0f00c |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Untested Sandybridge SF setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 1ae0cb5f286bbba10e99c8e3bc1c55d2aeb38b59 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add Sandybridge viewport setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c9065cd61fd43a507ae3100d7c0ab957672cab70 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Enable DRAWING_RECTANGLE emit on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 64e0c586a74553b2941f18feb199d8cddb192102 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add Sandybridge scissor state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a38096aa94ef62dba73792f1680098059b697662 |
|
14-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set the state base address on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ff3997904ab988824e744fdbecde6eb79d9bf40f |
|
04-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Reconnect the index/vertex setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| c9dc6d425e645f2988118ff51cabe167a0cd3971 |
|
04-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set up the SNB URB.
even with vs disabled, still doesn't work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 98f9666f04eed9ae873fdea20c4c4b9db6cead84 |
|
04-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Get vp-tri batchbuffers running (no rendering).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f58fbcf7618bcc6ef9da8e8939100b14ea4d584b |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add untested REJECT_ALL clip state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 520b64ddfb4c2efa742bc2217fef96fdec5eea9b |
|
27-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add untested passthrough GS setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| ba882d7827e5526e99c9d5c453d56c5e029c7476 |
|
16-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add untested Sandybridge passthrough VS setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 7ee590424c974cb10882e9c4664a6024595fc9de |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start adding support for the Sandybridge CC unit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 0b9932ffde3f7228288717302b43aa01df0b5fa0 |
|
03-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Update WM surface state setup for sandybridge's new BLEND_STATE.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 719f2b1d8570aa58b970bd28941221ee6c34af9b |
|
03-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set up sandybridge depthbuffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 554a8f4026459406e7d3ed4e7017a88a57492ddf |
|
03-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Start adding defines and some bits for sandybridge bringup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 26f8fad1456fdc2b352cea9d3b4c32cb5f6ae947 |
|
19-Feb-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
Remove _mesa_memset in favor of plain memset.
This may break the SUNOS4 build, but it's no longer relevant.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8f7dfe302557eca6a48d03abc38bfc32dbe2ad8f |
|
20-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove dead note_fence vtbl hook.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| d1cefabf98ac25832a420b245549492cc3bc6b4d |
|
22-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove obsolete comment about the state atoms.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 8451b29d9628f09b65962385bfbd95cd7f26427f |
|
21-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix several memory leaks on exit.
Bug #25194.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| bcbfda71b03303d3f008a6f3cf8cb7d9667bf8d2 |
|
02-Nov-2009 |
Brian Paul <brianp@vmware.com> |
intel: avoid unnecessary front buffer flushing/updating
Before, if we just called glXMakeCurrent() and didn't render anything we'd
still trigger a flushFrontBuffer() call.
Now only set the intel->front_buffer_dirty field at state validation time
just before we draw something.
NOTE: additional calls to intel_check_front_buffer_rendering() might be
needed if I missed some rendering paths.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e9b17d6477f99838fc7f261ea1b8d47eea12f42f |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: be clear that the Fallback field is a boolean, not a bitfield
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 54107a097904129ff794534542acd09ed152ea2e |
|
24-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Clean up some mess with the batch cache.
Its flagging of extra state that's already flagged by the vtbl new_batch
when appropriate was confusing my tracking down of the OA clear bug.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| af7315e58b8bfe230f7b4c5a8d5b669d67aab9f0 |
|
26-Aug-2009 |
Brian Paul <brianp@vmware.com> |
i965: added texture unit sanity check
Check that all the textures needed by the current fragment program
actually exist and are valid.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 255e5be265133280293bbfd8b2f9b74b2dec50bb |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Avoid re-uploading the index buffer when we don't need to.
No performance difference proven at 95% confidence with my GLSL demo (n=10).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 510c3bd7a1a8f6e350ca7b05ced1f0323098b2eb |
|
07-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove BRW_NEW_INPUT_VARYING
This state flag has been unused since the ffvertex_prog move to core.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 71fb9d62ece0177183efd5bb955d1f3292cb4376 |
|
06-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Split WM constant buffer update from other WM surfaces.
This can avoid re-uploading constant data when it isn't necessary, and is
a step towards not updating other surfaces just because constants change.
It also brings the upload of the constant buffer next to the creation.
This brings openarena performance up another 4%, to 91% of the Mesa 7.4 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 9490d86808300e5819941a40784e272c290e05ee |
|
05-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Disentangle VS constant surface state from WM surface state.
Also, only create VS surface state if there's a VS constant buffer to be
uploaded, and set the contents of the buffer at the same time as creation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f9af97c7a5d81226a87d79baf8fb00231c96398d |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: use two state caches instead of one
The new, second cache will only be used for surface-related items.
Since we can create many surfaces the original, single cache could get
filled quickly. When we cleared it, we had to regenerate shaders, etc.
With two caches, we can avoid doing that.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a071a8d2e72e52e6a8906448b171756c8920ce96 |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: remove unused state atom entries
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| f428255bde93a452a7cdd48fba21839c99beb6cb |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: the brw_constant_buffer state atom is no longer dynamic
No more dynamic atoms so we can simplify the state validation code a little.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| e5681fc176bc43bc6c7804bd1e8d8557cdcab345 |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: add _NEW_PROGRAM_CONSTANTS to mesa_bits[] list
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 14321fcfde9e30d0b9f15aab3c9a057271ae6295 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Delete old metaops code now that there are no remaining consumers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 6d2cf395f401b53da1c2fc4485a297fd975637c6 |
|
07-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove worrisome comment about _NEW_PROGRAM signaling fp change.
Everything now depends on either BRW_NEW_FRAGMENT_PROGRAM or
BRW_NEW_VERTEX_PROGRAM.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 287d719a93728dfd736ecd6ef31c8101f12d58c2 |
|
28-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Remove BRW_WM_LOCK dirty bit, introduced to work around lack of relocs.
This was causing a prepare of wm state at every primitive emit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 3f973de07c035c7307e4129db17ba2baa6ae9acf |
|
27-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Add debug code for dumping how frequently different dirty bits are set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| df94fd17647937975df031dcaa1ac24b2d79ce1b |
|
06-Nov-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Always check vertex program.
Now i965 also uses the vertex program created by Mesa Core, but this vertex program
is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex
program is updated or not. This fixes broken demo cubemap.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix check_aperture calls to cover everything needed for the prim at once.
Previously, since my check_aperture API change, we would check each piece of
state against the batchbuffer individually, but not all the state against the
batchbuffer at once. In addition to not being terribly useful in assuring
success, it probably also increased CPU load by calling check_aperture many
times per primitive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| 0cade4de4f74f6b0e86fb6622e2fc370c73fd840 |
|
20-Oct-2008 |
Eric Anholt <eric@anholt.net> |
intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time. Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| a74b1e149dd567dfa5ddcd69f44e5acfce0d0e0f |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead brw->wrap flag.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|
| b5d59222ccbec9db23b6847737765a4dc0d8c47b |
|
26-Sep-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Remove TNL-to-VP tracking from i965
The i965 driver previously had it's own set of code to convert
fixed-function TNL state to a vertex program. Core Mesa has code to
do this, so there is no reason to duplicate that effort in the driver.
In fact, this duplication leads to bugs when other aspects of the Mesa
infrastructure change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 3628185f566e178a12b493fb89abf52b4b281f99 |
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06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| f75843a517bd188639e6866db2a7b04de3524e16 |
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24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
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24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
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08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| ead798eb103e4cfe801704bc15eb4fe8df078fa8 |
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07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Remove already-disabled PIPE_CONTROL command.
This existed to get the icache flushed. However, GEM handles this for us
now for sure, and we had disabled it prematurely anyway.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
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17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 30c9d96ebf038864485139064c47aeb0d0319598 |
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02-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Fix indentation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 71f53a22d048b4d972c88a2ed49aa3bc4ff76a21 |
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01-Feb-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Don't emit state if fall back to software rendering. fix #14116
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
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29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| dc1608ae9d90a490ce32aa005488e3591a6d8369 |
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09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Replace the always_update dirty flag with BRW_NEW_BATCH.
This allows us to avoid re-emitting some state when validate_state happens
multiple times per batchbuffer. Even though we flush batch per primitive
currently, that may still happen already if the primitive changed (this should
probably be fixed as well).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| d9edd8e90588417e3d549f25132dab2f21445792 |
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09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove drawing rect upload, which is handled (better) by the kernel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 8abffada70fcd62e3c2dcbcdc6d00d258805326b |
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03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert relocations to not be cleared out on buffer submit.
We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
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14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
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08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state_upload.c
|