| f9edc550b2bb76f77e33b6cb122a91f266bc5958 |
|
11-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make a helper for finding an existing shader variant.
We had five copies of the same "walk the cache and look for an
existing shader variant for this program" code. Now we have one
helper function that returns the key.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 99c019e1d41eb72c5ca9e0ae4b263acd6e6c214f |
|
05-Jan-2017 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix textureGather with RG32I/UI on Gen7.
According to the "Gather4 R32G32_FLOAT Bug" internal documentation
page, the R32G32_UINT and R32G32_SINT formats are affected by the
same bug as R32G32_FLOAT. Applying the same workarounds should be
viable - apparently the R32G32_FLOAT_LD format shouldn't corrupt
integer data which is NaN or other sketchy floating point values.
One irritating caveat is that, because it's a FLOAT format, the
alpha channel or any set to SCS_ONE return 0x3f8 (1.0) rather than
integer 1. So we need shader code to whack those channels to 1.
Fixes GL45-CTS.texture_gather.plain-gather-int-cube-rg on Haswell.
v2: Fix swizzle component zeroing (caught by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 6e3f6097c995a74d4ce52f542413b01ff819c203 |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: stop passing gl_shader_program to the precompile and codegen functions
We no longer need it.
While we are at it we mark the vs, gs, and wm codegen functions as static.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 238486884e74888d32d64ea9d934ba6b07e79eb2 |
|
09-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: make use of new is_arb_asm flag
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2a4d169735fd4b76d60963561ac6878c703338f9 |
|
07-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: stop passing gl_shader_program to brw_nir_setup_glsl_uniforms()
We can now just get the data needed from the gl_shader_program_data
pointer in gl_program.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 9ca14f583c2613643671c1d5a8bd2b98745f4c7c |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: stop passing gl_shader_program to brw_assign_common_binding_table_offsets()
We now get everything we need directly from gl_program so there is
no need for this.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 6f76ca300b2945ba8075b022aaec834fbc64af60 |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: pass gl_program to the brw_*_debug_recompile() functions
Rather then passing gl_shader_program.
The only field use was Name which is the same as the Id field in
gl_program.
For wm and vs we also make the functions static and move them before
the codegen functions.
This change reduces the codegen functions dependency on gl_shader_program.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b880281f0bb3f4cd65d38ae13a0db2dba6d7a5ed |
|
08-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get InfoLog and LinkStatus via the shader program data pointer in gl_program
This removes another dependency on gl_shader_program in the codegen
functions.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 6643da6d7f3c3b9bdafb4bb9b01109e482c0b083 |
|
20-Dec-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: update brw_get_shader_time_index() not to take gl_shader_program
This removes another dependency on gl_shader_program in the codegen
functions which will help allow us to use gl_program in the
CurrentProgram array rather than gl_shader_program.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 718a0cf49f88ff456582366db45c31f881561ebf |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: move compiled_once flag to brw_program
This allows us to delete brw_shader and removes the last use of
gl_linked_shader in the codegen paths.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 203c8794a1debc0e45019fe945d1cc55459e6c6f |
|
07-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/glsl/nir/i965: make use of new gl_shader_program_data in gl_shader_program
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ff0253a5ede3acb70852c224f1cf50357781ae81 |
|
17-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable depth writes when depth test is GL_EQUAL.
There's no point in performing depth writes when the depth test
comparison function is set to GL_EQUAL - it would just write out
the same value that's already there (if it is written at all). While
this is harmless from a functional perspective, it hurts performance.
Obviously, writing to memory is not free, but there's another more
subtle impact as well: it can prevent early depth optimizations.
Depth writes aren't supposed to happen for pixels that are killed
by fragment shader discard statements or the alpha test. So, with
depth writes enabled and either of those, the pixel shader must be
invoked to determine whether or not to perform the write. This is
fairly stupid in the EQUAL case - we're running a shader to decide
whether to replace the existing depth value with itself.
By disabling these pointless writes, we allow early depth even with
discards and alpha testing, allowing the hardware to skip the pixel
shader altogether if the depth test fails.
Improves performance of Unigine Valley:
- Skylake GT2: +17.8%
- Broadwell GT3e: +11.5%
- Cherrytrail: +19.4%
Huge thanks to Mark Janes for building frameretrace [1], the performance
analysis tool that helped us find this issue, and to Robert Bragg for
providing us performance metrics on Linux. Mark also spent the time to
analyze Valley performance on Windows vs. Linux and discovered a
discrepancy in early depth test metrics. Once he had isolated a draw
call and drawn attention to the problem, fixing it was pretty simple.
[1] https://github.com/janesma/apitrace/wiki/frameretrace-branch
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ba40c8b03cb5250af771c50ff785bd5ec293e3c1 |
|
27-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get num_images from shader_info rather than gl_linked_shader
This is a step towards freeing gl_linked_shader after linking.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c3b8bf9bc90763c84558199511d062dde18a5d1e |
|
03-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: only try print GLSL IR once when using INTEL_DEBUG to dump ir
Since we started releasing GLSL IR after linking the only time we can
print GLSL IR is during linking. When regenerating variants only NIR
will be available.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 329ae922bdbfd94ddc7c958d4902107f2eb78cab |
|
20-Oct-2016 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Fix alpha-to-coverage and alpha test enabled checks
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 13d0cf57bf069644e4a1d8b2ddc3c5810e84cc67 |
|
18-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: replace brw_fragment_program with brw_program
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3423488d55b9c483fcdb3996eb89b424c1031d24 |
|
19-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/r200/i915/i965: eliminate gl_fragment_program
Here we move OriginUpperLeft and PixelCenterInteger into gl_program
all other fields have been replace by shader_info.
V2: Don't use anonymous union/structs to hold vertex/fragment fields
suggested by Ian.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 17e28a1571b6141368fefc84cc8b0a3b4e52f8ee |
|
19-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965/mesa/st/swrast: set fs shader_info directly and switch to using it
Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 91d61fbf7cb61a44adcaae51ee08ad0dd6b2a03b |
|
20-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: rewrite brw_setup_vue_interpolation()
Here brw_setup_vue_interpolation() is rewritten not to use the InterpQualifier
array in gl_fragment_program which will allow us to remove it.
This change also makes the code which is only used by gen4/5 more self contained
as it now has its own gen5_fragment_program struct rather than storing the map
in brw_context. This means the interpolation map will only get processed once
and will get stored in the in memory cache rather than being processed everytime
the fs changes.
Also by calling this from the fs compile code rather than from the upload code
and using the interpolation assigned there we can get rid of the
BRW_NEW_INTERPOLATION_MAP flag.
It might not seem ideal to add a gen5_fragment_program struct however by the end
of this series we will have gotten rid of all the brw_{shader_stage}_program
structs and replaced them with a generic brw_program struct so there will only
be two program structs which is better than what we have now.
V2: Don't remove BRW_NEW_INTERPOLATION_MAP from dirty_bit_map until the following
patch to fix build error.
V3 - Suggestions by Jason:
- name struct gen4_fragment_program rather than gen5_fragment_program
- don't use enum with memset()
- create interp mode set helper and simplify logic to call it
- add assert when calling function to show prog will never be NULL for
gen4/5 i.e. no Vulkan
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b |
|
13-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
nir/i965/anv/radv/gallium: make shader info a pointer
When restoring something from shader cache we won't have and don't
want to create a nir_shader this change detaches the two.
There are other advantages such as being able to reuse the
shader info populated by GLSL IR.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 7627fbd9b0ca5eb39acb4f0a2ce9b03c90931ebc |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get inputs read from nir info
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 7ef8286487562e1e8678ccc514e4054a682c0c89 |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get outputs written from nir info
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a38c809f6e2080da4100f3b4fe432e0b98950ebf |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: remove remaining tabs in brw_wm.c
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 556335eb9915fc6e00aafa15eaf0265ddc25b131 |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get uses discard from nir info
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ee829cba8ed7941631e214ae8557c5af9fa667b4 |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get uses texture gather from nir info
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 16d5536e55aed2aad0596e9385f1962b4ca5db2b |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->wm.prog_data pointer.
Just say no to:
- brw->wm.base.prog_data = &brw->wm.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_wm_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 017081a3e50d2907045fdd0a4811bb83a025ba07 |
|
14-Apr-2016 |
Carl Worth <cworth@cworth.org> |
i965: make vs and fs key generation helpers available to shader cache
Signed-off-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 94d0e7dc0848a5f70a550f2294e459eab51ace8f |
|
22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
i965: get rid of duplicated values from gen_device_info
Now that we have gen_device_info mutable, we can update its values and drop
all copies we had in brw_context.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| bc24590f0c579a2528fd94eb8d40dd4ce12eba29 |
|
22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
intel/i965: make gen_device_info mutable
Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).
This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 9694b23f66f4c41407289fb7d3ff25321042ef49 |
|
01-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename intelScreen to screen.
"intelScreen" is wordy and also doesn't fit our style guidelines.
"screen" is shorter, which is nice, because we use it fairly often.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 527f37199929932300acc1688d8160e1f3b1d753 |
|
23-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: s/brw_device_info/gen_device_info/
Generated by:
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 08705badfe136e1782e10472104323d861185357 |
|
01-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Allocate space in the binding table for non-coherent FB fetch.
Unfortunately due to the inconsistent meaning of some surface state
structure fields, we cannot re-use the same binding table entries for
sampling from and rendering into the same set of render buffers, so we
need to allocate a separate binding table block specifically for
render target reads if the non-coherent path is in use.
The slight noise is due to the change of
brw_assign_common_binding_table_offsets to return the next available
binding table index rather than void.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 40b23ad57e8da0fd7af21e81ad52d615f9b492ed |
|
22-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/fs: Add brw_wm_prog_key bit specifying whether FB reads should be coherent.
Some of the following changes in this series are specific to the
non-coherent path, so I need some way to tell whether the coherent or
non-coherent path is in use. The flag defaults to the value of the
gl_extensions::MESA_shader_framebuffer_fetch enable so that it can be
overridden easily on hardware that supports both framebuffer fetch
extensions in order to test the non-coherent path, like:
MESA_EXTENSION_OVERRIDE=-GL_EXT_shader_framebuffer_fetch
(Of course trying to force-enable the coherent framebuffer fetch
extension on hardware without native support won't work and lead to
assertion failures).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c8f5bd2c9960a8efe4d923e2a5aab7c169d68769 |
|
23-Aug-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965/fs: Don't consider the stencil output to be a color output.
This would cause gl_FragStencilRef to be counted as a color output
incorrectly during the precompile phase, which leads to unnecessary
recompilation on master and could trigger an assertion failure in
fs_visitor::emit_fb_writes() on my i965-fb-fetch branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8f1ca0ee3ff9e192540325ae42df9577b1ccdf7f |
|
05-Jul-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: make more effective use of SamplersUsed
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| d960284e447df9b1563deef0ce950617decfba63 |
|
13-Jun-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Keep track of the per-thread scratch allocation in brw_stage_state.
This will be used to find out what per-thread slot size a previously
allocated scratch BO was used with in order to fix a hardware race
condition without introducing additional stalls or memory allocations.
Instead of calling brw_get_scratch_bo() manually from the various
codegen functions, call a new helper function that keeps track of the
per-thread scratch size and conditionally allocates a larger scratch
BO.
v2: Handle BO allocation manually instead of relying on
brw_get_scratch_bo (Ken).
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 7398a32c501ed7fedb5619ee7505f9070551d4bd |
|
29-May-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Shrink stage_prog_data param array length
It appears we were over-allocating these arrays.
Previously we would use nir->num_uniforms directly for scalar
programs, and multiply it by 4 for vec4 programs.
Instead we should have been dividing by 4 in both cases to convert
from bytes to a gl_constant_value count. The size of gl_constant_value
is 4 bytes.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 654e950cba55dabd2d9accb60db8e5f4c1495716 |
|
02-May-2016 |
Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com> |
i965: Invoke lowering pass for YUV textures
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 08bc74e69476107e9944932d2fe9dba053b44570 |
|
17-May-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete brw_wm_prog_key::render_to_fbo and drawable_height.
Now that we handle flipping and other gl_FragCoord transformations
via a uniform, these key fields have no users.
This patch actually eliminates the associated recompiles. The Tomb
Raider benchmark's minimum FPS increases from ~1 FPS to a reasonable
number.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 265487aedfabbcfb073f9d6053d1ceb510b78b27 |
|
16-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/fs: Add an allow_spilling flag to brw_compile_fs
This allows us to disable spilling for blorp shaders since blorp state
setup doesn't handle spilling. Without this, blorp fails hard if you run
with INTEL_DEBUG=spill.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b23b099a0bc3ea0c6857b342b6d75f0dbfc334bd |
|
27-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Mark brw const in brw_state_dirty and callers.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c907ca6c8d256f4b8c271bcf0901661ef943ae08 |
|
13-May-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Flip interpolateAtOffset's y offset when necessary.
Fixes 4 dEQP-GLES31.functional.shaders.multisample_interpolation tests:
- interpolate_at_offset.no_qualifiers.default_framebuffer
- interpolate_at_offset.centroid_qualifier.default_framebuffer
- interpolate_at_offset.sample_qualifier.default_framebuffer
- interpolate_at_offset.array_element.default_framebuffer
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 712a980adde0b14eee8b4accd02af9b9740091a2 |
|
10-May-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/fs: Rework the persample shading key/prog_data bits
This commit reworks and simplifies the way we handle persample shading in
the shader key and prog_data. The previous approach had three different
key bits that had slightly different and hard-to-decern meanings while the
new bits are far more clear. This commit changes it to two easily
understood bits that communicate everything we need:
1) key->persample_interp: means that the user has requested persample
interpolation through the API. This is equivalent to having
SAMPLE_SHADING enabled and having MIN_SAMPLE_SHADING_VALUE set high
enough that you actually get multiple per-sample invocations.
2) key->multisample_fbo: means that the shader will be running on an
actual multi-sampled framebuffer.
This commit also adds a new "persample_dispatch" bit to prog_data which
indicates that the shader should be run in persample mode. This way the
state setup code doesn't have to look at the fragment program or GL state
and can just pull that data out of the prog_data.
In theory, this shuffle could mean more recompiles. However, in practice,
we were shoving enough state into the key before that we were probably
hitting a recompile on every per-sample shader anyway.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| cda8c2a9111d4fc45fac6227d895dbb9770dbb84 |
|
18-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/wm: Don't sample lossless compressed as multisampled
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 81407531e0b8d2e6a7f9c39cb44ed6a72dc61e77 |
|
06-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Generalize wm_key->compute_sample_id to wm_key->multisample_fbo.
I'm going to need a key entry meaning "we have a multisample FBO,
and multisampling is enabled" in an upcoming patch. This is basically
wm_key->compute_sample_id, except that it also checks that the SAMPLE_ID
system value is read.
The only use of wm_key->compute_sample_id is in emit_sampleid_setup(),
which is only called when handling the SAMPLE_ID system value. So we
can just eliminate the check and generalize the field.
v2: Also update the Vulkan driver.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| de0a46a040cf1aa83d5b262064b00bd601c09437 |
|
06-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete now dead persample_2x FS program key flag.
This was only used by the old gl_SampleID calculations. The new code
doesn't need to handle 2x specially.
v2: Delete it from the Vulkan driver, too.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b3340cd32acf5935891f19833de0cfc500a93e0b |
|
21-Jan-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement a drirc workaround for broken dual color blending.
OpenGL's dual color blending feature was specified so that an
implementation could support both multiple render targets (MRT) and
dual source blending. Fragment shader outputs specify both "location"
(the render target number) and "index" (either color 0 or 1).
I believe DirectX only has the notion of "location" - if using dual
color blending, location 0 or 1 will specify the operands. If not,
then location means the render target index. The two features can't
be used together.
As such, some applications mistakenly try to use <loc = 0, index = 0>
and <loc = 1, index = 0> in a shader used for dual color blending with
a single render target, rather than the correct <loc = 0, index = 0>
and <loc = 0, index = 1>.
In particular, Unigine Heaven 4.0 and Valley 1.0 suffer from this bug.
Unigine is aware of the problem, and quickly developed a fix, but has
not bothered to change the download link on their website to a working
copy in over a year. People were still using the broken version and
complaining. We tried working around this by disabling dual color
blending, but that apparently hurts performance, and people were once
again unhappy.
On i965, dual source blending is achieved by using different framebuffer
write messages than normal rendering. So, we have to compile different
code for the two cases. We're not being pedantic: we actually have to
know in order to function.
Normally, dual source blending is detectable in the shader: if a shader
has an output with index = 1, then it's meant for blending, not MRT.
With the broken inputs, they're indistinguishable, so we can only tell
by looking at the current GL state.
This patch implements a new drirc workaround:
export dual_color_blend_by_location=true
which makes the i965 driver detect when OpenGL state is configured for
dual source blending, and recompile the fragment shader to use the right
messages. In that case, we allow either location = 1 or index = 1 to
specify the second source for the blending equations.
It also re-enables GL_ARB_blend_func_extended for Unigine.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92233
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b6d4f051a5b2fbead793939cd2e9eb7a83c935ee |
|
02-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: De-duplicate key_debug() function.
This appeared in brw_vs.c and brw_wm.c, should have appeared in
brw_gs.c, and was soon going to have to be in brw_tcs.c and brw_tes.c as
well.
So, instead, move it to a central location (which has to know about both
struct brw_context and perf_debug()).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ecac1aab538d65f0867fd93e23d0d020c1a5d0f1 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Push down inclusion of brw_program.h.
We were including it in headers, which then caused it to be included in
tons of places it wasn't needed.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1a97cac767425b22e56fe698127795bc287bb773 |
|
15-Sep-2015 |
Neil Roberts <neil@linux.intel.com> |
i965/fs: Add a sampler program key for whether the texture is 16x MSAA
When 16x MSAA is used for sampling with texelFetch the compiler needs
to use a different instruction which passes more arguments for the MCS
data. Previously on skl+ it was unconditionally using this new
instruction. However since 16x MSAA is probably going to be pretty
rare, it is probably worthwhile to avoid using this instruction for
the other sample counts. In order to do that this patch adds a new
member to brw_sampler_prog_key_data to track when a sampler refers to
a buffer with 16 samples.
Note that this isn't done for the vec4 backend because it wouldn't
change how many registers it uses.
Acked-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4467344c829f1dccdf74e27bef2c5fda72552be6 |
|
09-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Rename brw_foo_emit to brw_compile_foo
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 67db9072b9fde74277f74f7303366b8bdd3a711e |
|
09-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/fs: Move some of the prog_data setup into brw_wm_emit
This commit moves the common/modern stuff. Some legacy stuff such as
setting use_alt_mode was left because it needs to know whether or not we're
an ARB program.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 22ad44910e993e1acd0b4052722fe786626008b5 |
|
06-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/fs: Rework wm_fs_emit to take a nir_shader and a brw_compiler
This commit removes all dependence on GL state by getting rid of the
brw_context parameter and the GL data structures.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8281a7c5333d9b78aabf9ce3e9cc7077ccca9413 |
|
09-Oct-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Fix unsafe pointer when dumping VS/FS IR
For the VS and FS stages that use ARB_vertex_program or
ARB_fragment_program we don't have a shader program, however,
when debuging is enabled, we call brw_dump_ir like this:
brw_dump_ir("vertex", prog, &vs->base, &vp->program.Base);
where vs will be NULL (since prog is NULL).
As pointed out by Chris, this &vs->base is not really a dereference,
it simply computes a new address that just happens to be 0x0 because
the offset of base in brw_shader is 0. Then brw_dump_ir will see a
NULL pointer and not do anything. This is why this does not crash at
the moment. However, this does not look very safe (it would crash
for any location of base that is not the first in brw_shader), so
patch it to prevent a potential (even if unlikely) problem in the
future.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ee0f0108c8e87b9cfec25bade66670bbc4254139 |
|
07-Oct-2015 |
Kristian Høgsberg Kristensen <krh@bitplanet.net> |
i965: Move brw_get_shader_time_index() call out of emit functions
brw_get_shader_time_index() is all tangled up in brw_context state and
we can't call it from the compiler. Thanks the Jasons recent
refactoring, we can just get the index and pass to the emit functions
instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ba71d581aeb96c4626500eb5b19f3bef2f40d586 |
|
05-Oct-2015 |
Kristian Høgsberg Kristensen <krh@bitplanet.net> |
i965: Move brw_dump_ir() out of brw_*_emit() functions
We move these calls one level up into the codegen functions.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 443d3bf3408984b11f99c1077d167d8331609007 |
|
03-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/wm: Make compute_barycentric_interp_modes take a nir_shader and a devinfo
Now that everything comes in through NIR, we can pick this directly out of
the shader source and don't need to reference the gl_fragment_program.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 30c63571133ed50907ec14172c2f3ef82ee8a34e |
|
01-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move prog_data uniform setup to the codegen level
As of now, uniform setup is more-or-less unified between vec4 and fs and no
longer requires the fs_visitor. This makes uniform setup more of a
language/API thing than a backend compiler thing. This commit moves
setting up the stage_prog_data.params arrays to the same place as we set up
the rest of stage_prog_data.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ea006c4cb5eb2d98d6bfd5a6c32fcae10b636f17 |
|
01-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Move binding table setup to codegen time.
Setting up binding tables really has little to do with the actual process
of turning shaders into instructions; it's more part of setting up
prog_data. This commit moves it out of the visitors and with the rest of
the prog_data setup stuff.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a7e0f755bcb626ed8f8ca773b7d193dd82364513 |
|
01-Oct-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Pull stage_prog_data.nr_params out of the NIR shader
Previously, we had a bunch of code in each stage to figure out how many
slots we needed in stage_prog_data.param. This code was mostly identical
across the stages and had been copied and pasted around. Unfortunately,
this meant that any time you did something special, you had to add code for
it to each of these places. In particular, none of the stages took
subroutines into account; they were working entirely by accident. By
taking this data from the NIR shader, we know the exact number of entries
we need and everything goes a bit smoother.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3948ac19a40663bd00deb84518ac747daa5f401f |
|
30-Sep-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Get rid of prog_data compare functions
They are no longer used.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a548c75e31b4146d55133cb8c57a82117c196584 |
|
05-Sep-2015 |
Kristian Høgsberg Kristensen <krh@bitplanet.net> |
i965: Move perf_debug code to brw_codegen_*_prog()
We're trying to avoid a libdrm dependency in the core compiler, so let's
move the perf_debug code one level up from the brw_*_emit() helpers to
the brw_codegen_*_prog() helpers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 84f2ed2cfdab45aa949aa6affe46cfe2944759c1 |
|
05-Sep-2015 |
Kristian Høgsberg Kristensen <krh@bitplanet.net> |
i965: Move brw_fs_precompile() to brw_wm.c
All other precompile functions live in the brw_<stage>.c files, make fs
follow the convention.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 786e0853bebc3c4ab073bdbb48eec8ba5ea93842 |
|
09-Feb-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.
v2: Store early fragment test mode in brw_wm_prog_data instead of
getting it from core mesa data structures (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 868f1ba0a4e6e3057be5b8c2458db4773cf82034 |
|
13-Jul-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Reserve enough parameter entries for all image uniforms used in the program.
v2: Add CS support.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 87a3e02d9bec689e110f820bba7b125b3e801fdd |
|
21-Jan-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define and initialize image parameter structure.
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size will be used for bounds checking with some image
formats and will be useful for ARB_shader_image_size too. surface_idx
is always used.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
v3: Improve documentation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2b81cefb3fec3c5c17e7ef9f95c9681abfad5386 |
|
11-Jun-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Trivial formatting changes in brw_wm.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b145855df624d0031eb2399503389948ebfcdd26 |
|
15-Jul-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965/fs: Move up prog_data->uses_omask assignment up to brw_codegen_wm_prog().
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 41b6db225f42a5d81beec1b4455ec7b504e2416d |
|
17-Jun-2015 |
Kevin Rogovin <kevin.rogovin@intel.com> |
i965: Use _mesa_geometric_ functions appropriately
Change references to gl_framebuffer::Width, Height, MaxNumLayers
and Visual::samples to use the _mesa_geometry_ convenience functions
for those places where the geometry of the gl_framebuffer is needed
(in contrast to the geometry of the intersection of the attachments
of the gl_framebuffer).
This patch is to pave the way to enable GL_ARB_framebuffer_no_attachments
on Gen7 and higher in i965.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 30c8d8a831edcdbac0bbaccab18cf3b53dbd08c1 |
|
24-Apr-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fill out the rest of brw_debug_recompile_sampler_key().
This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs.
UMS/IMS differences and Sandybridge textureGather workarounds.
Previously, we just flagged them as "Something else".
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a85c4c9b3f75cac9ab133caa91a40eec2e4816ae |
|
16-Apr-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Rename brw_compile to brw_codegen
This name better matches what it's actually used for. The patch was
generated with the following command:
for file in *; do
sed -i -e s/brw_compile/brw_codegen/g $file
done
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b9b66985c3d33fa0db2b49c0e0231aa6d341e183 |
|
20-Mar-2015 |
Carl Worth <cworth@cworth.org> |
i965: Rename do_<stage>_prog to brw_compile_<stage>_prog (and export)
This is in preparation for these functions to be called from other
files.
This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a57672f18deca3060eab129a77cf84f5e420bac8 |
|
20-Mar-2015 |
Carl Worth <cworth@cworth.org> |
i965: Split out per-stage dirty-bit checking into separate functions
The dirty-bit checking from each brw_upload_<stage>_prog function is
split out into its a new brw_<stage>_state_dirty function.
This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4a6c6c49a7236b1471df143a697195f0c11eb23c |
|
11-Feb-2015 |
Carl Worth <cworth@cworth.org> |
i965: Perform program state upload outside of atom handling
Across the board of the various generations, the intial few atoms in
all of the atom lists are basically the same, (performing uploads for
the various programs). The only difference is that prior to gen6
there's an ff_gs upload in place of the later gs upload.
In this commit, instead of using the atom lists for this program state
upload, we add a new function brw_upload_programs that calls into the
per-stage upload functions which in turn check dirty bits and return
immediately if nothing needs to be done.
This commit is intended to have no functional change. The motivation
is that future code, (such as the shader cache), wants to have a
single function within which to perform various operations before and
after program upload, (with some local variables holding state across
the upload).
It may be worth looking at whether some of the other functionality
currently handled via atoms might also be more cleanly handled in a
similar fashion.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 7b6620faf5b2cb327a749eee35ee20ea68a009fe |
|
30-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Store floating point mode choice in brw_stage_prog_data.
We use IEEE mode for GLSL programs, but need to use ALT mode for ARB
programs so that 0^0 == 1. The choice is based entirely on the shader
source language.
Previously, our code to determine which mode we wanted was duplicated
in 8 different places (VS and FS for Gen4-5, Gen6, Gen7, and Gen8).
The ctx->_Shader->CurrentProgram[stage] == NULL check was confusing
as well - we use CurrentProgram (non-derived state), but _Shader
(derived state). It also relies on knowing that ARB programs don't
use gl_shader_program structures today. The compiler already makes
this assumption in a few places, but I'd rather keep that assumption
out of the state upload code.
With this patch, we select the mode at compile time, and store that
choice in prog_data. The state upload code simply uses that decision.
This eliminates a BRW_NEW_*_PROGRAM dependency in the state upload code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8daf3c53c7df806f7302446acb8a58d391f69779 |
|
30-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move PSCDEPTH calculations from draw time to compile time.
The "Pixel Shader Computed Depth Mode" value is entirely based on the
shader program, so we can easily do it at compile time. This avoids the
if+switch on every 3DSTATE_WM (Gen7)/3DSTATE_PS_EXTRA (Gen8+) upload,
and shares a bit more code.
This also simplifies the PMA stall code, making it match the formula
more closely, and drops a BRW_NEW_FRAGMENT_PROGRAM dependency. (Note
that the previous comment was wrong - the code and the documentation
have != PSCDEPTH_OFF, not ==.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2a4f5728ad27bd1605b3604908caa9ad4983e256 |
|
01-Dec-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove "disable_derivative_optimization" driconf option.
This was added in September 2013 when we first implemented the fast
(but lower quality) derivatives. A quick Google search didn't turn
up anyone using or recommending the option, so I suspect no one does.
Applications that want to control the quality of their derivatives can
use the new GL_ARB_derivative_control extension, or use the glHint
mechanism. The driconf option seems superfluous.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 67c498086d0858a94d53ebb6921cfda847250368 |
|
26-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add _CACHE_ in brw_cache_id enum names.
BRW_CACHE_VS_PROG is more easily associated with program caches than
plain BRW_VS_PROG.
While we're at it, rename BRW_WM_PROG to BRW_CACHE_FS_PROG, to move away
from the outdated Windowizer/Masker name.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| bea9b8e306e8424ffacbdfc99ca2fc91f1c9912b |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Alphabetize brw_tracked_state flags and use a consistent style.
Most of the dirty flags were listed in some arbitrary order. Some used
bonus parenthesis. Some put multiple flags on one line, others put one
per line. Some used tabs instead of spaces...but only on some lines.
This patch settles on one flag per line, in alphabetical order, using
spaces instead of tabs, and sheds the unnecessary parentheses.
Sorting was mostly done with vim's visual block feature and !sort,
although I alphabetized short lists by hand; it was pretty manual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 133280120b4bc714bbb7665e383f36ab262c280a |
|
08-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set prog_data->uses_kill if simulating alpha test via discards.
When using MRT on Gen4-5, we have to simulate GL's alpha test feature
by emitting discards in the fragment shader. In this case, it makes
sense to set prog_data->uses_kill, which means the fragment shader may
kill pixels via the discard mechanism.
This saves us from having to look an extra key value in a couple of
places, including in the generator.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 936ca6f3cfb563719d8b51ae000d4f0594aba824 |
|
29-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Add uses_kill to brw_wm_prog_data
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f92fbd554f2e9e702a2bd650c9b2571a3f4f1ab8 |
|
02-Sep-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move curb_read_length/total_scratch to brw_stage_prog_data.
All shader stages have these fields, so it makes sense to store them in
the common base structure, rather than duplicating them in each.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2c50212b14da27de4e3da62488ae4e35c069d84e |
|
11-Aug-2014 |
Neil Roberts <neil@linux.intel.com> |
i965: Store uniform constant values in a gl_constant_value instead of float
The brw_stage_prog_data struct previously contained an array of float pointers
to the values of parameters. These were then copied into a batch buffer to
upload the values using a regular assignment. However the float values were
also being overloaded to store integer values for integer uniforms. This can
break if x87 floating-point registers are used to do the assignment because
the fst instruction tries to fix up invalid float values. If an integer
constant happened to look like an invalid float value then it would get
altered when it was copied into the batch buffer.
This patch changes the pointers to be gl_constant_value instead so that the
assignment should end up copying without any alteration. This also makes it
more obvious that the values being stored here are overloaded for multiple
types.
There are some static asserts where the values are uploaded to ensure that the
size of gl_constant_value is the same as a float.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81150
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1e0da6233be6e5fb0143615d5e3d3642ddb7964f |
|
25-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
util: Move ralloc to a new src/util directory.
For a long time, we've wanted a place to put utility code which isn't
directly tied to Mesa or Gallium internals. This patch creates a new
src/util directory for exactly that purpose, and builds the contents as
libmesautil.la.
ralloc seemed like a good first candidate. These days, it's directly
used by mesa/main, i965, i915, and r300g, so keeping it in src/glsl
didn't make much sense.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
v2 (Jason Ekstrand): More realloc uses and some scons fixes
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 38ffef7840edddada23bac48f669d2070e6f158c |
|
18-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.
We might be able to do this without an extra program key field, but this
is non-invasive and fixes the bug, for now.
This fixes the following Piglit tests on Broadwell:
- ARB_sample_shading/builtin-gl-sample-id 2
- ARB_sample_shading/builtin-gl-sample-position 2
- EXT_framebuffer_multisample/multisample-blit 2 color
- EXT_framebuffer_multisample/multisample-blit 2 color linear
- EXT_framebuffer_multisample/multisample-blit 2 depth
- EXT_framebuffer_multisample/no-color 2 depth combined
- EXT_framebuffer_multisample/no-color 2 depth separate
- EXT_framebuffer_multisample/no-color 2 depth single
- EXT_framebuffer_multisample/no-color 2 depth-computed combined
- EXT_framebuffer_multisample/no-color 2 depth-computed separate
- EXT_framebuffer_multisample/no-color 2 depth-computed single
- EXT_framebuffer_multisample/unaligned-blit 2 color msaa
- EXT_framebuffer_multisample/unaligned-blit 2 depth msaa
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80991
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4cf47c80fc841f1542762a0112117ebeff1058f1 |
|
17-Jul-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing persample_shading field to brw_wm_debug_recompile.
Otherwise, the performance warning for shader recompiles will just say
"something else".
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 221169693bf1dfdaf46dddc1df318cee992237aa |
|
29-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Support GL_CLAMP natively on Broadwell.
The new hardware actually supports this OpenGL 1.x feature natively,
so we can finally drop our shader workarounds.
Not many applications use GL_CLAMP, and most use it unintentionally, but
it's trivial to do right, so we should.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 09b4f260a7ffbfc5a097bf80d5269469adbce647 |
|
14-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Finally kill struct brw_wm_compile (better known as 'c').
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8b994d0f3bb4249fc33a9fe1a6fcad1755fbba20 |
|
14-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Stop copying the program key.
We already have a perfectly good copy of the program key, and nobody is
going to modify it. The only reason we copied it was because the
brw_wm_compile structure embedded the key rather than pointing to it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| cca6dc9f0fd43db366730d67baae1affdca8c6de |
|
14-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Rip struct brw_wm_compile out of the visitors and generators.
Instead, just pass the key and prog_data as separate parameters.
This moves it up a level - one step further toward getting rid of it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2d4ac9b5b825b745257e935dd9b33a2d3507c72a |
|
14-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Plumb a mem_ctx all the way through the FS compile.
'c' is going away, but we still need a memory context that lives
for the duration of the compile.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 81b11bf0934d5387bd3741b6268501df3973a6a7 |
|
14-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Actually free program data on the error path.
We throw away the data generated during compilation on the success path,
so we really ought to on the failure path as well. The caller has no
access to it anyway, so it's purely leaked.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 7e28bd797dbe1721e5d97916f041493d1f30220d |
|
14-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Move total_scratch calculation into fs_visitor::run().
With this one use gone, c->last_scratch is now only used inside
fs_visitor. The rest of the driver uses prog_data->total_scratch.
We already compute similar prog_data fields in fs_visitor, so this
seems reasonable.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c51163b0cf7aff0375b1a5ea4cb3da9d9e164044 |
|
14-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Move perf_debug about register spilling to a more obvious spot.
The if (!allocated_without_spills) block is an obvious spot for this
performance warning message.
In the Vec4 backend, scratch is also used for indirect access of
temporary arrays. The FS backend doesn't implement that yet, but
if it did, this message would be inaccurate, since scratch access
wouldn't necessarily mean spilling. Moving it preemptively fixes that.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ff9c3e8e5a22597c83505479e918981377f8fdf4 |
|
24-Apr-2014 |
Eric Anholt <eric@anholt.net> |
mesa: Replace use of _ReallyEnabled as a boolean with use of _Current.
I'm probably not the only person that has tried to kill _ReallyEnabled.
This does the mechanical part of the work, and cleans _ReallyEnabled from
i965.
I think that using _Current makes texture management clearer: You can't
have multiple targets in use in the same texture image unit at the same
time, because there's just that one pointer.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2ffb50d77b7ae3cdedf0319a0def16732ed39578 |
|
22-Feb-2014 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Remove unused sampler key fields
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c03477050a6f51e601f75cb3c061a3e16a5b7171 |
|
03-May-2013 |
Gregory Hainaut <gregory.hainaut@gmail.com> |
mesa/sso: rename Shader to the pointer _Shader
Basically a sed but shaderapi.c and get.c.
get.c => GL_CURRENT_PROGAM always refer to the "old" UseProgram behavior
shaderapi.c => the old api stil update the Shader object directly
V2: formatting improvement
V3 (idr):
* Rebase fixes after a block of code was moved from ir_to_mesa.cpp to
shaderapi.c.
* Trivial reformatting.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| eef710fc53113a5b3d6bbf7d9a20f63d7add7911 |
|
19-Feb-2014 |
Francisco Jerez <currojerez@riseup.net> |
i965/fs: Use a separate variable to keep track of the last uniform index seen.
Like the VEC4 back-end does. It will make dynamic allocation of the
param_size array easier in a future commit.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ae8b066da5862b4cfc510b3a9a0e1273f9f6edd4 |
|
19-Feb-2014 |
Francisco Jerez <currojerez@riseup.net> |
i965: Move up duplicated fields from stage-specific prog_data to brw_stage_prog_data.
There doesn't seem to be any reason for nr_params, nr_pull_params,
param, and pull_param to be duplicated in the stage-specific
subclasses of brw_stage_prog_data. Moving their definition to the
common base class will allow some code sharing in a future commit, the
removal of brw_vec4_prog_data_compare and brw_*_prog_data_free, and
the simplification of the stage-specific brw_*_prog_data_compare.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2b7bbd89e87c4025cfc5513a078b1e7a10640357 |
|
03-Feb-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add Gen6 gather wa to sampler key
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| dc2f94bc786768329973403248820a2e5249f102 |
|
23-Jan-2014 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Ignore 'centroid' interpolation qualifier in case of persample shading
I missed this change in commit f5cfb4a. It fixes the incorrect
rendering caused in Dolphin Emulator.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73915
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Markus Wick <wickmarkus@web.de>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 5a51a268044ab191262e6f73f135ca95aa59f5df |
|
18-Jan-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Switch from BRW_MAX_TEX_UNIT to the actual limit.
BRW_MAX_TEX_UNIT is about to grow, but only Gen7+ will be able to
support the new larger value. On older platforms, we don't want to
allocate the extra space - it would just be a waste.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a92e5f7cf63d496ad7830b5cea4bbab287c25b8e |
|
06-Jan-2014 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Use sample barycentric coordinates with per sample shading
Current implementation of arb_sample_shading doesn't set 'Barycentric
Interpolation Mode' correctly. We use pixel barycentric coordinates
for per sample shading. Instead we should select perspective sample
or non-perspective sample barycentric coordinates.
It also enables using sample barycentric coordinates in case of a
fragment shader variable declared with 'sample' qualifier.
e.g. sample in vec4 pos;
A piglit test to verify the implementation has been posted on piglit
mailing list for review.
V2: Do not interpolate all the 'in' variables at sample position
if fragment shader uses 'sample' qualifier with one of them.
For example we have a fragment shader:
#version 330
#extension ARB_gpu_shader5: require
sample in vec4 a;
in vec4 b;
main()
{
...
}
Only 'a' should be sampled at sample location, not 'b'.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3313cc269bd428ca96a132d86da5fddc0f27386a |
|
13-Jan-2014 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Add an option to ignore sample qualifier
This will be useful in my next patch which depends on a functionality
of _mesa_get_min_invocations_per_fragment() to ignore the sample
qualifier (prog->IsSample) based on a flag passed to it.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 877128505431adaf817dc8069172ebe4a1cdf5d8 |
|
17-Jan-2014 |
José Fonseca <jfonseca@vmware.com> |
s/Tungsten Graphics/VMware/
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a1ca5802401c384c1eadbf72cf910c65e377600c |
|
29-Nov-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Don't flag gather quirks for Gen8+
My understanding is that Broadwell retains the same SCS mechanism
that Haswell has, so even if the underlying issue with this format
is not fixed, the w/a will be applied in SCS rather than needing
shader code.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 27359b807918503763bf22fc280158999776d0cb |
|
29-Nov-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/Gen7: Include bitfield in the sampler key for CMS layout
We need to emit extra shader code in this case to sample the
MCS surface first; we can't just blindly do this all the time
since IVB will sometimes try to access the MCS surface even if
disabled.
V3: Use actual MSAA layout from the texture's mt, rather
then computing what would have been used based on the format.
This is simpler and less fragile - there's at least one case where
we might want to have a texture's MSAA layout change based on what
the app does (CMS SINT falling back to UMS if the app ever attempts
to render to it with a channel disabled.)
This also obsoletes V2's 1/10 -- compute_msaa_layout can now remain
an implementation detail of the miptree code.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a7bdd4cba8ddcab8dff59ecaaa7efbd436c6c307 |
|
26-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop trailing whitespace from the rest of the driver.
Performed via:
$ for file in *; do sed -i 's/ *//g'; done
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 5720832f23f486e2c869ecb022a6a9ba47ac1619 |
|
15-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix texture swizzling on Broadwell.
Like Haswell, we do this in SURFACE_STATE rather than shader
workarounds.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1080fc610ef20e376c3a54b3cee2be911df9f012 |
|
26-Oct-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Gen4-5: Include alpha func/ref in program key
V2: Better explanation of the rationale for doing this.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| e12bbb503f71b60b9f212e82fdd3ed9aaf3ab318 |
|
25-Oct-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Add FS backend for builtin gl_SampleID
V2:
- Update comments
- Add compute_sample_id variables in brw_wm_prog_key
- Add a special backend instruction to compute sample_id.
V3:
- Make changes to support simd16 mode.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 65d0452bbc14c69ecd2cffdb38f711cfbaab348e |
|
25-Oct-2013 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Add FS backend for builtin gl_SamplePosition
V2:
- Update comments.
- Add compute_pos_offset variable in brw_wm_prog_key.
- Add variable uses_pos_offset in brw_wm_prog_data.
V3:
- Make changes to support simd16 mode.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3c9dc2d31b80fc73bffa1f40a91443a53229c8e2 |
|
02-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make a brw_stage_prog_data for storing the SURF_INDEX information.
It would be nice to be able to pack our binding table so that programs
that use 1 render target don't upload an extra BRW_MAX_DRAW_BUFFERS - 1
binding table entries. To do that, we need the compiled program to have
information on where its surfaces go.
v2: Rename size to size_bytes to be more explicit.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| fbc088ee494bb73c85c13244b052dc7a7490f7f2 |
|
02-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead arguments from prog_data_compare.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2656c6118be066766f16cc7c801e8e7997539c8b |
|
05-Oct-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/ivb: Flag RG32F quirk for texture gather regardless of swizzles
As of ARB_gpu_shader5, textureGather doesn't always read the
post-swizzle RED channel -- so we can't just look at the red swizzle
state.
Theoretically we could only flag the quirk if *some* green swizzle is in
use, but that's probably more trouble than it's worth.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 88f196ab6e2c3efcc75642533aad8bed8c87267a |
|
30-Sep-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/hsw: Apply gather4 RG32F w/a using SCS instead of shader.
The new surface channel select bits allow us to avoid having to
recompile the shader for this workaround.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| cfa3c8a0d326e031c349039b95fc1232d9d623eb |
|
10-Aug-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: w/a for gather4 green RG32F
V4: Only flag quirks if there are any uses of gather in the shader,
to avoid spurious recompiles just because someone happened to use
RG32F.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 848c0e72f36d0e1e460193a2d30b2f631529156f |
|
12-Sep-2013 |
Chia-I Wu <olv@lunarg.com> |
i965: compute DDX in a subspan based only on top row
Consider only the top-left and top-right pixels to approximate DDX in a 2x2
subspan, unless the application requests a more accurate approximation via
GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the
new driconf option disable_derivative_optimization.
This results in a less accurate approximation. However, it improves the
performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0%
confidence) on Haswell. No noticeable image quality difference observed.
The improvement comes from faster sample_d. It seems, on Haswell, some
optimizations are introduced to allow faster sample_d when all pixels in a
subspan have the same derivative. I considered SAMPLE_STATE too, which allows
one to control the quality of sample_d on Haswell. But it gave much worse
image quality without giving better performance comparing to this change.
No piglit quick.tests regression on Haswell (tested with v1).
v2: better guess for precompile program key
Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 875972029eddfd53cb90a8e34e9f27b2afed119f |
|
03-Sep-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: When >64 input components, order them to match prev pipeline stage.
Since the SF/SBE stage is only capable of performing arbitrary
reorderings of 16 varying slots, we can't arrange the fragment shader
inputs in an arbitrary order if there are more than 16 input varying
slots in use. We need to make sure that slots 16-31 match the
corresponding outputs of the previous pipeline stage.
The easiest way to accomplish this is to just make all varying slots
match up with the previous pipeline stage.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4b3c0a797f89830fd5ba0943b061abf4fc38337e |
|
02-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use brw_stage_state for WM data as well.
This gets the VS, GS, and PS all using the same data structure.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c5fe7d063cc886ef1307f8ea58a301debed12fba |
|
10-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Shorten sampler loops in key setup.
Now that we have the number of samplers available, we don't need to
iterate over all 16. This should be particularly helpful for vertex
shaders.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 794de2f3873bcedc78300b3ba69656adc755894c |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::is_<platform> flags to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b15f1fc3c6b3b9dc4422940c412f80e581c9900d |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::perf_debug to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ec995de6fbafe8d6018b91ca130abac760112475 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::stats_wm to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| fe0a8cb30dd53bed0d024b01e2c2b60911a3c526 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::reduced_primitive to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1415a1884c59aff37d0f1a53447ef389dd9f9b39 |
|
01-Jul-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: fix alpha test for MRT
Include src0 alpha in the RT write message when using MRT, so it is used
for the alpha test instead of the normal per-RT alpha value.
Fixes broken rendering in Dota2 under Wine [FDO #62647].
No Piglit regressions on Ivybridge.
V2: reuse (and simplify) existing sample_alpha_to_coverage flag in
the FS key, rather than adding another redundant one.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewd-by: Paul Berry <stereotype441@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62647
NOTE: This is a candidate for the stable branches.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 94ecf913b44d8b966b090723b6ab56cdbe6927e9 |
|
20-Jun-2013 |
Eric Anholt <eric@anholt.net> |
intel: Stop doing special _NEW_STENCIL state flagging on drawbuffers.
2/3 packets depending on Stencil._Enabled already checked for
_NEW_BUFFERS, so just add _NEW_BUFFERS to the remaining one.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 43dac2700ca05bc773b3fd84fab6f8c1f83079d6 |
|
15-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: don't flag _NEW_DEPTH in Begin/EndQuery if driver implements the functions
We don't want to set the flag for Gallium.
I think only swrast needs the flag to be set for occlusion queries.
v2: fix stats_wm updates in i965
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b99ad7f02c5561b179d59418a64c2756c1d77f16 |
|
13-Mar-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove BRW_NEW_WM_INPUT_DIMENSIONS dirty bit.
This was only produced by the brw_wm_input_dimensions atom, which was
removed in the previous commit. So there's no need for the dirty bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 705c8247fa0eb50587b6c19561eb31e4d3a1b876 |
|
13-Mar-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove now dead brw_wm_prog_key::proj_attrib_mask field.
The previous commit removed the last user of this field, so there's no
longer any point in setting it. Removing this should eliminate
state-dependent recompiles, and make the precompile more reliable.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 0a0deb92d9e25067ac4b89cbbd8f8f8f3b4d05db |
|
20-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: Rename vp_outputs_written to input_slots_valid.
With the introduction of geometry shaders, fragment inputs will no
longer come exclusively from the vertex shader; sometimes they come
from the geometry shader. So the name "vp_outputs_written" will
become a misnomer. This patch renames vp_outputs_written to
input_slots_valid, to reflect the true meaning of the bitfield from
the fragment shader's point of view: it indicates which of the
possible input slots contain valid data that was written by the
previous shader stage.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| bf9bfe838eba116cb63dac9a8998da475e1bd98b |
|
17-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Use brw.vue_map_geom_out instead of VS output VUE map where appropriate.
This patch modifies post-GS pipeline stages (transform feedback, clip,
sf, fs) to refer to the VUE map through brw->vue_map_geom_out rather
than brw->vs.prog_data->vue_map. This ensures that when geometry
shader support is added, these pipeline stages will consult the
geometry shader output VUE map when appropriate, rather than the
vertex shader output VUE map.
v2: Fixed some stale "CACHE_NEW_VS_PROG" comments.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8fbc22e880a7a6f34a2fe4e8111b489bdd01919c |
|
17-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Move brw_vs_prog_data::outputs_written into VUE map.
Future patches will allow for there to be separate VUE maps when both
a geometry shader and a vertex shader are in use. When this happens,
we will want to have correspondingly separate outputs_written
bitfields. Moving outputs_written into the VUE map will make this
easy.
For consistency with the terminology used in the VUE map, the bitfield
is renamed to "slots_valid" in the process.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 995bbc22564b22de2ef6aac4e6881fd4c23e3162 |
|
23-Feb-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: Avoid unnecessary recompiles due to POS bit of proj_attrib_mask.
Previous to this patch, when using fixed function fragment shading,
bit VARYING_BIT_POS of brw_wm_prog_key::proj_attrib_mask was being set
differently during precompiles and normal usage. During precompiles
it was being set only if the fragment shader reads from window
position (which it never does), so it was always being set to 0.
During normal usage it was being set if the vertex shader writes to
all 4 components of gl_Position (which it usually does), so it was
usually being set to 1. As a result, we were almost always doing an
extra recompile for the fixed function fragment shader.
The recompile was totally unnecessary, though, because
brw_wm_prog_key::proj_attrib_mask is only consulted for
fs_visitor::emit_general_interpolation(), which isn't used for
VARYING_SLOT_POS.
This patch avoids the unnecessary recompile by always setting bit
VARYING_BIT_POS of brw_wm_prog_key::proj_attrib_mask to 1.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| eed6baf7621fa94e7888f8079b155fc67a08540c |
|
23-Feb-2013 |
Paul Berry <stereotype441@gmail.com> |
Replace gl_frag_attrib enum with gl_varying_slot.
This patch makes the following search-and-replace changes:
gl_frag_attrib -> gl_varying_slot
FRAG_ATTRIB_* -> VARYING_SLOT_*
FRAG_BIT_* -> VARYING_BIT_*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 6bec74bfd98e2f9c090c550c18c02f71ea80d04e |
|
24-Feb-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Change fragment input related bitfields to 64-bit.
This patch updates the bitfields brw_context::wm.input_size_masks,
tracker::size_masks, and brw_wm_prog_key::proj_attrib_mask, all of
which are indexed by gl_frag_attrib, from 32-bit to 64-bit.
This paves the way for supporting geometry shaders, and for merging
the gl_frag_attrib and gl_vert_result enums. The combination of these
two will require at least 55 bits in the bitfields.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 14cec07177f438717cc6fb9252525e16d6b3d8dd |
|
22-Feb-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make perf_debug() output to GL_ARB_debug_output in a debug context.
I tried to ensure that performance in the non-debug case doesn't change
(we still just check one condition up front), and I think the impact is
small enough in the debug context case to warrant including all of it.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 9db2098d18dd28cbb4f9f98ec9e8f9d579608c38 |
|
24-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use GL_RED for DEPTH_TEXTURE_MODE in ES 3.0 for unsized formats.
Khronos has apparently decided that depth textures with sized formats
(allowed with ARB_internalformat_query or ES 3.0) should be treated as
GL_RED, while unsized formats (an existing feature) should be treated
as GL_INTENSITY for compatibility with ES 2.0.
Ian is proposing changes to ARB_internalformat_query which will make
this actually legal and consistent.
A similar problem exists with GL 4.2, but we're going to ignore that
for the time being.
Tested on Ivybridge: no Piglit regressions; fixes 4 es3conform tests:
- depth_texture_fbo
- depth_texture_fbo_clear
- depth_texture_teximage
- depth_texture_texsubimage
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4d09fe938e72b26d814b6b52caee5112cf6f1103 |
|
21-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Move uses of brw_compile from do_wm_prog to brw_wm_fs_emit.
The brw_compile structure is closely tied to the Gen4-7 hardware
encoding. However, do_wm_prog is very generic: it just calls out to
get a compiled program and then uploads it.
This isn't ultimately where we want it, but it's a step in the right
direction: it's now closer to the code generator.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1f74002a9817e000d3f5633dd5eb6adfd1d51ba5 |
|
20-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Move brw_wm_compile::fp to fs_visitor.
Also change it from a brw_fragment_program to a gl_fragment_program,
since that seems to be what everything wants anyway.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2429c9d347fe1c6e98a248c1039041f6a59fd749 |
|
14-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Move brw_wm_payload_setup() to fs_visitor::setup_payload_gen6()
Now that we only have the one backend, there's no real point in keeping
this separate. Moving it should allow some future simplifications.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ce96f6db9028f8488faf778444597b1a3d26433f |
|
20-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Remove brw_wm_compile::computes_depth field.
Everybody determines this by checking if fp's OutputsWritten field
contains the FRAG_RESULT_DEPTH bit. Rather than having payload setup
check this and set the computes_depth flag, we can just do the check in
the only place that actually used it: emit_fb_writes().
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a43b107403ab5f812d68172f799e8cb490e97b95 |
|
08-Nov-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Unify the param pointer allocation for FP/non-FP.
Now that we're using the new backend, we may actually put things into push
constants if you have too many uniform values uploaded. Also, correctly
account for texture rectangle params and drop the old special case for the
0.0/1.0 params from the old backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2fcaf4eae890930fc591df2dc9ad4f6422e8eed0 |
|
06-Nov-2012 |
Eric Anholt <eric@anholt.net> |
i965: Fix slow leak of brw->wm.compile_data->store
We were successfully freeing our compile data at context destroy, but until
then we were allocating a new store every compile without freeing it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56019
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b57d2dfbf64889813d21f7104443db9180da98bb |
|
27-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add "alpha to coverage" to performance debug recompile messages.
This was missing and got labeled "Something else".
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 098acf6c84333edbb7b1228545e4bdb2572ee0cd |
|
18-Sep-2012 |
Eric Anholt <eric@anholt.net> |
i965: Remove the old ARB_fragment_program backend.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 97615b2d8c7c3cea6fd3a43bcb1739a96e2046c4 |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Replace brw_wm_* with dumping code into the fs_visitor.
This makes a giant pile of code newly dead. It also fixes TXB on newer
chipsets, which has been totally broken (I now have a piglit test for that).
It passes the same set of Ian's ARB_fragment_program tests. It also improves
high-settings ETQW performance by 3.2 +/- 1.9% (n=3), thanks to better
optimization and having 8-wide along with 16-wide shaders.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=24355
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 6d6aef79742ece3bb570ae44e6c13791aae15e01 |
|
21-Sep-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Do texture swizzling in hardware on Haswell.
Haswell supports EXT_texture_swizzle and legacy DEPTH_TEXTURE_MODE
swizzling by setting SURFACE_STATE entries. This means we don't have to
bake the swizzle settings into the shader code by emitting MOV
instructions, and thus don't have to recompile shaders whenever the
swizzles change.
Unfortunately, we can't handle GL_ALPHA this way: unlike all the others,
which store the comparison result in the .r channel (and possibly others
as well), GL_ALPHA puts it in the .a channel. The GLSL 1.30+ style
functions which return a float always simply return the .r channel,
which would be zero if we handled this as a surface override. In this
case, fall back to doing it the old way. DEPTH_TEXTURE_MODE = GL_ALPHA
isn't an interesting performance path anyway.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b5a042a657fed45264406cbd0d67fa6217a410a1 |
|
07-Sep-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Refactor texture swizzle generation into a helper.
It's going to be reused in a second place soon.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f144b78dfbb97a70121be6f20d10bad8111267e3 |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make the param pointer arrays for the WM dynamically sized.
Saves 26.5MB of wasted memory allocation in the l4d2 demo.
v2: Rebase on compare func change, fix comments.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 99596cba7828af67bfcd0f2dafcb44b65d39d239 |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add functions for comparing two brw_wm/vs_prog_data structs.
Currently, this just avoids comparing all unused parts of param[] and
pull_param[], but it's a step toward getting rid of those giant statically
sized arrays.
v2: Actually use the new function instead of just looking at its
address. This required changing the args to const pointers.
(review by Kenneth)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f8a8f069ee2dae35470c6e2a681e5e110044e6fe |
|
29-Aug-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/msaa: flag _NEW_MULTISAMPLE in the brw_tracked_state
This is required to get the program recompiled when SampleAlphaToCoverage
is enabled.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f3d0daf7ea7e42ff9ce11e8bd6fba1059a2406e8 |
|
26-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Index sampler program key data by linker-assigned index.
Now that most things are based on the linker-assigned index, it makes
sense to convert the arrays in the VS/WM program key as well. It seems
silly to leave them indexed by texture unit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ab17762c70852ca8fc400d7b5c6696d412ff2afe |
|
14-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Only set proj_attrib_mask for fixed function.
brw_wm_prog_key's proj_attrib_mask field is designed to enable an
optimization for fixed-function programs, letting us avoid projecting
attributes where the divisor is 1.0.
However, for shaders, this is not useful, and is pretty much impossible
to guess when building the FS precompile key. Turning it off for
shaders should allow the precompile to work and not lose much.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 6cc14c2493bb6957f2581671020809e90a8d8643 |
|
26-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't set stats_wm in the WM program key on Gen6+.
It's only needed for Gen4/5 IZ lookup workarounds.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b6b1fc1261e86e2aa03ae8d2dd587c88a207354f |
|
14-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't set vp_outputs_written in the WM program key on Gen6+.
It's only used by on pre-Sandybridge hardware.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 98211d5af7efa26c350f6191457ab2564847abde |
|
16-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Fix INTEL_DEBUG=perf program key printing.
When dumping differences in program keys, it printed messages of the
format:
[Name of thing that changed] [new]->[old]
This was terribly confusing: the right arrow implies "the value changed
from this to that", when in fact the message conveyed the opposite.
Except that some of the time, it didn't, since we accidentally swapped
the arguments to brw_debug_recompile_sampler_key. With two swaps, it
would often come out in the expected format.
This patch fixes it to properly print:
[Name of thing that changed] [old]->[new]
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 76d1301e8e8e50dc962601a9977bc52148798349 |
|
14-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set SWIZZLE_NOOP for unused texture units in the program keys.
Previously, we left the swizzle key field as zero for unused texture
units. The precompile sets all of them to SWIZZLE_NOOP, which meant
that we mismatched almost every time.
Since either works equally well, change it to SWIZZLE_NOOP to match
the precompiles.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| e592f7df0361eb8b5c75944f0151c4e6b3f839dd |
|
02-Aug-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/msaa: Add sample-alpha-to-coverage support for multiple render targets
Render Target Write message should include source zero alpha value when
sample-alpha-to-coverage is enabled for an FBO with multiple render targets.
Source zero alpha value is used as fragment coverage for all the render
targets.
This patch makes piglit tests draw-buffers-alpha-to-coverage and
alpha-to-coverage-no-draw-buffer-zero to pass on Sandybridge. No
regressions are observed with piglit all.tests.
V2: Revert all the changes made in emit_color_write() function to
include src0 alpha for targets > 0. Now handling this case in a if
block.
V3: Correctly calculate the instruction length for buffer zero.
Properly handle the case of dual_src_blend when alpha-to-coverage
is enabled.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| fc3b7c9b56701f23b002543de33a8d8c43f9bdc2 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add performance debug for shader recompiles.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4cfb9e30000eea9cb1f316ace9347083b619cdb0 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add performance debug for register spilling.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c37efbfe4c415b6fd2d4f968220d7c9b62f11ecf |
|
12-Jun-2012 |
Pauli Nieminen <pauli.nieminen@linux.intel.com> |
mesa: Move DepthMode to texture object
GL_DEPTH_TEXTURE_MODE isn't meant to be part of sampler state based on
compatibility profile specifications.
OpenGL specification 4.1 compatibility 20100725 3.9.2:
"... The values accepted in the pname parameter
are TEXTURE_WRAP_S, TEXTURE_WRAP_T, TEXTURE_WRAP_R, TEXTURE_MIN_-
FILTER, TEXTURE_MAG_FILTER, TEXTURE_BORDER_COLOR, TEXTURE_MIN_-
LOD, TEXTURE_MAX_LOD, TEXTURE_LOD_BIAS, TEXTURE_COMPARE_MODE, and
TEXTURE_COMPARE_FUNC. Texture state listed in table 6.25 but not listed here and
in the sampler state in table 6.26 is not part of the sampler state, and remains in the
texture object."
The list of states is in Table 6.24 "Textures (state per texture
object)" instead of 6.25 mentioned in the specification text.
Same can be found from 3.3 compatibility specification.
Signed-off-by: Pauli Nieminen <pauli.nieminen@linux.intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| d08fdacd58dfa6b1926e9df4707dd9e8dd5370c5 |
|
20-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Avoid unnecessary recompiles for shaders that don't use dFdy().
The i965 back-end needs to compile dFdy() differently for FBOs and
window system framebuffers, because Y coordinates are flipped between
the two (see commit 82d2596: i965: Compute dFdy() correctly for FBOs).
This patch avoids unnecessarily recompiling shaders that don't use
dFdy(), by only setting render_to_fbo in the wm program key if the
shader actually uses dFdy().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| fe911c1d433c6fddc8f1e1226286b26d635d6ad4 |
|
16-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move loop over texture units into brw_populate_sampler_prog_key.
The whole reason I avoided this was because it might operate on a
brw_vertex_program or a brw_fragment_program. However, that isn't a
problem: all we need is the gl_program base type.
This avoids awkwardly passing the loop counter 'i' as a parameter,
simplifies both callers, and also plumbs prog in place for future use.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 86e401b771ce4a6f9a728f76c5061c339f012d0a |
|
12-Jul-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Always emit alpha when nr_color_buffers == 0.
If alpha-testing is enabled, we need to send alpha down the pipeline
even if nr_color_buffers == 0. However, tracking whether alpha-testing
is enabled in the WM program key is expensive: it causes us to compile
multiple specializations of the same shader, using program cache space.
This patch removes the check for alpha-testing, and simply emits alpha
whenever nr_color_buffers == 0. We believe this will also be necessary
for alpha-to-coverage, and it should add minimal overhead to an uncommon
case. Saving the recompiles should more than make up the difference.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b546aebae922214dced54c75e6f64830aabd5d1c |
|
10-Jul-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete previous workaround for textureGrad with shadow samplers.
It had many problems:
- The shadow comparison was done post-filtering.
- It required state-dependent recompiles whenever the comparison
function changed.
- It didn't even work: many cases hit assertion failures.
- I never implemented it for the VS.
The new lowering pass which converts textureGrad to textureLod by
computing the LOD value works much better.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8313f44409ceb733e9f8835926364164237b3111 |
|
21-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Fix centroid interpolation of unlit pixels.
From the Ivy Bridge PRM, Vol 2 Part 1 p280-281 (3DSTATE_WM:
Barycentric Interpolation Mode):
"Errata: When Centroid Barycentric mode is required, HW may
produce incorrect interpolation results when a 2X2 pixels have
unlit pixels."
To work around this problem, after doing centroid interpolation, we
replace the centroid-interpolated values for unlit pixels with
non-centroid-interpolated values (which are interpolated at pixel
centers). This produces correct rendering at the expense of a slight
increase in shader execution time.
I've conditioned the workaround with a runtime flag
(brw->needs_unlit_centroid_workaround) in the hopes that we won't need
it in future chip generations.
Fixes piglit tests "EXT_framebuffer_multisample/interpolation {2,4}
{centroid-deriv,centroid-deriv-disabled}". All MSAA interpolation
tests pass now.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| d1056541e239dfcee0ad6af2fd2d9fab37dbf025 |
|
18-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add backend support for centroid interpolation.
This patch causes the fragment shader to be configured correctly (and
the correct code to be generated) for centroid interpolation. This
required two changes: brw_compute_barycentric_interp_modes() needs to
determine when centroid barycentric coordinates need to be included in
the pixel shader thread payload, and
fs_visitor::emit_general_interpolation() needs to interpolate using
the correct set of barycentric coordinates.
Fixes piglit tests "EXT_framebuffer_multisample/interpolation {2,4}
centroid-edges" on i965.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 82d25963a838cfebdeb9b080169979329ee850ea |
|
20-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Compute dFdy() correctly for FBOs.
On i965, dFdx() and dFdy() are computed by taking advantage of the
fact that each consecutive set of 4 pixels dispatched to the fragment
shader always constitutes a contiguous 2x2 block of pixels in a fixed
arrangement known as a "sub-span". So we calculate dFdx() by taking
the difference between the values computed for the left and right
halves of the sub-span, and we calculate dFdy() by taking the
difference between the values computed for the top and bottom halves
of the sub-span.
However, there's a subtlety when FBOs are in use: since FBOs use a
coordinate system where the origin is at the upper left, and window
system framebuffers use a coordinate system where the origin is at the
lower left, the computation of dFdy() needs to be negated for FBOs.
This patch modifies the fragment shader back-ends to negate the value
of dFdy() when an FBO is in use. It also modifies the code that
populates the program key (brw_wm_populate_key() and
brw_fs_precompile()) so that they always record in the program key
whether we are rendering to an FBO or to a window system framebuffer;
this ensures that the fragment shader will get recompiled when
switching between FBO and non-FBO use.
This will result in unnecessary recompiles of fragment shaders that
don't use dFdy(). To fix that, we will need to adapt the GLSL and
NV_fragment_program front-ends to record whether or not a given shader
uses dFdy(). I plan to implement this in a future patch series; I've
left FIXME comments in the code as a reminder.
Fixes Piglit test "fbo-deriv".
NOTE: This is a candidate for stable release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2f8351a5ac7bb04482eebaa73d967f7527df4d18 |
|
17-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't set brw_wm_prog_key::iz_lookup on Gen6+.
Sandy Bridge and later don't use this field, so there's no point in
setting it. It can only cause harmful state-based recompiles.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4433b0302d0aa9dc61002e8bb4fd1b752b0be338 |
|
20-Apr-2012 |
Brian Paul <brianp@vmware.com> |
intel: use _mesa_is_winsys/user_fbo() helpers
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a07cf3397e332388d3599c83e50ac45511972890 |
|
27-Mar-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add support for sampling texture buffer objects on gen7+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 71d71d5e891570e8516c65471939a2ebdc07282a |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Compute required barycentric interp modes once at FS compile time.
Improves VS state change microbenchmark performance 1.78817% +/-
0.556878% (n=25).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b527dd65c830a2b008816cf390d5be906e29bb23 |
|
15-Nov-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Track fixed-function fragment shader as a shader
Previously the fixed-function fragment shader was tracked as a
gl_program. This means that it shows up in the driver as a Mesa IR
program instead of as a GLSL IR program. If a driver doesn't generate
Mesa IR from the GLSL IR, that program is empty. If the program is
empty there is either no rendering or a GPU hang.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 387a3d43d11cbd3eb1bd8ce787a2c693d575300c |
|
08-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Only set brw_wm_prog_key data for samplers used by the WM.
This should avoid state-dependent FS recompiles when samplers that are
only used by the VS change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1b05fc7cdd0e5d77b50bc8ee2f2c851da5884d72 |
|
07-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Factor out texturing related data from brw_wm_prog_key.
The idea is to reuse this for the VS and (in the future) GS as well.
v2: Include yuvtex data since we're not dropping GL_MESA_ycbycr.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| d2235b0f4681f75d562131d655a6d7b7033d2d8b |
|
18-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Always handle GL_DEPTH_TEXTURE_MODE through the shader.
We were already doing it through the shader (layered underneath
GL_EXT_texture_swizzle) in the shadow compare case. This avoids
having per-format logic for switching out the surface format dependent
on the depth mode.
v2: Also do the swizzling for DEPTH_STENCIL. oops.
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| dc9a753f6687133d2d057597e5af86abcdc56781 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move program compile to emit() time.
Only 4 other prepare() functions are left, which don't rely on this.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 5aa96286e7e1a5380673eb75e8653616b48751fd |
|
22-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Add support for noperspective interpolation.
This required the following changes:
- WM setup now makes the appropriate set of barycentric coordinates
(perspective vs. noperspective) available to the fragment shader,
based on whether the shader requires perspective interpolation,
noperspective interpolation, both, or neither.
- The fragment shader backend now uses the appropriate set of
barycentric coordiantes when interpolating, based on the
interpolation mode returned by
ir_variable::determine_interpolation_mode().
- SF setup now uses gl_fragment_program::InterpQualifier to determine
which attributes are to be flat shaded (as opposed to the old logic,
which only flat shaded colors).
- CLIP setup now ensures that the clipper outputs non-perspective
barycentric coordinates when they are needed by the fragment shader.
Fixes the remaining piglit tests of interpolation qualifiers that were
failing:
- interpolation-flat-*-smooth-none
- interpolation-flat-other-flat-none
- interpolation-noperspective-*
- interpolation-smooth-gl_*Color-flat-*
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| e04bdeae82797dbdcf6f544a997a4626fdfd4aee |
|
22-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Parameterize barycentric interpolation modes.
This patch modifies the fragment shader back-end so that instead of
using a single delta_x/delta_y register pair to store barycentric
coordinates, it uses an array of such register pairs, one for each
possible intepolation mode.
When setting up the WM, we intstruct it to only provide the
barycentric coordinates that are actually needed by the fragment
shader--that is computed by brw_compute_barycentric_interp_modes().
Currently this function returns just
BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because this is the only
interpolation mode we support. However, that will change in a later
patch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| db6dd6d88fdc4361193dd063e4f150f01a104faa |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename (vs|wm)_max_threads to max_(vs|wm)_threads for consistency.
The inconsistency between vs_max_threads and max_vs_entries was rather
annoying. I could never seem to remember which one was reversed, which
made it harder to find quickly. "Max __ Threads" seems more natural.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| de772c402215b956ab3aa0875330fc1bf7cdf95b |
|
21-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Use gl_shader_program::_LinkedShaders instead of FragmentProgram
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4170227407eea7fd8287b17480a37309bf73f4e4 |
|
07-Oct-2011 |
Brian Paul <brianp@vmware.com> |
i965: silence unused var warnings in non-debug builds
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| abbb8fc3a7d49066ecca10cb9db0b4756a1bbef0 |
|
23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix typo in 2b224d66a01f3ce867fb05558b25749705bbfe7a
Unfortunately, since a previous efficiency improvement, we no longer
have any open-source testcases producing register spilling, so this
code was untested in the fragment shader path. That should change
when we get proper temporary array support in the fragment shader.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40194
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2b224d66a01f3ce867fb05558b25749705bbfe7a |
|
07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Set up allocation of a VS scratch space if required.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 0722edc59cd526437c2d4bad474b934dad84d789 |
|
28-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Don't allocate the old backend's compile structs for our compile.
This saves some 35MB when the program only uses GLSL shaders.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 6430df37736d71dd2bd6f1fe447d39f0b68cb567 |
|
10-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Add support for TXD with shadow comparisons.
Our hardware doesn't have a sample_d_c message, so we have to do a
regular sample_d and emit instructions to manually perform the
comparison.
This requires a state dependent recompile whenever the sampler's compare
mode or function change. This adds the per-sampler comparison functions
to brw_wm_prog_key, but only sets them when the sampler's compare mode
is GL_COMPARE_R_TO_TEXTURE (i.e. only for shadow sampling).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8752764076e5b3f052a57e0134424a37bf2e9164 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Do a FS compile up front at link time to produce link errors.
At glLinkShaders time, a fail() call in FS compile in 8-wide (the one
that's required to succeed, though we may relax that at some point for
pre-Ironlake performance) will now report out as a link error.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1791857d7d950d3d2834bbb09b495f51f43ef7c1 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Move the computation of register block count from unit to compile.
No net code size change, but unit update is down 0.8% code size
pre-gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 9a729ab4b273f503747209a9c58dbb664adca838 |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead shadowtex_mask entry in the WM key.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f147599ef4b0d14c25a7e0d3f9f1c9b0229bb6fc |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.
From the GL 2.1 spec:
"Required perspective-correct interpolation for all fragment
attributes except depth in sections 3.4.1 and 3.5.1, effectively
making GL PERSPECTIVE CORRECT HINT a no-op."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b126a0c0cb30b1e2f2df1953fe14d8596d1cf4f7 |
|
02-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for correct GL_CLAMP behavior by clamping coordinates.
This removes the stupid strict-conformance fallback code I broke when
adding ARB_sampler_objects.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36572
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 774fb90db3e83d5e7326b7a72e05ce805c306b24 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Get a ralloc context into brw_compile.
This would be so much easier if we were using C++; we could simply use
constructors and destructors. Instead, we have to update all the
callers.
While we're at it, ralloc various brw_wm_compile fields rather than
explicitly calloc/free'ing them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3032582d032a28381dd4c2f4093d82c79e73129e |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead entrypoints to state cache, rename the one that's left.
As we expanded the usage of the state cache, it grew extra
functionality. However, with the recent state streaming rework, we're
back to the state cache being used only for shader kernels, which is
the piece of GPU state that's actually expensive to compute again from
scratch, since it involves compiling.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 662f1b48bd1a02907bb42ecda889a3aa52a5755d |
|
12-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add initial support for 16-wide dispatch on gen6.
At this point it doesn't do uniforms, which have to be laid out the
same between 8 and 16. Other than that, it supports everything but
flow control, which was the thing that forced us to choose 8-wide for
general GLSL support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1f32c665c8af0622e2bbf451edb999ffbcd7d0fe |
|
20-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_sampler_objects.
This extension support consists of replacing
"gl_texture_obj->Sampler." with "_mesa_get_samplerobj(ctx, unit)->".
One instance of referencing the texture's base sampler remains in the
initial miptree allocation, where I'm not sure we have a clear
association with any texture unit.
Tested with piglit ARB_sampler_objects/sampler-objects.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| d22e2ebe35ef9d33ec5f7a67f903f36bcd9fbc91 |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_color_buffer_float.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 59c6b775a6aacfe03c84dae62c2fd45d4af9d70b |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add gen6 register spilling support.
Most of this is code movement to get the scratch space allocated in a
shared location. Other than that, the only real changes are that the
old oword block messages now operate on oword-aligned areas (with new
messages for unaligned access, which we don't do), and that the
caching control is in the SFID part of the descriptor instead of
message control.
Fixes glsl-fs-convolution-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| ecfaab88b2577bd0395bc05d75a036126806a9c4 |
|
10-Apr-2011 |
Brian Paul <brianp@vmware.com> |
mesa: move sampler state into new gl_sampler_object type
gl_texture_object contains an instance of this type for the regular
texture object sampling state. glGenSamplers() generates new instances
of gl_sampler_object which can override that state with glBindSampler().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a99447314ca1cfce60f2a22285398fb222b2a440 |
|
12-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix alpha testing when there is no color buffer in the FBO.
We were alpha testing against an unwritten value, resulting in garbage.
(part of) Bug #35073.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1842b89f77bb7bd283b61e27cd69c643f2a60a22 |
|
13-Mar-2011 |
Chad Versace <chad.versace@intel.com> |
i965: Fix tex_swizzle when depth mode is GL_RED
Change swizzle from (x000) to (x001).
Signed-off-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| e0cbb154f2cb62e3ae0354dc4f14185dbad2bef2 |
|
13-Mar-2011 |
Chad Versace <chad.versace@intel.com> |
i965: Remove dead assignment
The assignment on line 368, `tex_swizzles[i] = SWIZZLE_NOOP`, is rendered
dead by the reassignment on line 392.
Signed-off-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1b80622c4e94e8c59eb2f7ee9989d99712baff8f |
|
31-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop the dead tracking of color_regions[].
We pull the draw regions right out of the renderbuffers these days.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3fb18d67753fec8a21461266246ff6949fc0fe81 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
intel: Set the swizzling for depth textures using the GL_RED depth mode.
Fixes depth-tex-modes-rg.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 5ba517baa22b05d594b8839ac06fe45b81c1d09f |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Nuke brw_wm_glsl.c.
It was only used for gen6 fragment programs (not GLSL shaders) at this
point, and it was clearly unsuited to the task -- missing opcodes,
corrupted texturing, and assertion failures hit various applications
of all sorts. It was easier to patch up the non-glsl for remaining
gen6 changes than to make brw_wm_glsl.c complete.
Bug #30530
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 16f8c823898fd71a3545457eacd2dc31ddeb3592 |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move payload reg setup to compile, not lookup time.
Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3b337f5cd94384d2d5918fb630aa8089e49b1d8d |
|
13-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix gl_FragCoord inversion when drawing to an FBO.
This showed up as cairo-gl gradients being inverted on everyone but
Intel, where I'd apparently tweaked the transformation to work around
the bug. Fixes piglit fbo-fragcoord.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 4e7252510976d8d3ff12437ea8842129f24d88f5 |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Correct scratch space allocation.
One, it was allocating increments of 1kb, but per thread scratch space
is a power of two. Two, the new FS wasn't getting total_scratch set
at all, so everyone thought they had 1kb and writes beyond 1kb would
go stomping on a neighbor thread.
With this plus the previous register spilling for the new FS,
glsl-fs-convolution-1 passes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 32573792de559c4dbad766a7cfcf02ea71f5047f |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Tell the shader compiler when we expect depth writes for gen6.
This fixes hangs in some Z-writes-in-shaders tests, though other
pieces don't come out correctly.
Bug #30392: hang in fbo-fblit-d24s8. (still fails with bad color drawn
to some targets)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 14bf92ba19373d54e9909bbdda5e430e0affea37 |
|
03-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix glean/texSwizzle regression in previous commit.
Easy enough patch, who needs a full test run. Oh, that's right. Me.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a7fa00dfc5ab5782b2e497fbf4ca292dde69cdbd |
|
03-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.
The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't
apply to shadow compares, which always return an intensity value. The
texture swizzles can do the job for us.
Fixes:
glsl1-shadow2D(): 1
glsl1-shadow2D(): 3
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| a66e9a4d86d227b65874c43fbf9e299c7a26389f |
|
26-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for attribute interpolation on Sandybridge.
Things are simpler these days thanks to barycentric interpolation
parameters being handed in in the payload.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| dd9a88f4ddf4e5fa384792f891a1cc3d8ff73946 |
|
21-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Track the windowizer's dispatch for kill pixel, promoted, and OQ
Looks like the problem was we weren't passing the depth to the render
target as expected, so the chip would wedge. Fixes GPU hang in
occlusion-query-discard.
Bug #30097
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| dd5ef33e3c2ac7886ca71344e41201d0be2062c0 |
|
01-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: DP2 produces a scalar result like DP3, DP4, etc.
Fixes glsl-fs-dot-vec2-2.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 9763d0a82a1ee605a8794f199d432824fb972b6a |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start building direct GLSL2 IR to 965 assembly codegen.
Our channel-expressions and vector-splitting changes now happen into a
private copy of the IR that we maintain for ourselves. Uniform
assignment still happens by the core, so we continue using Mesa IR
generation not just for swrast fallbacks but also for uniform values
(since there's no storage for their contents other than
shader_program->FragmentProgram->Parameters->ParameterValues). And
most importantly, at the moment no actual codegen is hooked up other
than emitting our favorite color to the framebuffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c374487a54aca2dd1053645092367c1cf0414ef7 |
|
11-Aug-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove include of texmem.h, since we haven't used it in ages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 32f2fd1c5d6088692551c80352b7d6fa35b0cd09 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace _mesa_malloc, _mesa_calloc and _mesa_free with plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f62c2a0bb89041567467a6c01cf1eb27cec01e9e |
|
26-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix fp fragment.position handling and enable HW part of ARB_fcc.
As with swrast, this fixes the default pixel center behavior which was
broken, and implements the previous behavior for integer. Fixes
piglit fp-arb-fragment-coord-conventions-none. The extension won't be
exposed until we get the GLSL part implemented.
The DRI1 origin_x/y parts are dropped since they're no longer relevant.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8451b29d9628f09b65962385bfbd95cd7f26427f |
|
21-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix several memory leaks on exit.
Bug #25194.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 5606dfb572bf4b89b4882265924705bacc8c182b |
|
18-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'outputswritten64'
Add a GLbitfield64 type and several macros to operate on 64-bit
fields. The OutputsWritten field of gl_program is changed to use that
type. This results in a fair amount of fallout in drivers that use
programs.
No changes are strictly necessary at this point as all bits used are
below the 32-bit boundary. Fairly soon several bits will be added for
clip distances written by a vertex shader. This will cause several
bits used for varyings to be pushed above the 32-bit boundary. This
will affect any drivers that support GLSL.
At this point, only the i965 driver has been modified to support this
eventuality.
I did this as a "squash" merge. There were several places through the
outputswritten64 branch where things were broken. I foresee this
causing difficulties later for bisecting. The history is still
available in the branch.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c5413839b3e99c7b162f1260142f3c175502b0ce |
|
11-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.
For an app that's blowing out the state cache, like sauerbraten, the
memset of the giant arrays ended up taking 11% of the CPU even when only a
"few" of the entries got used. With this, the WM program compile drops back
down to 1% of CPU time.
Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 861fec163c1ae7e431956db0a08989d841e2b74e |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: avoid shader translation on window resize
If the fragment shader doesn't use FRAG_ATTRIB_WPOS (gl_FragCoord) we
don't need to worry about the window size and origin in
brw_wm_populate_key().
This avoids re-generating the i965 shader code when a window is resized.
Issue spotted by Keith Whitwell.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 9ef33b86855c4d000271774030bd1b19b6d79687 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: don't use context state in emit_fb_write()
Put the state that we care about in the hash key.
Issue spotted by Keith Whitwell.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 3e34a2a2b97e7c93955deedb7c12b73bccd6662d |
|
06-Oct-2009 |
Brian Paul <brianp@vmware.com> |
drivers: don't include texformat.h
And remove other unneeded #includes while we're at it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa |
|
01-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: replace gl_texture_format with gl_format
Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 08687c8b402f42eda5e0061112382528836b0fe9 |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Correct brw_wm_nr_args for WM_DELTAXY and WM_PIXELXY.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 0eb819a2d175cab139f8c672b6d44148b2c99a4e |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Store the dispatch width in the WM compile struct.
I'll be using this in merging brw_wm_emit.c and brw_wm_glsl.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f44916414ecd2b888c8a680d56b7467ccdff6886 |
|
06-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix source depth reg setting for FSes reading and writing to depth.
For some IZ setups, we'd forget to account for the source depth register
being present, so we'd both read the wrong reg, and write output depth to
the wrong reg.
Bug #22603.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8d482227915552c414e13743652e6794c4313ae2 |
|
17-Jun-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch'
Conflicts:
src/mesa/main/api_validate.c
|
| 6b917d0b1787280f976c2f0d1ead0e5d7587a3e9 |
|
17-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix bugs in projective texture coordinates
For the TXP instruction we check if the texcoord is really a 4-component
atttibute which requires the divide by W step. This check involved the
projtex_mask field. However, the projtex_mask field was being miscalculated
because of some confusion between vertex program outputs and fragment
program inputs.
1. Rework the size_masks calculation so we correctly set bits corresponding
to fragment program input attributes.
2. Rename projtex_mask to proj_attrib_mask since we're interested in more
than just texcoords (generic varying vars too).
3. Simply the indexing of the size_masks and proj_attrib_mask fields.
4. The tracker::active[] array was mis-dimensioned. Use MAX_PROGRAM_TEMPS
instead of a magic number.
5. Update comments, add new assertions.
With these changes the Lightsmark demo/benchmark renders correctly, until
we eventually hit a GPU lockup...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 18af7c384cf663533f210d95d074c244d4214f29 |
|
13-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: interpolate colors with perspective correction by default
...rather than with linear interpolation. Modern hardware should use
perspective-corrected interpolation for colors (as for texcoords).
glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get
linear interpolation if mode = GL_FASTEST.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 0f5113deed91611ecdda6596542530b1849bb161 |
|
14-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix register allocation of GLSL fp inputs.
Before, if the VP output something that is in the attributes coming into
the WM but which isn't used by the WM, then WM would end up reading subsequent
varyings from the wrong places. This was visible with a GLSL demo
using gl_PointSize in the VS and a varying in the WM, as point size is in
the VUE but not used by the WM. There is now a regression test in piglit,
glsl-unused-varying.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 44a4abfd4f8695809eaec07df8eeb191d6e017d7 |
|
08-May-2009 |
Robert Ellison <papillo@vmware.com> |
i965: fix segfault on low memory conditions
When out of memory (in at least one case, triggered by a longrunning
memory leak), this code will segfault and crash. By checking for the
out-of-memory condition, the system can continue, and will report
the out-of-memory error later, a much preferable outcome.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 5f1ce6b87e837b9f6bc2a4f3e81cf8feea4af2df |
|
31-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: comments
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 699db6d842c52d0b3b98b320f8ef1104a65fa783 |
|
24-Mar-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix glFrontFacing in twoside GLSL demo.
This also cuts instructions by just using the existing bit in the payload
rather than computing it from the determinant in the SF unit and passing it
as a varying down to the WM. Something still goes wrong with getting the
backface color right, but a simpler shader appears to get the right result.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 5cbd1170da0a902fdc9c460584bc503b0c4085a6 |
|
07-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: avoid unnecessary calls to brw_wm_is_glsl()
This function scans the shader to see if it has any GLSL features like
conditionals and loops. Calling this during state validation is expensive.
Just call it when the shader is given to the driver and save the result.
There's some new/temporary assertions to be sure we don't get out of sync
on this.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 91e61f435a71436c209934a0ece165b540aba3e0 |
|
02-Mar-2009 |
Brian Paul <brianp@vmware.com> |
mesa: use Stencil._Enabled field instead of Stencil.Enabled
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8d475822e6e19fa79719c856a2db5b6a205db1b9 |
|
28-Feb-2009 |
Brian Paul <brianp@vmware.com> |
mesa: rename, reorder FRAG_RESULT_x tokens
s/FRAG_RESULT_DEPR/FRAG_RESULT_DEPTH/
s/FRAG_RESULT_COLR/FRAG_RESULT/COLOR/
Remove FRAG_RESULT_COLH (NV half-precision) output since we never used it.
Next, we might merge the COLOR and DATA outputs (COLOR0, COLOR1, etc).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 55d33e1fa7d231a0cdfce9b9650ae9e136e6c63c |
|
20-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: update comment, use const qualifier
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 2f78d4a2cd009d8d6a5f470d5738586b7f89f3d9 |
|
12-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: code clean-ups, comments, and minor refactoring
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 14dc4937336061c4c8d51c75d96fa216d9edcf2a |
|
12-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix inconsistant indentation in brw_wm.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| c0d3b7679aa90e1a0dca2db152205efaec088b90 |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement GL_EXT_texture_swizzle
If the texture swizzle is not XYZW (no-op) add an extra MOV instruction
after the TEX instruction to rearrange the components.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 89fddf978c9d2ab5042f89110015234e979c2686 |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor improvements in brw_wm_populate_key()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| dde7cb962860e72e1bf3175069767358cc5b3f3c |
|
10-Jan-2009 |
Ian Romanick <idr@freedesktop.org> |
Track two sets of back-face stencil state
Track separate back-face stencil state for OpenGL 2.0 /
GL_ATI_separate_stencil and GL_EXT_stencil_two_side. This allows all
three to be enabled in a driver. One set of state is set via the 2.0
or ATI functions and is used when STENCIL_TEST_TWO_SIDE_EXT is
disabled. The other is set by StencilFunc and StencilOp when the
active stencil face is set to BACK. The GL_EXT_stencil_two_side spec has
more details.
http://opengl.org/registry/specs/EXT/stencil_two_side.txt
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| fc3971d80051b34836716579fd060dbb122d036b |
|
09-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove gratuitous whitespace in INTEL_DEBUG=wm output.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 046e88fc0be37d5a3dfbfa9fb8033b549604c74c |
|
09-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use _mesa_num_inst_src_regs() instead of keeping a copy of its contents.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 32e03c4a2ff5ef07de892dcd26f6be3b82ab3ba1 |
|
01-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: added OPCODE_NRM3/4
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8a1e7086c7c1d2fed22a0d7f840de515a6ca7e18 |
|
03-Dec-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix stray character that the compile whined about.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 8e76ac070dfea5d151d31121af5c8ca1c99caeb0 |
|
27-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i915: Remove dead early z enable bit which was always on.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| b17b110716936c32d20910cb9589038062b4f527 |
|
20-Aug-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Enable GL_ARB_fragment_program_shadow and fix key->shadowtex_mask. (bug #16852, #16853)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|
| fcb7cb9e72ecac7c165a3a6ed7a033e2e6793a26 |
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13-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 7676980d38cff417015bca8d23549d567d74228b |
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07-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] fix fd.o bug #11471 and #11478
1. Follow EXT_texture_rectangle with YCbCr texture
2. swap UV component for MESA_FORMAT_YCBCR
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 9c8f27ba1366da07e20e86a0d48341ea97f5cda4 |
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28-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Bug #9151: make fragment.position return window coords not screen coords.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| eb9da9706ee060a8e4bb5c4fa133ab06dc6b5a53 |
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14-Feb-2008 |
Dave Airlie <airlied@redhat.com> |
i965: remove unused hal hooks
These don't appear to have ever been used.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
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29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 9136e1f2c80ce891fb6270341a4316f219c89d49 |
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21-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Fix and enable separate stencil.
Note that this does not enable GL_EXT_stencil_two_side, because Mesa's computed
_TestTwoSide ends up respecting only STENCIL_TEST_TWO_SIDE_EXT (defaults to
GL_FALSE), even if the application uses only GL 2.0 / ATI entrypoints.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
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14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 125bd4cae51c6deaacd2e90f14931c2052f146ab |
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06-Dec-2007 |
Eric Anholt <eric@anholt.net> |
Revert "[965] Add missing flagging of new stage programs for updating stage state."
I had forgotten part of brw_state_cache.c that made this fix not relevant for
master (last_addr comparison and flagging based on cache id).
This reverts commit a4642f3d18bdaebaba31e5dee72fe5de9d890ffb.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| a4642f3d18bdaebaba31e5dee72fe5de9d890ffb |
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06-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Add missing flagging of new stage programs for updating stage state.
Otherwise, choosing a new program wouldn't necessarily update the state, and
and an old program could be executed, leading to various sorts of pretty
pictures or hangs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 6ef27b88e6f767cd476676b33cb7c4ea6922234e |
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26-Oct-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Merge branch '965-glsl'
Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
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| 88451b04e9cd39db9cc9315aaf69e074614f22f9 |
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13-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix projtex_mask
projtex_mask is only an 8bit field, and wm.input_size_masks includes
other attributes' information, therefore right shift is needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
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21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 35707dbe57873adb5a8088cd47c13bd216e143e4 |
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12-Apr-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Initial 965 GLSL support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 064ae479a770bf434958d673baf6f7530f642697 |
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23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| d7b24fec245f90db4b8c66f4f7c167b8f20a9b9e |
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10-Dec-2006 |
Eric Anholt <eric@anholt.net> |
i965: Fix a crash with wine by not allocating >1MB on the stack.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
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09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.c
|