| 270597d13fbd2659b17deddb215adabd32961459 |
|
26-Jan-2017 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix check for negative pitch in can_do_fast_copy_blit().
At this point, the pitch is in bytes. We haven't yet divided the pitch
by 4 for tiled surfaces, so abs(pitch) may be larger than 32K. This
means the bit 15 trick won't work.
The caller now has signed integers anyway, so just pass those through
and do the obvious check.
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 02216a1ddf2bcafb86fda352e514f27ab6f7a4fa)
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 2554c98d70f4a919fbe71c43e6261b799d2cd6ba |
|
22-Jan-2017 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make intelEmitCopyBlit not truncate large strides.
When trying to blit larger tiled surfaces, the pitch can be larger than
32768 bytes, which means it won't fit in a GLshort. Passing it in will
truncate the stride to 0, which has...surprising results.
The pitch can be up to 32,768 DWords, or 128kB. We measure it in bytes,
but divide by 4 when programming it. So we need to handle values up to
131,072. Switch from GLshort to int32_t to avoid the truncation.
Fixes GL45-CTS.gtf30.GL3Tests.depth_texture.depth_texture_copyteximage
at widths greater than 8192.
v2: Use int32_t as negative values can be used (Jason).
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit f8f7ea508be7fe7222cd19e0d59574cfea2decf0)
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 157971e450c34ec430c295ff922c2e597294aba3 |
|
06-Dec-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blit: Fix the src dimension sanity check in miptree_copy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 06d864921ee6cfd083ac3782d4434d91ec652eea |
|
01-Dec-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/copy_image: Re-implement the blitter path with emit_miptree_blit
By using emit_miptree_blit which does chunking, this fixes the blitter path
for the case where the image is too tall to blit normally. We also pull it
into intel_blit as intel_miptree_copy. This matches the naming of the
blorp blit and copy functions brw_blorp_blit and brw_blorp_copy.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 6c74e7f492b526f16b6ae59b16eb30df14f793c8 |
|
01-Dec-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blit: Break the guts of intel_miptree_blit into a helper
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 9c7717c066b4a315ed6dccd8a48d9eaf81a5b33f |
|
15-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Provide slice details to color resolver
v2: Make intel_miptree_resolve_color() take start layer and
layer count.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 80d3af812935978f01c9bb6d02102140383c4034 |
|
24-Oct-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blit: Break blits into chunks in intel_miptree_blit
This allows us to blit much larger images than if we use the blitter
directly. In particular, it gives us an almost infinite image height
compared to the fairly limiting 32k. We do, however, still have a
restriction on stride of the image because handling larger strides, while
possible, is fairly difficult.
v2: Properly handle linear blit alignment restrictions
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| b7979a849bc185fbcab93a841eed692a10d61e25 |
|
24-Oct-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blit: Break blits into chunks in set_alpha_to_one
v2: Properly handle linear blit alignment restrictions
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 174f4900b294f939c85cfa94f5d8401ce73e5522 |
|
24-Oct-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blit: Remove a bogus assertion
This assertion, while valid for linear buffers, doesn't work properly for
tiled memory. It used to work most of the time because the offset provided
was always to the left-hand edge of the image. However, if you use a byte
offset to get to the inside of the image, the height * stride calculation
may actually end up being too large.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 949a89202621eb73e9f9d4c7b452d9bf9afbfd40 |
|
09-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Roll intel_reg.h into brw_defines.h
More than half of the stuff in intel_reg.h had nothing whatsoever to do
with registers and really belongs in brw_defines.h anyway.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| b1586526e84ab6eab2023b589da8e153f70dda50 |
|
03-Aug-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Bail on the BLT path if BlitFramebuffer requires sRGB conversion.
Modern OpenGL BlitFramebuffer require sRGB encode/decode when
GL_FRAMEBUFFER_SRGB is enabled. The blitter can't handle this,
so we need to bail. On Gen4-5, this means falling back to Meta,
which should handle it.
We allow sRGB <-> sRGB blits, as decode then encode ought to be a noop
(other than potential precision loss, which nobody wants anyway).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| df210ff24dbdf9d3459061196e28dd37223c0cc5 |
|
28-May-2016 |
Thomas Hindoe Paaboel Andersen <phomes@gmail.com> |
i965: add missing return in if statement
Re-add the "return false" that was removed in 0c02d7002d6c005b4c1fe997b5ef5916978dd183
It seems that something went wrong when merging the patch. The patch
sent to the mailing list does not directly match what was committed.
https://lists.freedesktop.org/archives/mesa-dev/2016-May/118198.html
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 0c02d7002d6c005b4c1fe997b5ef5916978dd183 |
|
25-May-2016 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Don't use fast copy blit in case of logical operations other than GL_COPY
XY_FAST_COPY_BLT command doesn't have a field for raster operation. So, fall
back to using XY_SRC_COPY_BLT to handle those cases.
Fixes piglit test gl-1.1-xor-copypixels when fast copy blit is enabled
for all tiling formats.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 97f0f91cc191d9d024588458f23a229b91acb84d |
|
12-Dec-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen9: Remove the halign/valign field setup code in fast copy blit
Experimentation with different values of src/dst horizontal/vertical
alignment showed that these fileds are not used on gen9 hardware.
A recent update in graphics specs has removed these fields from
XY_FAST_COPY_BLT command.
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Chad Versace <chad.versace@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| f709a0845792540544982740fa47be672825ee8a |
|
08-Dec-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Add means for limiting color resolves
Until now there has been only one type of color buffer that needs
to resolved - namely single sampled fast clear. As even the
sampler engine in GPU doesn't understand the associated meta data,
the color values need to be always resolved prior to reading them.
From SKL onwards there is new scheme supported called the lossless
compression of single sampled color buffers. This is something that
is understood by the sampling engine and therefore resolving of
these types of buffers is not necessary before sampling.
This patch adds means to make the distinction when considering if
resolve is needed.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 0bf037c0fed0df655a3bb259348bb03389c00ddb |
|
11-Nov-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen9: Return false in place of assert in intelEmitCopyBlit()
This allows the fallback paths to handle it correctly.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 5cbe01c83fb78009371535e558eb21e213312416 |
|
03-Nov-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen9: Remove regions overlap check in fast copy blit
Overlapping blits are anyway undefined in OpenGL. So no need
of overlap check here.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 3c8b97a45b824712452b1425ed5cac3b97286439 |
|
28-Jul-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen9: Don't use fast copy blit in case of non power of 2 cpp
Fast copy blit is currently enabled for use only with Yf/Ys tiling.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| eb6b80842ffc27f138cc0221c5465c51d0105c04 |
|
10-Apr-2015 |
Mark Janes <mark.a.janes@intel.com> |
i965: remove unneeded #include of colormac.h
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 945592f92ca91e21307d10b657835d512bacf8b8 |
|
24-Jul-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen9: Add a condition for starting pixel in fast copy blit
This condition restricts the use of fast copy blit to cases
where starting pixel of src and dst is oword (16 byte) aligned.
Many piglit tests (if using fast copy blit in Mesa) failed earlier
because I missed adding this condition.Fast copy blit is currently
enabled for use only with Yf/Ys tiling.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 0bfd914f9f02c85a4ad8e6892f1a31e37c14f2b2 |
|
12-Aug-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen9: Fix {src, dst}_pitch alignment check for XY_FAST_COPY_BLT
I misinterpreted the alignmnet restriction in XY_FAST_COPY_BLT earlier.
Instead of checking pitch for 64KB alignmnet we need to check it for
tile widh alignment.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 0fa39bff19dc2fbd3c184bd0e1267c86bd5040d9 |
|
12-Aug-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Fix {src, dst}_pitch alignment check for XY_SRC_COPY_BLT
Current code checks the alignment restrictions only for Y tiling.
From Broadwell PRM vol 10:
"pitch is of 512Byte granularity for Tile-X: This means the tiled-x
surface pitch can be (512, 1024, 1536, 2048...)/4 (in Dwords)."
This patch adds the restriction for X tiling as well.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| e83b07aa7b124184decd68a64d970e8f408f8725 |
|
12-Aug-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Move conversion of {src, dst}_pitch to dwords outside if/else
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 485285498f39aa9590d430dee6d52c796531b8c0 |
|
12-Aug-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Delete temporary variable 'src_pitch'
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 284dcad20a9a55278c1d3dd98f53e45650b22896 |
|
20-Aug-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Fix typos in license
grep -lr 'sub license' | while read f; do \
sed --in-place -e 's/sub license/sublicense/' $f ;\
done
grep -lr 'NON-INFRINGEMENT' | while read f; do \
sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\
done
As noted by Matt, both of these changes match the MIT license text found
at http://opensource.org/licenses/MIT.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| aa1a5c0c9e0de71ecd15e7190c121d6dd98471a6 |
|
20-Aug-2015 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Remove horizontal bars from file header comments
Why was that ever a thing?
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| d38a5601068ae1d923efece8f28757777f4474e4 |
|
06-Jun-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Prevent coordinate overflow in intel_emit_linear_blit
Fixes regression from
commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Wed Apr 15 03:04:33 2015 -0700
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
which adjusted the coordinates to be relative to the nearest cacheline.
However, this then offsets the coordinates by up to 63 and this may then
cause them to overflow the BLT limits. For the well aligned large
transfer case, we can use 32bpp pixels and so reduce the coordinates by
4 (versus the current 8bpp pixels). We also have to be more careful
doing the last line just in case it may exceed the coordinate limit.
Reported-and-tested-by: kaillasse91@hotmail.fr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 2484263fe97cebc9fa7a5c9de04c757dc6cc7713 |
|
29-Jul-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| f11c6f09cf36909ff399353b20195a31cf0f1907 |
|
09-Jul-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Optimize batchbuffer macros.
Previously OUT_BATCH was just a macro around an inline function which
does
brw->batch.map[brw->batch.used++] = dword;
When making consecutive calls to intel_batchbuffer_emit_dword() the
compiler isn't able to recognize that we're writing consecutive memory
locations or that it doesn't need to write batch.used back to memory
each time.
We can avoid both of these problems by making a local pointer to the
next location in the batch in BEGIN_BATCH().
Cuts 18k from the .text size.
text data bss dec hex filename
4946956 195152 26192 5168300 4edcac i965_dri.so before
4928956 195152 26192 5150300 4e965c i965_dri.so after
This series (including commit c0433948) improves performance of Synmark
OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 3df5aaaa158bfb878e9e5ce467dd654466942880 |
|
28-May-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/skl: Extract the blit command setup in to a helper
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 412c8c8e7eaeec2763bb21a30626544b5a711cb2 |
|
15-Apr-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()
This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
It can be later turned on for other tiling patterns (X,Y) too.
V3: Flush in between sequential fast copy blits.
Fix src/dst alignment requirements.
Make can_fast_copy_blit() helper.
Use ffs(), is_power_of_two()
Move overlap computation inside intel_miptree_blit().
V4: Use _mesa_regions_overlap() function.
Add check for src_buffer == dst_buffer.
Simplify horizontal and vertical alignment computations.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9 |
|
30-Apr-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 84d27c32d238ca7a7b115bf190e7e527b7f70e92 |
|
28-May-2015 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Remove break after return
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 922c0c9fd526ce19b87bc74a3159dec7705c1de1 |
|
05-Jun-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Export format comparison for blitting between miptrees
Since the introduction of
commit 536003c11e4cb1172c540932ce3cce06f03bf44e
Author: Boyan Ding <boyan.j.ding@gmail.com>
Date: Wed Mar 25 19:36:54 2015 +0800
i965: Add XRGB8888 format to intel_screen_make_configs
winsys buffers no longer have an alpha channel. This causes
_mesa_format_matches_format_and_type() to reject previously working BGRA
uploads from using the BLT fast path. Instead of using the generic
routine for matching formats exactly, export the slightly more relaxed
check from intel_miptree_blit() which importantly allows the blitter
routine to apply a small number of format conversions.
References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Alexander Monakov <amonakov@gmail.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| c2d0606827412b710dcaed80268fc665de8c9c5d |
|
05-Jun-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i915: Blit RGBX<->RGBA drawpixels
The blitter already has code to accommodate filling in the alpha channel
for BGRX destination formats, so expand this to also allow filling the
alpha channgel in RGBX formats.
More importantly for the next patch is moving the test into its own
function for the purpose of exporting the check to the callers.
v2: Fix alpha expansion as spotted by Alexander with the fix suggested by
Kenneth
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Alexander Monakov <amonakov@gmail.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 8da79b8378ae87474d8c47ad955e4833edf98359 |
|
05-Jun-2015 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Fix HW blitter pitch limits
The BLT pitch is specified in bytes for linear surfaces and in dwords
for tiled surfaces. In both cases the programmable limit is 32,767, so
adjust the check to compensate for the effect of tiling.
v2: Tweak whitespace for functions (Kenneth)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 5957da1edb9ad504d8af83878c10c3a24e41fc6c |
|
21-Apr-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disallow linear blits that are not cacheline aligned.
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of converting the BLT to
use 48-bit addressing.
The main user, intel_emit_linear_blit, now handles this properly.
But we might also have linear miptrees; just refuse to blit those.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 8c17d53823c77ac1c56b0548e4e54f69a33285f1 |
|
15-Apr-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of converting the BLT to
use 48-bit addressing.
intel_emit_linear_blit needs to handle blits that are not cacheline
aligned, as we use it for arbitrary glBufferSubData calls and subrange
mappings.
Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst
pixel X offset field to represent the unaligned portion, and subtract
that from the address so it's cacheline aligned.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 28d9e90428282a5e0a6aa31ad858a5cf514d1264 |
|
07-Apr-2015 |
Marius Predut <marius.predut@intel.com> |
i965: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 7ea1e3749738c63388d3bcca327e4e4dd28f17b8 |
|
23-Dec-2014 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965: Add more stringent blitter assertions
Blits to or from a y-tiled surface must always be a multiple of the tile size.
From page 16 of the HSW PRM
(https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16)
"The pitch of a tiled enclosing region must be an integral number of tile
widths"
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| efde74c89dd8596b4cc0dfd9601e55832833f20e |
|
23-Dec-2014 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965: Consolidate some of the intel_blit logic
An upcoming patch is going to introduce some code here, and having this code
organized as the patch does makes it a bit easier to read later.
There should be no functional change here.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 83e8bb5b1a50c0105b642d559999f07fa64a982f |
|
16-Sep-2014 |
Cody Northrop <cody@lunarg.com> |
i965: Require pixel alignment for GPU copy blit
The blitter will start at a pixel's natural alignment. For PBOs, if the
provided offset if not aligned, bits will get dropped.
This change adds offset alignment check for src and dst, kicking back if
the requirements are not met.
The change is based on following verbiage from BSPEC:
Color pixel sizes supported are 8, 16, and 32 bits per pixel (bpp).
All pixels are naturally aligned.
Found in the following locations:
page 35 of intel-gfx-prm-osrc-hsw-blitter.pdf
page 29 of ivb_ihd_os_vol1_part4.pdf
page 29 of snb_ihd_os_vol1_part5.pdf
This behavior was observed with Steam Big Picture rendering incorrect
icon colors. The fix has been tested on Ubuntu and SteamOS on Haswell.
Signed-off-by: Cody Northrop <cody@lunarg.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83908
Reviewed-by: Neil Roberts <neil@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 9cd4f9024239f00c005e3dc1b2270e60e82b412d |
|
11-Dec-2014 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/gen8: Check correct number of blitter dwords
The odds of having this patch make a difference on Gen8+ are probably very low.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-but-not-tested-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 3d826729dabab53896cdbb1f453c76fab1c7e696 |
|
29-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use unreachable() instead of unconditional assert().
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| e7f65655cbddc53a95ca9d9b6f5d738e82797aac |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Delete the intel_regions.c code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| e16c5c906316c58c0633e9bba02339ef981e5ef3 |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop use of intel_region from miptrees.
Note: region->width/height used to reflect the total_width/height padding
of separate stencil, though mt->total_width didn't. region->width/height
was being used in EGL images, where the padded value would have been the
wrong one, so I converted them to use rb->Width/Height.
v2: Drop debug printf that slipped in (caught by Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| b3094d9927fe7aa5a84892262404aaad4d728724 |
|
08-Jan-2014 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965: Fix the region's pitch condition to use blitter
intelEmitCopyBlit uses a signed 16-bit integer to represent
buffer pitch, so it can only handle buffer pitches < 32k.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| b18871c863fabec3ed383881d2cdd0298b157b06 |
|
23-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't forget to subtract mt->first_level in minify calls.
This fixes fbo-clear-formats GL_ARB_depth_texture on Ironlake, which
regressed since commit f128bcc7c293013f4b44e4b661638333de0077c2
("i965: Drop mt->levels[].width/height.") intel_miptree_copy_slice was
calling minify(.., 7) on a 2x2 texture with mt->first_level == 7.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75292
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 73c78c514f8db0605c0deb85382003d0f66b5525 |
|
22-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't try to use the hardware blitter for multisampled miptrees.
The blitter is completely ignorant of MSAA buffer layouts, so any
attempt to use BLT paths with MSAA buffers is likely to break
spectacularly.
In most cases, BLORP handles MSAA blits, so we never hit this bug.
Until recently, it also wasn't worth fixing, since Meta couldn't handle
MSAA either, so there was nothing to fall back to. But now there is.
+143 piglit tests on Broadwell (which doesn't have BLORP support).
Surprisingly, three also start failing. Since non-IMS MSAA buffers
store samples in successive array slices, using the blitter ought to
access sample 0 and ignore the rest, which is apparently good enough for
a few not-very-picky Piglit tests. Presumably the meta replacement code
is still broken.
No Piglit changes on Ivybridge.
v2: Move the early return to the top of the function (suggested by
Paul).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| f128bcc7c293013f4b44e4b661638333de0077c2 |
|
14-Feb-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop mt->levels[].width/height.
It often confused people because it was unclear on whether it was the
physical or logical, and people needed the other one as well. We can
recompute it trivially using the minify() macro, clarifying which value is
being used and making getting the other value obvious.
v2: Fix a pasteo in intel_blit.c's dst flip.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| ef145ba4ded6aafb28e3bda02fb348e6b8bff12a |
|
20-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: Rename 4 color component unsigned byte MESA_FORMATs
Change all 4 color component unsigned byte formats to meet spec for P
Type formats:
s/MESA_FORMAT_RGBA8888\b/MESA_FORMAT_A8B8G8R8_UNORM/g
s/MESA_FORMAT_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_UNORM/g
s/MESA_FORMAT_ARGB8888\b/MESA_FORMAT_B8G8R8A8_UNORM/g
s/MESA_FORMAT_ARGB8888_REV\b/MESA_FORMAT_A8R8G8B8_UNORM/g
s/MESA_FORMAT_RGBX8888\b/MESA_FORMAT_X8B8G8R8_UNORM/g
s/MESA_FORMAT_RGBX8888_REV\b/MESA_FORMAT_R8G8B8X8_UNORM/g
s/MESA_FORMAT_XRGB8888\b/MESA_FORMAT_B8G8R8X8_UNORM/g
s/MESA_FORMAT_XRGB8888_REV\b/MESA_FORMAT_X8R8G8B8_UNORM/g
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 71fe9437169cfdafda8814aa814bb85429fb6cfc |
|
04-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: change gl_format to mesa_format
s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 94c0a11b199fb299ee1b2ea38154df5d5e621a64 |
|
13-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update blitter code for 48-bit addresses.
v2: Rebase on Eric's SET_FIELD changes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 877128505431adaf817dc8069172ebe4a1cdf5d8 |
|
17-Jan-2014 |
José Fonseca <jfonseca@vmware.com> |
s/Tungsten Graphics/VMware/
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 66524daf175950bd7266fc3cbb4125c24984a482 |
|
23-Dec-2013 |
Eric Anholt <eric@anholt.net> |
i965: Use SET_FIELD to safety check our x/y offsets in blits.
The earlier assert made sure that our math didn't exceed our bounds, but
this makes sure that we don't overflow from the high bits X into the low
bits of Y. We've already put checks in intel_miptree_blit(), but I've
wanted to expand the type in our protoype from short to uint32_t, and we
could get in trouble with intel_emit_linear_blit() if we did.
v2: Add Ken's comment about the funny language extension used.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 98cdb2ceede34ad04cd8f65691bd96fbb44bcced |
|
23-Dec-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add a safety check for emitting blits.
With all of the flipping and pitch twiddling and miptree layout involved
in our blits, there are lots of ways for us to scribble outside of a
buffer. Put in a check that we're not about to do so.
This catches a bug that glamor was running into.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| bdc5241af4aa9afbd66f6c96ee6d20e09f77ea89 |
|
24-Dec-2013 |
Eric Anholt <eric@anholt.net> |
i965: Don't call the blitter on addresses it can't handle.
Noticed by tex3d-maxsize on my next commit to check that our addresses
don't overflow.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 19190c2b8c67baa258cf2865ea95ff5dca300d36 |
|
25-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Replace OUT_RELOC_FENCED with OUT_RELOC.
On Gen4+, OUT_RELOC_FENCED is equivalent to OUT_RELOC; libdrm silently
ignores the fenced flag:
/* We never use HW fences for rendering on 965+ */
if (bufmgr_gem->gen >= 4)
need_fence = false;
Thanks to Eric for noticing this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| a7bdd4cba8ddcab8dff59ecaaa7efbd436c6c307 |
|
26-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop trailing whitespace from the rest of the driver.
Performed via:
$ for file in *; do sed -i 's/ *//g'; done
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 6bc40f9af5b35724caff9fa7ced47b2ca6183f22 |
|
29-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert brw->batch.is_blit to a BLT_RING/RENDER_RING enum.
Passing BLT_RING or RENDER_RING to batchbuffer functions is a lot more
obvious than passing true or false.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 68f1b274b06ed6f14cc8d069bee3cabc520fb553 |
|
03-Nov-2013 |
Vinson Lee <vlee@freedesktop.org> |
i965: Fix logic_op check.
Fixes "Macro compares unsigned to 0" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| fcb4ab6db12ec4287e5520c5148adfc2df079e19 |
|
08-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete the BATCH_LOCALS macro.
This hasn't done anything in a long time, and it's only used in a couple
places...which means we couldn't use it without doing a bunch of work
anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| b15f1fc3c6b3b9dc4422940c412f80e581c9900d |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::perf_debug to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 329779a0b45b63be17627f026533c80b2c8f7991 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::batch to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| a69274454b6bde265a910ca5bd3199217431f5b5 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Replace #include "intel_context.h" with brw_context.h.
brw_context.h includes intel_context.h, but additionally makes the
brw_context structure available. Switching this allows us to start
using brw_context in more places.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| d58d0a37548c75a8521d0196560b401e705d0fb9 |
|
21-Jun-2013 |
Eric Anholt <eric@anholt.net> |
i965: Drop i915-specific blit clear code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 4a08a86f222f839aba68c5b5a775352d5b5ff5fa |
|
21-Jun-2013 |
Eric Anholt <eric@anholt.net> |
i965: Drop #ifdef I915 code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 3dbba95b72262344b82fba018b7c2c1208754cd2 |
|
21-Jun-2013 |
Eric Anholt <eric@anholt.net> |
i965: Move the remaining intel code to the i965 directory.
Now that i915's forked off, they don't need to live in a shared directory.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Adam Jackson <ajax@redhat.com>
(and I hear second hand that idr is OK with it, too)
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| bea6b5fe5aa3138cec8d057766ae48da4aa57dee |
|
20-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Enable EXT_framebuffer_object.
To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 2c9e515d8607fb91f08c500a841cdf7f32bda346 |
|
17-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace our own depth constants in intel context with GL context ones.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| c1d6b874b35dd353b2f9862b47aadb52a812a4aa |
|
17-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Cleanup of */intel_blit.c to bring the two closer.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 27674c41352dc78ad79f67cebca16d7896cd2093 |
|
20-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 3177b4e2cf7d2fff7428cb6057bebbe60ff5cc6c |
|
30-Oct-2007 |
Michel Dänzer <michel@tungstengraphics.com> |
More vblank cleanups.
* Fix crash at context creation in most drivers supporting vblank.
* Don't pass vblank sequence or flags to functions that get passed the drawable
private already.
* Attempt to initialize vblank related drawable private fields just once
per drawable. May need more work in some drivers.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 38fdb47d26055e19d50cd407266b56ed4317ae0a |
|
29-Oct-2007 |
Jesse Barnes <jesse.barnes@intel.com> |
Refactor and fix core vblank support
Consolidate support for synchronizing to and retrieving vblank counters. Also
fix the core vblank code to return monotonic MSC counters, which are required
by some GLX extensions. Adding support for multiple pipes to a low level
driver is fairly easy, the Intel 965 driver provides simple example code (see
intel_buffers.c:intelWindowMoved()).
The new code bumps the media stream counter extension version to 2 and adds a
new getDrawableMSC callback. This callback takes a drawablePrivate pointer,
which is used to calculate the MSC value seen by clients based on the actual
vblank counter(s) returned from the kernel. The new drawable private fields
are as follows:
- vblSeq - used for tracking vblank counts for buffer swapping
- vblFlags - flags (e.g. current pipe), updated by low level driver
- msc_base - MSC counter from the last time the current pipe changed
- vblank_base - kernel DRM vblank counter from the last time the pipe changed
Using the above variables, the core vblank code (in vblank.c) can calculate a
monotonic MSC value. The low level DRI drivers are responsible for updating
the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags)
along with msc_base and vblank_base whenever the pipe associated with a given
drawable changes (again, see intelWindowMoved for an example of this).
Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to
driDrawableGetMSC32 and add code for pipe switching as outlined above to fully
support the new scheme.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 77e0523fb7769df4bf43747e136b1653b2421b97 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 0fc9efd8f0b1b6c4e3525a50e3478e5aef72531a |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
Replace bmBufferOffset usage in batchbuffer setup with OUT_RELOC.
This is in preparation for 965 TTM.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 6bac9478c39fbe7955d10a21a2d7743697427a56 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
Replace duplicated intel_reg.h with a shared header.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 1f7378ee465eba8d82d224a7bf835e38c5ab6ee2 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
Replace some structure-based batch preparation with plain OUT_BATCH.
OUT_BATCH is far more amenable to the upcoming relocations being done for TTM
support.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| e886ae4c58bc98897d6901e3f30deea008bc7f8a |
|
28-Sep-2007 |
Eric Anholt <eric@anholt.net> |
Revert "WIP 965 conversion to dri_bufmgr."
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e.
Somehow I ended up with my branch's save-this-while-I-work-on-master commit
actually on master.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| b2f1aa2389473ed09170713301b042661d70a48e |
|
27-Sep-2007 |
Eric Anholt <eric@anholt.net> |
WIP 965 conversion to dri_bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| bd9db5eed2cca6cd394c88adf09c70204be9da33 |
|
04-Jul-2007 |
Eric Anholt <eric@anholt.net> |
fix LogicOp/bitmap problem, bug 11133
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| ef02f8be10a9f95788fee48bb9e7801dea0c2ba6 |
|
13-Dec-2006 |
Zou Nan hai <nanhai.zou@intel.com> |
i965: xdemos/glxthreads get: Assertion `block->fenced' failed (9201)
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 46c04525d2282fc7fb5632de8348fef379c71120 |
|
21-Nov-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Gary Wong's patches for CopyPixels Logiop (enable) and Blend
(disallow). Slightly cleaned to disallow on all blend states for code
consiseness and turn a table lookup into a function to match other
code in the driver.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| a5676795cfe2e24979b5da65c2f499049ab009d9 |
|
01-Nov-2006 |
Brian Paul <brian.paul@tungstengraphics.com> |
Remove x/y/width/height parameters from Clear functions.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 68da677ae29c0c38ca1bce1ce78087b9c7cf0e1a |
|
05-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Accelerate glBitmap with a color expand blit. Nice speedup for demos
like 'fire' that display a help message or fps number this way.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 9c5d75e592edd15b737294853fc247b66d74619e |
|
22-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Explicit test for +ve pitches in intelEmitCopyBlit()
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 4f17378ec32844a483c45252ebd76fa892b8aca7 |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Add a comment about the interactions of negative pitches, overlapping
blits and the different ways of specifying a blit on this hardware.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 3a5319293c9210ea3c0c9d84604fa0720a96f0e8 |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Broadwater seems to prefer this style of blitting.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/intel_blit.c
|