| 36fb1cec5777b87c8c6236dc1cdb9941abc58ead |
|
06-Oct-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix vld, vst instructions with post-index.
Change-Id: I23298cb948eb73e4a98c7b3e24fd0717214be8ee
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| f9d8c6e6eacb90fa4284a0d3fc784ad2bc4874af |
|
12-Sep-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Check unpredictable (OutsideITBlock()) for crc, hvc.
Change-Id: I1d61eac5e2db61b9e89e88438089d1c6ba672c84
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| f9a3bc17461518bd96d7afff61fb4cb5e3d48964 |
|
12-Sep-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Check unpredictable for vldm, vstm.
Change-Id: I7fedb713b3280e33c5da7448be9f146d51123231
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 8ecc789f1bdda97c006ce4e8e075b9ca1c964dfb |
|
08-Sep-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Check unpredictable conditions for vstr.
/r/4070/
Change-Id: I39981e2009e09ae53dd9302300b3772ebdb09ee1
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 71fb5916778754132c6f0872134731ef996e80dc |
|
16-Aug-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix tests for indexed register.
Change-Id: I5b3923328169d945766643d0f5e8a6bf99a118ff
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 1bce007699e07bd855b7d194ca93fa5504a73eda |
|
06-Jun-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Use clang-format 3.8 to format VIXL
Additionally, this version of clang-format orders include directives
alphabetically which showed that the "non-const-visitor.h" header was missing
two of them.
Change-Id: Ib03407dd2046a0bb7175370685e09fb3aebe583f
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| ac2854411c51a724d1c9866abfa6ea9c94998116 |
|
16-May-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Factorize reference info.
Change-Id: Iaf796e0f2e4fd6af4654f855ea5695cdbb14d5d3
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 8b57c86886020cf0a5331823be4789ee558764e2 |
|
02-Mar-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
[pool-manager] Integration with aarch32.
Key points of this patch:
- renames LabelBase to LocationBase
- makes the Location class derive from LoctionBase
- moves the code for Location, Label and RawLiteral/Literal to a shared file
- moves ReferenceInfo out of Assembler
- removes all the old veneer pool and literal pool code
- updates the macro assembler to use the new pool manager
- updates existing tests that expect a certain behaviour from the pool manager
- adds new tests for corner cases that came up during integration
- adds tests for issues that the new pool manager addresses (literal_and_veneer_interaction_*)
Change-Id: Ied81401d40f88cb988ff95e85fe832851f171f77
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| c9a1da70cea8c4f28bac34bad9f195c27f095bfa |
|
24-May-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix adr A1 info.
Change-Id: I03ad5f9b818650c3fc4965da9f120a4244e7a23a
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 275c9d477d5bb717ac48f29db4ed153495be5ad3 |
|
12-May-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
[pool-manager] Split Label and Literal.
Add a new Location class that's a parent of both Label and Literal. Uses of
Label and Literal in the MacroAssembler stay as before, whereas in the
Assembler the new simple Location class is used.
Also changes the EmitOperator to store the ISA of the reference instruction (to
avoid storing this information in ForwardReference), and removes the minimum
and maximum offsets from EmitOperator, since that information is now stored in
ReferenceInfo. Addition of the architecture-specific PC-offset is now done in
the Encode method of the EmitOperator, where we don't need to check which
instruction set we are using (it's statically known).
These changes are in preparation of integration with the new pool manager, but
also clean up usage of labels and literals in some cases. For example, it won't
be possible to jump to a literal with the MacroAssembler anymore, as Literal
does not derive from Label.
Change-Id: I1139faaccfbd087e97ecbff2cfc2433a35582973
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 4b139a2dd8a7c32fc0f7df0cfd36d6c1336bc26c |
|
31-Mar-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
[pool-manager] Add helper functions to get info on forward references.
Change-Id: I0da221d37d8fa8b0188ace565be37a5f3dd6f3da
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 07f9e742691f10b7ff8b0107415eb94e157c2b33 |
|
21-Apr-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Use SOperand and DOperand for cmp and cmpe.
Change-Id: Ie5419a9f423c9dca7e21308ce3b35909500f2ca2
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 94ce7a99e8fad024fd8e17ada567eebe32431d64 |
|
20-Feb-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove redundant LR checks in the assembler
A32 instructions using "rt" and "rt2" as operands have redundant checks in the
assembler. In those cases "rt2" is defined to be "rt + 1" and we have the
following checks:
- rt != LR
- rt2 != PC
Let's remove the LR check. The affected instructions are:
- LDAEXD (A1)
- LDRD (A1)
- STLEXD (A1)
- STRD (A1)
- STREXD (A1)
Change-Id: I6da70dc2b15451e7b6250b354c61b40d3e328ba9
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| dc626f3eb17d2a790a672d2fde74c48929e854b6 |
|
15-Feb-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Add unpredictable checks when the instruction has to be last in IT block
Some instructions may only be used inside an IT block when there are the last
one, add checks for this in the assembler.
- BL
- BLX
- BX
- BXJ
- SUBS
Change-Id: I2c6e76580cb8b25900ab7b336910ddaa72bef66f
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 6bf388ddc1e1050141b7163df9d7e5ccde4959c8 |
|
15-Feb-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Add unpredictable checks mis-uses of PC in aliases
Add checks for mis-use of PC in the following alias instructions:
- ASR{S}
- LSL{S}
- LSR{S}
- ROR{S}
- RRX{S}
- POP
- PUSH
- SUB (alias ADR)
Change-Id: Ibfd8d1be6841e9e8a12ffd5cf015b6de6bc9eacd
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| fcd33733df701a39192f80c17eccc6b134ea0aa5 |
|
15-Feb-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Explicitely name the RS register
The assembler would always refer to RS as
"operand.GetShiftRegister()". Explicitely name this register rs instead of
assuming it is in an operand.
Change-Id: I637e444cae50fdedc53925885c245b316735b3cb
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 960d28b9155a4e2f50c8fc298b812255fc724300 |
|
15-Feb-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Add unpredictable checks for mis-use of PC
Add the following checks in the assembler:
- If PC is not allowed unconditionally:
if (!register.IsPC() || AllowUnpredictable()) {
// Emit
}
- If PC is not allowed inside an IT block unless it is the last instruction in
the block:
if ((!register.IsPC() || OutsideITBLockAndAlOrLast(cond)) ||
AllowUnpredictable()) {
// Emit
}
This patch does not include instructions which are aliases.
Change-Id: I3ebb90747eeb9562f9d98e7d20006da1cd856713
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 609821fcd0b88f46b514e1938c420bde12284267 |
|
08-Feb-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Use an integer instead of an operand for bfc, bfi, sbfx and ubfx width operand.
Change-Id: I5eb025f01b4d92eded9a393b6364c38de27c6fe5
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| fc61fb69b2dea19053c0ae6694ee4e424a0d0245 |
|
12-Jan-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Clean up the Label class.
This adds a separate Label class to be used by the Disassembler, which needs
fewer fields than the Assembler, and removes the pc_offset and minus_zero
fields from the Label class used by the Assembler. If the user wants a minus
zero offset in an instruction that supports it, they can achieve that by using
a MemOperand with PC as the base.
Change-Id: I891b03cef5027acf7d3d5e42e5446663d80a92a1
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 9a9331faeba996d6c85e6e2a6355ccfc22c6cab6 |
|
09-Dec-2016 |
Rodolph Perfetta <rodolph.perfetta@arm.com> |
Allow conditional inclusion of A32, T32 and A64.
The 'target_arch' option has been replace by 'target' which can be any
combination of aarch32, aarch64, a32, t32, a64.
Change-Id: Id5cd052276747cd718551f562b74f79443b91869
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| e99f34dd95e54fb15605a022309175ed8020bf2c |
|
21-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Check for unpredictable CLZ.
Change-Id: I2f8799efc32bd2aae3c3d9c604d389511eab8987
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 942e3b7b1d381454c8f17c31c8a3ccbe568512f7 |
|
30-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add unpredictable conditions for mov.
Change-Id: I193cc0ec2ba3882805496f6d2efb6a73161f98a6
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| b323da089731b39a34ad0a77d20f0a96c1c1a1bc |
|
02-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Ensure that all used labels are bound.
Change-Id: I95c1a9c2d91c91303ac10898ca556e6e798403e5
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| d17e348e16bf0d6eca4f9ea0e935c7544098d045 |
|
23-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add unpredictable conditions for ADC_i, ADC_r, ADC_rr, ADD_ADR, ADD_i, ADD_r, ADD_rr, ADD_SP_i, ADD_SP_r, ADR and MOV_i.
Change-Id: I2d0255c352881d855b375db65794ee7f282b1cfe
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 989663e3cb7be8ac458d71f8e8d99afd29b13a39 |
|
24-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Rename operand-aarch32.{h,cc} to operands-aarch32.{h,cc}
We were inconsistent in naming this file between the AArch64 and AArch32
targets, let's go with what AArch64 calls is and pluralize operand.
Change-Id: Id2581255e4aa398f2c6fa81e5abce1f4b9b8a364
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 39b5e60b78f447c4af8c18f12281ed7ab9c33c82 |
|
18-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix assembler for instructions with an operand like [<Rn>, imm].
Change-Id: Iff2f0f8a6bd67886cb8b658b606514a9845796f7
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 9fcf6d6dd240d7f40f187965c981749eb4eaa94b |
|
17-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix assembler for instructions with an operand like "[PC, #imm]".
Change-Id: If6a945b9ef2ae08639efe1e85fef9e7d28340c25
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| c0ee83fd133e93d3967d8347ad2bf2a218524348 |
|
18-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Use IsOffset, IsPreIndex and IsPostIndex.
Change-Id: Ib7fd5e55689954c12ce90cf2bb605528a3ea057c
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 7827144797ee5ebfa0b574f45ad8ff235f919304 |
|
08-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow a label which is in the veneer pool to be bound with 'bind'.
Change-Id: I1e0d03498ec86ed23d94ef1db2d2adc5b73ef984
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 60241a544be0ebf48347789bf0ec268414364627 |
|
10-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Specify NOLINT disabled directives.
Remain:
src/aarch32/operand-aarch32.h:207: Operand(float) VIXL_NO_RETURN_IN_DEBUG_MODE { // NOLINT
src/aarch32/operand-aarch32.h:210: Operand(double) VIXL_NO_RETURN_IN_DEBUG_MODE { // NOLINT
which can't be specified due to a linter bug.
Change-Id: I5cf55e18772564363a9d895ef83481381ae96635
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| e42218c6ca969b7d4032da978fb05f06641df100 |
|
19-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Make bind and place more consistent.
Change-Id: I1743511e3c6f995f05cded38347a015c198b1fb9
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 3fac43c1a101f98f116e752b80abc122d32b83ac |
|
31-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Mark methods as `override` when compiling with C++11
This patch introduces a VIXL_OVERRIDE macro. When building with gcc
-std=c++11, we now enable the `-Wsuggest-override` warning so that we do
not forget to add them in the future.
Change-Id: I0f402599019ba9de1a7a654e9499f00a07f00201
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 120cafb9da939e107413e7158897ad73b83d55bf |
|
30-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly assemble VCLE and VCLT
VCLE and VCLT are aliases for VCGE and VCGT, however the source operands
have to be commuted. The assembler did not do this.
Change-Id: Icfa437ed417d9e234510fcab6034aa983d53e744
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 8ee2cef99dc4fae4129430834d2778d97cb5e076 |
|
12-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Revert "Correctly assemble VCLE and VCLT"
This reverts commit 702351b9ba0640958e17eed2ee041278294899b1.
Change-Id: Ic625aeecd276ebd582afd60005f8b1b2eea65f55
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 702351b9ba0640958e17eed2ee041278294899b1 |
|
30-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly assemble VCLE and VCLT
VCLE and VCLT are aliases for VCGE and VCGT, however the source operands
have to be commuted. The assembler did not do this.
Change-Id: Ia660ddce3c7a8aeaaf636b393b1df2b710d37c63
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 8885c17bce593f82cf90c086da242e52943c50ef |
|
24-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
forbid direct use of assembler from the macro-assembler
Change-Id: Ic00c9c72e9aed7efaab72a6fd6838bbd0bda6531
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 78973f258039f6e96eba85f1b5ecdb14b3c51dbb |
|
10-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly include C headers
This patch refactors VIXL to use `extern` block when including C header
that do not have a C++ counterpart.
Change-Id: I203d7d107755dbac3e5f4cf8d2f196f70dea1e07
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| 10dae1a549308bddc1931f29754d6a4459f70c9b |
|
27-Jul-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Improve the API for selecting the ISA.
Specifically, replace SetT32(false) with SetA32(), and SetT32(true) with
SetT32(). This also adds a parameterised SetInstructionSet(...) helper, and
allows the instruction set to be set in the constructors.
Change-Id: I82609823a4b2af908b38c0a4240ff239561f7507
/external/vixl/src/aarch32/assembler-aarch32.cc
|
| d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c |
|
04-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Update naming to `aarch32` and `aarch64`.
Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
/external/vixl/src/aarch32/assembler-aarch32.cc
|