| 9e52d5becfa81b6b819cdc0350693c3ad6b95b1d |
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01-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Fix logic-aarch64 to satisfy UBSan
Most changes are fixing shifts of signed integers, or out of range shifts.
Change-Id: I1a747dbd4cedda67857cf49a11e51f636e60751f
/external/vixl/src/aarch64/logic-aarch64.cc
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| 1e1277e629b68c96a1d7b953c2c6f90c7a44cdb7 |
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31-Oct-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Use AreConsecutive in NEON table instructions
AreConsecutive's intentions are more clear.
Also, remove a line of stray debug code from an earlier patch.
Change-Id: I85be135354cf50602d7b6e0e43b14f01a7cb1374
/external/vixl/src/aarch64/logic-aarch64.cc
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| b953ea8255b36e27834f17941429cd17af12f6f2 |
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20-Oct-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Fix simulation of NEON min/maxp and tbl
The simulation of [su](min|max)p, tbl and tbx was broken when source and
destination registers aliased. Fix these and add regression tests.
Change-Id: I3945e520df7a1f9453595c9941bdfbb3447ae581
/external/vixl/src/aarch64/logic-aarch64.cc
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| 491a575777fe21edc15bedd877a288a7f042bf48 |
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18-Oct-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Fix NEON 'across' instruction simulation
The simulation of NEON instructions that operate across a vector, eg. uminv,
was incorrectly clearing its destination register, which was a problem when
source and destination registers aliased.
Fix the simulation and improve the tests to check instances of aliased
registers.
Change-Id: I65717c472e5bfc85258952002b571597d554270d
/external/vixl/src/aarch64/logic-aarch64.cc
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| b49bdb7996e603555eba4c8b56c7325e3e737ab6 |
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26-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Improve include directives in `src/aarch64`.
Some `aarch64` files had include directives such as:
#include "globals-vixl.h"
#include "aarch64/other-aarch64.h"
This required users of VIXL to compile with `-I<path/to/vixl/src>`.
Change-Id: Ie0d1d39d1d8eb4a0e6b4b96af95a352b16043003
/external/vixl/src/aarch64/logic-aarch64.cc
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| 1e85b7f2e8ad2bfb233de29405aade635ed207ce |
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05-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce architecture specific guards for the simulator
This patch makes the VIXL_INCLUDE_SIMULATOR and
VIXL_GENERATE_SIMULATOR_CODE header guards specific to either AArch64 or
AArch32. Even though the simulator only support AArch64. The build
system was updated accordingly, the "simulator" variable now takes
"aarch64" or "none" as possible values instead of "on" and "off".
This fixes issues we have when we want to build VIXL natively on
AArch64 without a simulator, but still include the AArch32
macro-assembler. The later would check for VIXL_GENERATE_SIMULATOR_CODE
and then generate calls to native code, which breaks.
Change-Id: I2850782558d4cc37f37c1644f0efbd70a3123057
/external/vixl/src/aarch64/logic-aarch64.cc
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| 868bfc49d722d6a233390ec847fa1407820a1eab |
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19-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch64: Add more Simulator read/write helpers working with `GenericOperand`.
Change-Id: I4950e9895a7ba458581c7265ca0b08b59048455f
/external/vixl/src/aarch64/logic-aarch64.cc
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| d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c |
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04-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Update naming to `aarch32` and `aarch64`.
Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
/external/vixl/src/aarch64/logic-aarch64.cc
|