| 5d1d9ee085e6f297b4b74a26719dcf8700a125a4 |
|
03-Oct-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Disable forward reference info negative tests in release mode.
The forward reference tests require ExactAssemblyScope checks that
are debug-only.
Change-Id: I2847456e5f0cc68636786d0cb7a54e416fbff0c5
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 1bce007699e07bd855b7d194ca93fa5504a73eda |
|
06-Jun-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Use clang-format 3.8 to format VIXL
Additionally, this version of clang-format orders include directives
alphabetically which showed that the "non-const-visitor.h" header was missing
two of them.
Change-Id: Ib03407dd2046a0bb7175370685e09fb3aebe583f
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 8b57c86886020cf0a5331823be4789ee558764e2 |
|
02-Mar-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
[pool-manager] Integration with aarch32.
Key points of this patch:
- renames LabelBase to LocationBase
- makes the Location class derive from LoctionBase
- moves the code for Location, Label and RawLiteral/Literal to a shared file
- moves ReferenceInfo out of Assembler
- removes all the old veneer pool and literal pool code
- updates the macro assembler to use the new pool manager
- updates existing tests that expect a certain behaviour from the pool manager
- adds new tests for corner cases that came up during integration
- adds tests for issues that the new pool manager addresses (literal_and_veneer_interaction_*)
Change-Id: Ied81401d40f88cb988ff95e85fe832851f171f77
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| c9a1da70cea8c4f28bac34bad9f195c27f095bfa |
|
24-May-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix adr A1 info.
Change-Id: I03ad5f9b818650c3fc4965da9f120a4244e7a23a
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| a6090f84eb54fab650f7ac4acc45e8a895eaf598 |
|
01-Feb-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
[pool-manager] Separating pool checkpoint and buffer checkpoint.
The new pool manager does not expose the pool checkpoint anymore, so split the
buffer size check from the pool emission check.
Change-Id: Id9e04a855017b873d607848310d2854ff0401713
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 606582c29b827e78b814c728f3c39a5e56c12833 |
|
12-May-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Remove Label versions of PLD and PLI from the MacroAssembler.
These are unsafe to use, as we do not guarantee that the labels they refer to
will be in range. Users can use the assembler version, or the MemOperand
version instead.
Change-Id: Ied575009f11514bbbca59a64f88e78cdc442fc73
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 4b139a2dd8a7c32fc0f7df0cfd36d6c1336bc26c |
|
31-Mar-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
[pool-manager] Add helper functions to get info on forward references.
Change-Id: I0da221d37d8fa8b0188ace565be37a5f3dd6f3da
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 35afe7ee222b8cf95c870f9f443491303a941e58 |
|
09-May-2017 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Clear floating-point flags in SETUP.
Some tests assume that the flags are cleared before running them. For example,
vcmp tests assume that all the flags that are not affected by the vcmp
instruction will be zero, which might not be the case if an inexact conversion
has happened, for instance. Clearing the flags makes the tests work reliably.
Change-Id: I02b2f367db5ce8219a0028d99db59766f0355e46
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 74d4ef31746fbfd90118858857502c7006e3e925 |
|
08-May-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
[test] Remove TEARDOWN macro for AArch32
This macro was never necessary, remove it.
Change-Id: Ie7428a80eb55505d36235467ea40ebdca72037ad
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 6c266808812883d690cb944c2763d22c50d116a6 |
|
05-May-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Fix array-bounds warning when compiling with GCC 6
The following code triggers a warning with newer GCC:
~~~
const uint32_t data[] = {0, 1, 2, 3};
uintptr_t ptr = reinterpret_cast<uintptr_t>(data - 1);
~~~
We safely did this in a test, and this test was only enabled for 32-bit
hosts. Fix this by decrementing after the cast.
Change-Id: Ic365598d59d75f86c761e8319aead0ffe2219336
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 3fab627d900c0bc5056c07df260e14f6eb155584 |
|
04-May-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
[test] Fix wrong result in VCMP tests
The VCMP tests were expecting the comparison to yield "smaller than" when the
result is actually "greater than".
Change-Id: Id3f31479f0bc69dd77eaf8aabee89f318cdc2856
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 07f9e742691f10b7ff8b0107415eb94e157c2b33 |
|
21-Apr-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Use SOperand and DOperand for cmp and cmpe.
Change-Id: Ie5419a9f423c9dca7e21308ce3b35909500f2ca2
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| b815212d28120f65e1e808faadfc503e89a45990 |
|
05-Apr-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
[tests] Add missing START and TEARDOWN to veneer_bind
Change-Id: If16d5dbb778b23d44bcb8105926696b72c896e25
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 94a02bb2b5f7c85dc5a3852aac8c6692f9c6c446 |
|
24-Feb-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Add accidently removed tests
I accidently removed this file when regenerating test traces.
Change-Id: Ia7db9159e8c22bb436fdaff8f9ab89a1468c02f3
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| d1bf2784420717dcd20888a6eaecb18ab7f01d56 |
|
27-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
[tests] Allow generating one description to support two ISA
This patch changes the naming scheme of the generated tests, so we can
support generating both a A32 and T32 test for a single
description. This is a pre-requisite to tests NEON/VFP instructions, as
they very often have the same constraints in both ISAs.
The name of the ISA is now placed at the end of each tests. A
configuration file which does not specify an ISA will see its test files
duplicated for both.
Finally, the "rd-rn-rm-{a32,t32}.json" configurations where identical
apart from the ISA. This patch shares them.
Change-Id: Icd89112b94dd135b7519b6c65fade17fe3b8e217
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 8cb4e850c01607da237c7819265e1cfe6034861f |
|
08-Feb-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Add fuzz tests that mixes near branches and literals
Change-Id: Ic8cfacbc23cff3ccc49e3bfc1949b02ce4ef91e2
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 8571b89fb163d8f3551327ceb46deb1cda359cee |
|
09-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce a FinalizeOption to Finalize()
The last instruction we generate before calling `Finalize` should be an
unconditional branch. However, it is useful to break this constraint when
fuzzing.
We now have two options that we can pass to Finalize:
- kUnreachable: This is the default, with the existing behaviour.
- kFallThrough: You are allowed to generate more instructions after Finalize.
Change-Id: I3ecc873934a8448ab35646ecabd7085af3182637
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| bde2e4b5ce376456d50a972b6f3aaee3475f8786 |
|
24-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Enable clang-format in the tests
Extend the clang_format.py script to format everything by trace files in
the `test/` directory. Also, we have to add "on/off" marker in
`test-simualtor-inputs-aarch64.h` as clang-format is getting confused
there.
Change-Id: I1159498072bda1bfd049082aeccb347ec55e7825
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 5c01c410ae559d0a77d68a023957c5bc9de143e0 |
|
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Adr(Register, Label*) support from the MacroAssembler
The Adr macro-instruction taking a label should, in theory, be able to
handle a label bound anywhere in the 32-bit address space. However this
is not implemented therefore we shouldn't have it exposed in the
MacroAssembler as it can be misleading. One would naturally expect it to
generate the appropriate sequence for any label.
Let's enable this again later once it is entirely implemented.
Change-Id: I186b5f0ba1be4febb26ca548df2e1c056863e975
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 32929a7f73c3a103a2abe21f49258fba149a5157 |
|
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Switch implementation from VIXL
The Switch implementation is not well tested, and uses Adr with a label
which we are going to temporarily disallow until we support patching
multiple instructions. The reason this is tricky is that pools can be
generated in between each macro-instruction and this can break Adr,
which breaks Switch.
Let's add it again later when the feature is ready.
Change-Id: I30d6adf89e4ddcebada6aa70ff7b6a5dc9239ad4
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| d87b1134b5be7b7fb5518180efb3b20b37a7923b |
|
06-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Extend near branch fuzz test to include B(T2) and CBNZ
The B(T1) and B(T2) instructions are both near branches but have different
ranges. Additionnaly, the CBNZ instruction was not covered in the test. It is
not strictly necessary as CBNZ and CBZ are basically the same instruction, but
let's do it anyway.
Change-Id: I92411c1cd221bfcfc3fd7b07a3b5634c2819c1c4
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 9a9331faeba996d6c85e6e2a6355ccfc22c6cab6 |
|
09-Dec-2016 |
Rodolph Perfetta <rodolph.perfetta@arm.com> |
Allow conditional inclusion of A32, T32 and A64.
The 'target_arch' option has been replace by 'target' which can be any
combination of aarch32, aarch64, a32, t32, a64.
Change-Id: Id5cd052276747cd718551f562b74f79443b91869
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| a4cbc576a003da934ab58b293d9023d9b6f3077b |
|
05-Jan-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer emission.
Change-Id: I2ef8b153f1ab87fa9972f80b1b4660ceefabceb4
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 139307eb64ef70e32e75b4de5ba95da58513e238 |
|
05-Jan-2017 |
Martyn Capewell <martyn.capewell@arm.com> |
Extend branch fuzzing to near branches
Add near (16-bit) branches to the existing Cbz fuzzing test, and increase the
number of iterations to provide similar coverage.
Change-Id: Ie6c3c0727c994eb0fd9a5600bc37c88b02baff24
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 2272afbda5f15c4bfb25c3c9bf95d960c9df39d6 |
|
04-Jan-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix for veneer pool when using near branches and cbz.
Change-Id: Ifc9cf13b07d6b5504f3fe4d4d45597cc05e069aa
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 14e3bf1f6fc699edbb5e3a031964cb659bc16f9d |
|
16-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Test code size after commutation.
The MacroAssembler should try to commute operands (where possible) to take
advantage of 16-bit encodings. Currently, it can't do that, but the tests in
this patch can be used to check the desired behaviour once it is implemented.
Change-Id: I2ff2c33147dd804454a425ff11a73925ef6096d9
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66 |
|
14-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Assert perfect nesting for UseScratchRegisterScope.
Since UseScratchRegisterScope now has a MacroAssembler pointer anyway, this
patch also removes available_ and availablefp_, and uses the MacroAssembler
directly.
Some negative tests would be useful but I'll add them separately.
Change-Id: Ia093c67a980044f8e1514cff81998fd9dbfaa44e
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| be9c4d02c96eaa6cdc9a9a5ae3cc65f57d54585c |
|
15-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Support conditional load literal for T32.
Change-Id: I2865cd2ef2e075c47d1d18838c97c04c9294177c
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| cf91ee6bcaabf00356516bbc2d478acbeb8bed9a |
|
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Make rewinding of load literal instructions less conservative.
Change-Id: I2f1b7dce445ceff1edb1f93608b693737be1bc51
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 50e45c514c11300c91b370c251235a9a77bdaf5f |
|
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
After rewinding a load, only add the label to the literal pool if it's not bound.
Change-Id: I5f0296582630cc8f81a72a304986b1c15acab02c
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 57544695f27605ae5a54bcfd2b6b508ea6b13387 |
|
09-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
[aarch32] Cleanup *_pool_in_delegate tests
The veneer_pool_in_delegate and literal_pool_in_delegate tests were written to
make sure that generating a pool from inside a MacroAssembler delegate was
working. However, we no longer allow this and block the pool before delegates
can be called. Instead, we generate pools before handling the instruction, if we
need to.
So cleanup and rename those test to avoid confusion. They now just test that a
macro-instruction does generate the pools first. Additionnaly, the veneer was
changed so the branches would be taken, to make sure the veneers are correct.
Change-Id: Idc60d8b874aa2602711f8329d34e3f48f4ae0bb0
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 4f002a865b625dc388e9175bfdda285812e17f2b |
|
14-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Increase max recursion limit for delegates.
The new case that needs a larger recursion limit is related to literal loads
with negative offsets (due to already bound labels). In some cases, the Ldrd
delegate (1) calls MemOperandComputationHelper which calls Add (2). The Add has
a negative immediate that cannot be encoded so calls Sub (3). This recurses in
the new code that handles add/sub with negative offsets (4), and after we
recurse we add a Mov and end up in that Delegate (5). This increases the limit
to 6 which works fine in this case.
Change-Id: I994dd46a201fb24afb377bd13c4e5dcd3cb29002
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 1edc01c4a153d6ced9c71543365edefe7030f9a7 |
|
13-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
A dedicated test file for UseScratchRegisterScope.
This mostly provides a framework which will be extended later, though one
new test is included.
Change-Id: I0835b67beac6bd42b9755234992ad2d8fdd6541d
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 4a30c5d68ebbc271d6d876d828ffa96db53d8d7c |
|
08-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add MacroAssembler B with hint.
Change-Id: Ic56a63c5af35c6d46b1a03a4b58165e991afc4d7
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 67b839b72b77d13cca5363b477facaee33f22bb9 |
|
09-Dec-2016 |
Jacob Bramley <Jacob.Bramley@arm.com> |
Add a fuzzing test for Cbz, Bind etc.
Change-Id: I9baa064f62fc4961e4ba5e7cddaad29baeee0012
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| e31fda5ecc961cdb78a0a5311d692ae4b15e5933 |
|
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Correct number of bytes we check we can emit in ITScope.
This value was out of sync with MacroEmissionCheckScope, and we are
always using an ITScope together with a MacroEmissionCheckScope, so
we could potentially trigger an assertion that was not necessary.
Change-Id: I1e942d6b919070a3a41d4b38edde74feebb7cc19
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 18908fb3bb1d433e9c48c715ab95e164839eb390 |
|
12-Dec-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Add some basic test for blx.
We currently don't test ARM/Thumb interactions.
Change-Id: Ic80eb6a758a4c622055ae36384cfbb8671f45777
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| c6d19d5facc0bb99296067ef4a6ca55f83bf4788 |
|
09-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add veneer_and_literal6 test.
Change-Id: I383368ad59fbdcb43d7cd99008cab00ee13d793d
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 89d2f7702f0dc1751574bd5f9d35b5182fc65fac |
|
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix very-long-range literal loads.
The code was basically functional but the CodeBufferCheckScope sizes had to be
increased. The generated code could be improved, but its a corner case anyway so
it's not a priority for now. Here's an example:
0x004223f2 f2af31ec adr r1, 0x00422008
0x004223f6 f44f5c00 mov ip, #8192
0x004223fa f2c00c42 movt ip, #66
0x004223fe eba1010c sub r1, ip
0x00422402 6809 ldr r1, [r1]
This sequence occurs for offset ranges over about 1MB. For ranges below 1MB, the
worst case is still adr+sub+ldr.
Change-Id: I6345127aed12abb59c819f63167170d57160da0b
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 52e987eb677af65859f169b20816fa5d293c6cf0 |
|
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix long-range literal loads.
This is the second attempt. We no longer generate unpredictable instructions. As
before, this has only been tested for T32.
Change-Id: If5519fe603281b081e93a25bb7980c3e965f037b
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| e44090587ff7104b4ad3f786e64940c82838387c |
|
09-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove tab character in AArch32 tests
Change-Id: If191110332c78c1bb92b0e923053e197a7f75e9e
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| f86422e92dcbcd2e0a15b26e47c855c29c0132d5 |
|
09-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Fix AArch32 veneer_and_literal{3,4} tests natively
Those tests did not pass natively. We would check that r0 and r1 are loaded with
a literal but we were generating a branch over the entire test.
Change-Id: Iaefef093f092f8be116e3c891106afd1dd7156db
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 3e1f5530fae1bf65c565f5dc757bd58913ffd2a2 |
|
29-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Test 16-bit branch over literal to unaligned PC.
Change-Id: If0333dfafdb56f5f36379ebc3cdd95b72b936f7e
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| cb6592f4b00347a84f9d7638473f0af8f1b6b1dd |
|
08-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Close the UseScratchRegisterScope in the right place.
Change-Id: I97b37a24730e3d8f5b771712e7b5a780f481ead4
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| ead6404d95d7736deeed9ded7595804ea211dc36 |
|
08-Dec-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Add some tests for ldm/stm.
Change-Id: Ib99be3ce7534adccf406aab0c77ea59287b973eb
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 4cb13e841305b38acbd8195b1c511d59c91ec8d9 |
|
08-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Correct usage of scratch registers in tests.
Exclude all registers from the UseScratchRegister list for start and end code
in tests, then include ip where necessary. Similarly, exclude all registers
from the scratch register list in the Printf implementation, which handles
available registers in its own way.
Change-Id: I96100411a45f104f85bbc4020959fc9d98e240af
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 6dce099abc8c1c4b3d052080c7f4e330915edb79 |
|
08-Dec-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Test for vmrs/vmsr instructions.
Change-Id: I8d94dfad4122e157a380734a5de93d63f9970eb6
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 1ddc52b438c2f07872e6e715c6b86e8d3b772795 |
|
08-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix MacroAssembler::GenerateInstruction.
Change-Id: Ibc942d3a8c3864f58a4f6d812864051b2d76bb59
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| bd087d8fe70f7db770f37569073b8b9f77a9c372 |
|
29-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix concurrent veneer and literal emission.
Change-Id: I83be782d9e2862cb94ab618440c375a66c1da201
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 15985a2fcc72ce0ec5e19c410b444ceec899c11f |
|
28-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer pool generation when several cbz/cbnz are generated one after the other and when several veneers have the same checkpoint.
Change-Id: Ic2d7f348854666f07c191aadc43f299b422867c5
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 27f1339a9fbbe5cb2df532557fd14c499d05a237 |
|
08-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Another build issue.
Change-Id: I0254c76f8bec44e12acddc66cef31a3930a4a418
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 832e97bf00eda271c2abbe3426618e9f8e60850e |
|
08-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Fix build issue.
Change-Id: Ida098be4edfa14e15f87dbba9c47aa8995ed0036
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 9c112d81bf7bc65d6bea5a1d889ef3db7609771d |
|
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix literal loads from unaligned instructions.
Change-Id: I07a1f7819328ef7ce1fb36ccdc0b940312e36afb
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| eb11988bb73246cfa10aa817915184cd1c893fb5 |
|
07-Dec-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Some basic tests for barrier and preload instructions.
Change-Id: If6435350ba99a1678f891f8a60002fdfcb3b2492
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| f8c2284645ce651f99ba410a512279102851076e |
|
29-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix Ldr for distant, bound literals.
Change-Id: I0ed3b1df4e93cbbc4bd5ce109130d1ce1ac35ef0
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 7027d2f28e155bb1dfc360b4c69c8f86320a6094 |
|
02-Dec-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Fix compilation after 2e7b9043baf27f8a4487403e24666203981ba57b
Change-Id: I78f58485717a68a1e6823b136baf77546336d06f
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 2e7b9043baf27f8a4487403e24666203981ba57b |
|
30-Nov-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Add test with custom literal placement at range limits.
Change-Id: Id17474b03fe9ba72f3f3a421c8d7c0c62dd080fc
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 1661f51a172e7c3dcce6caca55b6fe6d10ebd416 |
|
31-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Use the shared code generation scope `ExactAssemblyScope`.
This patch finishes the transition to shared code generation scopes
for the AArch32 backend.
Change-Id: Iccbdb5de48b41803408410a01307afabe30a7fee
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 8d191abf32edf41421f68f35585e4fce8da4d50c |
|
29-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Use the shared scopes `CodeBufferCheckScope` and `EmissionCheckScope`.
This patch continues toward the goal of unifying code-generation scopes for all
backends.
The new scopes differ from the existing AArch32 mechanisms, so a few tests for
literal and veneer pools needed to be updated.
The patch also adds AArch32 tests for the new scopes.
Change-Id: Ia6a93e6e860b47e703b6c9034fefa405810c18a0
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| ea90afd4d8e19b3b3f9c051f96c1d7ef98da5c5e |
|
28-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix two uses of TEST (to TEST_NOASM).
Change-Id: If6d4a85d84b90eea97683a3b4400729659abd221
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 7d0ad8b7de47bd31742317523a5d764cdd58a466 |
|
25-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Test switch without explicitly bound default label.
Change-Id: I98bb1913e114655abefb0678b92e456f80141112
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 2e5ad788a3a6c591d6c486d2a7c410926a165a58 |
|
24-Nov-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
Add more tests for custom literal placement on AArch32.
Change-Id: I4558ff1d97085faef91dcaf5b61628686fab8048
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| b21b7623a9fb6d4c627aec1e3a0b51f278ef0a72 |
|
24-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly exclude V registers in UseScratchRegisterScope
There was a nasty bug in UseScratchRegister::Exclude(VRegisterList). We were
taking the *core* register list as a source instead of the vfp register
list.
Add some tests for the Exclude/Include operations.
Change-Id: I8f58a8efa9d66927caf4d355e684b4a3b61b4da6
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 353025e7ae5ac51b476183a282121c8788b07ea9 |
|
24-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Remove left over debug code.
Change-Id: Ie7db6d062cdc6b62714dc857d620034d8825b88e
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| be370b630bc10bf728ed662594ca09d42e254192 |
|
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Improve tests related to pool emissions while in a delegate.
The main goal of the new version is to not be dependent on the behaviour of the
`MacroAssembler` regarding the margin it uses to generate literal and veneer
pool. So for example the new tests do not assume that
masm.Mov(r0, r1);
will only check whether pools are required in the next 2 bytes.
The tests themselves were validated by partially reverting:
commit dcffac4d0a5a586d3c14971e33bd28fc848bc148
Author: Vincent Belliard <vincent.belliard@arm.com>
Date: Wed Oct 19 11:31:20 2016 -0700
Fix veneer/pool emission while in a Delegate.
Change-Id: I76ff3e224f5e85a58a53865c62536d97e73b6730
and
commit e42218c6ca969b7d4032da978fb05f06641df100
Author: Vincent Belliard <vincent.belliard@arm.com>
Date: Wed Oct 19 13:24:28 2016 -0700
Make bind and place more consistent.
Change-Id: I1743511e3c6f995f05cded38347a015c198b1fb9
to restore the problematic behaviours.
Change-Id: Ibfde6bcfc8778ca375f2dd48e0216b35170318df
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 740da998f1b2677636dfd76a6028e283d6175bf0 |
|
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Correctly require space before the branch in `PerformEnsureEmitFor()`.
Change-Id: Ib3828be4e3cf762ebb13c8fc654067fdccff9eac
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 0eb25b040732354c6273c93df709f8d585a140de |
|
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Fix and test the precision of margins before pool emission.
This precision is paramount when writing tests for corner cases
of veneer or literal pools emission.
Also check that the buffer only grows when required.
Change-Id: I8992f1c389578a7a8301ea621ea6db7a7f9c9c11
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| a38f9aec7b79989b658790b2492e2de67a64b430 |
|
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Ensure `MacroAssembler::Nop` generates a single `nop`.
The `MacroAssembler` is allowed to emit any code that is functionally
equivalent to what is requested by the user, and is expected to
generate 'good' code. The user can expect calls such as
`masm.Add(r0, r0, 0)` to be optimized away (think that `0` may be the
value of a variable).
Following this we *could* generate no code for calls to `Nop()`. But
`Nop()` will likely not be used by mistake, so we ensure it generates
at least one `nop` instruction. This is useful for tests where we want
to generate 'some' code.
Change-Id: Iecf31b5cfd151a77b1633ea5158ff54fef9f8908
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| bfde9ad1b9ca9b857aca6b29aac9146a6572d256 |
|
11-Nov-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
Add more tests for load literal range for A32 and T32.
Change-Id: Ia5dbc31379eaea6ca05f1018e0291c9389ac544e
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 8a06e54e03258ff45aba33b1cafa412f8350b54a |
|
22-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Fix signed/unsigned comparison
VIXL failed to build on a 32-bit host due to a "-Wsign-compare" warning
in the tests.
Change-Id: If281c9a6d78cc077ef1084b10c9228fcdb1ce16b
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| c5beb5d4cf4c96c9a23bb8e37e3275728852e847 |
|
21-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Allow AArch32 tests that do not use the `isa` parameter.
Change-Id: I49c194e3137220660eb3749ef5c832c9f6a28ca3
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| dbc19e4a4f4117fdaa81265e6371178d2c107ac2 |
|
21-Nov-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Fix emit_literal test.
Make sure that the memory used to store the string literal is preserved while
we need it.
Change-Id: I6268393d2b3145aec9851ec77fde0f66cc59dddb
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 40b7e470e71b158158ef6ce8a1a3f701857ce0e2 |
|
09-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix PerformEnsureEmit for literals.
Change-Id: Iab0cb33eb59a69a90a00754263c7210b16ad2044
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| a01fbf25f9e2c9c53e82774126c4717ee37c1d91 |
|
18-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Add MacroAssembler tests for Msr.
Only handle immediates in the MacroAssembler: either for T32 which
does not have an immediate version of the instruction, or for A32
when the immediate cannot be encoded.
Change-Id: I8f83dce6a3548ebdebb19b8d677cc9ce59b3e56b
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| cf4d2842eb8d63c621d7003e240ec094a357cad0 |
|
15-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Check that the user doesn't pass in scratch registers.
The user must not use registers that the MacroAssembler can allocate as scratch
registers. This patch attempts to enforce this restriction by checking that the
user never passes an available scratch register to the MacroAssembler.
Change-Id: I7897b788df6dc0fabc452df0fe28d986fd84097c
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| e6c6319611916b73b227075c7a7c2f76bec50745 |
|
16-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Replace VRegisterList::Include with explicit variants.
Previously, it wasn't clear whether `list.Include(d0)` should have been true
when the list included s0 but not s1. Now, the user must call a specific variant
of Include to make this clear.
This patch also fixes the implementation of UseScratchRegisterScope accordingly,
and updates the test to check this behaviour. Further testing would be
beneficial here, but this patch is blocking other work.
Change-Id: I25499b8d3a292df217e3338e13d1817a7d125b45
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 7827144797ee5ebfa0b574f45ad8ff235f919304 |
|
08-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow a label which is in the veneer pool to be bound with 'bind'.
Change-Id: I1e0d03498ec86ed23d94ef1db2d2adc5b73ef984
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 2ec4cbaaa5d0c4d50fd207140886e4cbc2d37aa0 |
|
14-Nov-2016 |
Rodolph Perfetta <rodolph.perfetta@arm.com> |
[AArch32] run tests in both ISA.
Now will run the manual assembler tests using both ISA. Some tests need
fixing, this will be done in future patches.
Change-Id: Id5186d8c36780099a5eb5a37e0f53c189471f86f
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| f8833fa525b25cb1d72beb4f2d033d5ad9a3eb80 |
|
09-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow Cbz/Cbnz to branch immediately after the instruction.
Change-Id: I7ad6bbc84d69bc7ac3b61999fd77823b6ea552a2
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| dcffac4d0a5a586d3c14971e33bd28fc848bc148 |
|
19-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer/pool emission while in a Delegate.
Change-Id: I76ff3e224f5e85a58a53865c62536d97e73b6730
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 024aa58e9d83147f57a2509cf115b9fc9d260477 |
|
26-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Remove the implicit `aarch32::MemOperand` constructor.
Change-Id: Ieca14f0e4b411d059442842c81364836c503625d
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 25e3987b3b684df88edc8069d60b483b95587be5 |
|
20-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Support getting the address of a literal with ADR
This patch changes the printf implementation in the MacroAssembler to
use ADR instead of LDR to get the address of the format string. The
format string is placed directly in the code stream.
Additionally, Literal<const char*> was changed to simply
StringLiteral. It may be surprising to have a completely different
behaviour for this case.
Change-Id: I15c7acd457eb8ffed056a60cc438b9d7b54a94e1
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 6a049f97861bd71c69d81f643e42308d28c5de31 |
|
21-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Unify the `Assembler` helpers related to the code buffer.
A few helpers in `Assembler` classes that were simply wrappers around
`CodeBuffer` methods have been deprecated, and should be replaced by calls to
the `CodeBuffer` methods.
Change-Id: I72608c8c1f1f2823c58c8f6de042e932abe12629
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 919e3fe28a5024c53ede42922092bbc32e89dcb8 |
|
14-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Create a base class for assemblers.
This base class defines an interface that assemblers must adhere to.
For now, we use it to hold the code buffer.
Change-Id: I487430bb98c7044e57b348cffa1e74a2a4c8026f
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| bc01be684fe63a8a8c785f92e8aaa080cb6e87fa |
|
12-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce --disassemble option to test-runner
This patch adds a "--disassemble" option that one can pass to the
test-runner binary so that generated instructions will be printed to
standard output before executing.
Change-Id: Idb767a43d8f2bd8fdd4fa3718b973fb35204d0e0
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 0ec9dc10536b569b807274627e8c61bf6d6ceae7 |
|
05-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Rewrite `VIXL_CHECK` in terms of `abort`.
The `VIXL_CHECK` macro is meant to be used for runtime checks. However
VIXL is built, the check should always be done. We used `assert` to
implement `VIXL_CHECK`, but an assertion in C can be disabled with the
`NDEBUG` macro, which is also how Android builds VIXL.
This patch also replaces uses of asserts with `VIXL_CHECK`.
Change-Id: I576c5b4910c7dee66e37c3fd9f73ad4edca3f4b7
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| ace89ae8424261309696af6f71c37d09c55fdd84 |
|
22-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Fix literal_update test on AArch32
The AARCH32_ASM_literal_update test would fail, it turned out to be a
bug in the test itself, where register values where in the wrong
order. "LDRD" loads the low 32 bits in the first register, and the high
32 bits in the second, assuming we are little endian.
Change-Id: Ibc0c541f51f917b0fabe1018c13361d4d863e915
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 51d1cccb2cbb843c41a586fbedad00ded8f0d6a0 |
|
22-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
add load functions with manually placed literals
Change-Id: I60c554b2396c608ca371a427d718fe69892bfa26
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 8e7b9ae08bf958a99c4130ad15ec4aeedeee1cb2 |
|
27-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Fix logical_arithemtic_identities test
The AARCH32_ASM_logical_arithmetic_identities test was failing natively
on ARM. It turned out the tests was expecting the wrong result:
__ Orn(r4, r0, 0); <- puts 0xffffffff in r4
__ Orr(r5, r0, 0xffffffff); <- puts 0xffffffff in r5
Change-Id: I803b427b91b8f16144a51f294d58c0e2dbafcac0
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 31dd2ae90d5e82871667fbf3ee2697a155e7c3ac |
|
05-Jul-2016 |
Alex Gilday <Alexander.Gilday2@arm.com> |
Correctly allocate executable memory in CodeBuffer
CodeBuffer allocates memory that is executable via an ExecuteMemory
function.
Change-Id: Ib2dca824e9edd3144694cfac627becd35dd48e3c
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 628c5263f1ff96c793173770b85b93ebf8bf8d44 |
|
21-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Optimise a few logical and arithmetic identities.
The identities are used to avoid generating code or for strength reduction.
Change-Id: I8eecd23ced2b283884651a49e794c8f34bda1d29
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 1e85b7f2e8ad2bfb233de29405aade635ed207ce |
|
05-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce architecture specific guards for the simulator
This patch makes the VIXL_INCLUDE_SIMULATOR and
VIXL_GENERATE_SIMULATOR_CODE header guards specific to either AArch64 or
AArch32. Even though the simulator only support AArch64. The build
system was updated accordingly, the "simulator" variable now takes
"aarch64" or "none" as possible values instead of "on" and "off".
This fixes issues we have when we want to build VIXL natively on
AArch64 without a simulator, but still include the AArch32
macro-assembler. The later would check for VIXL_GENERATE_SIMULATOR_CODE
and then generate calls to native code, which breaks.
Change-Id: I2850782558d4cc37f37c1644f0efbd70a3123057
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 3e1b899f48c1328ac748b1f5fa78f417f7ec6581 |
|
14-Jul-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
AArch32: allow literals' update
Numerical literals can now be updated even after being emitted.
Change-Id: Ief50bac9079bb8c89c800c911ce6eb93a43ffd0e
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 78973f258039f6e96eba85f1b5ecdb14b3c51dbb |
|
10-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Correctly include C headers
This patch refactors VIXL to use `extern` block when including C header
that do not have a C++ counterpart.
Change-Id: I203d7d107755dbac3e5f4cf8d2f196f70dea1e07
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| 10dae1a549308bddc1931f29754d6a4459f70c9b |
|
27-Jul-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Improve the API for selecting the ISA.
Specifically, replace SetT32(false) with SetA32(), and SetT32(true) with
SetT32(). This also adds a parameterised SetInstructionSet(...) helper, and
allows the instruction set to be set in the constructors.
Change-Id: I82609823a4b2af908b38c0a4240ff239561f7507
/external/vixl/test/aarch32/test-assembler-aarch32.cc
|
| d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c |
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04-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Update naming to `aarch32` and `aarch64`.
Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
/external/vixl/test/aarch32/test-assembler-aarch32.cc
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