| d1bf2784420717dcd20888a6eaecb18ab7f01d56 |
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27-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
[tests] Allow generating one description to support two ISA
This patch changes the naming scheme of the generated tests, so we can
support generating both a A32 and T32 test for a single
description. This is a pre-requisite to tests NEON/VFP instructions, as
they very often have the same constraints in both ISAs.
The name of the ISA is now placed at the end of each tests. A
configuration file which does not specify an ISA will see its test files
duplicated for both.
Finally, the "rd-rn-rm-{a32,t32}.json" configurations where identical
apart from the ISA. This patch shares them.
Change-Id: Icd89112b94dd135b7519b6c65fade17fe3b8e217
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
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| 9a9331faeba996d6c85e6e2a6355ccfc22c6cab6 |
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09-Dec-2016 |
Rodolph Perfetta <rodolph.perfetta@arm.com> |
Allow conditional inclusion of A32, T32 and A64.
The 'target_arch' option has been replace by 'target' which can be any
combination of aarch32, aarch64, a32, t32, a64.
Change-Id: Id5cd052276747cd718551f562b74f79443b91869
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
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| 1661f51a172e7c3dcce6caca55b6fe6d10ebd416 |
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31-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Use the shared code generation scope `ExactAssemblyScope`.
This patch finishes the transition to shared code generation scopes
for the AArch32 backend.
Change-Id: Iccbdb5de48b41803408410a01307afabe30a7fee
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
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| 1d451fce2580f360ef249893135526156985a85c |
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04-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Isolate each generated tests into anonymous namespaces
Generated tests all have declarations and definitions with the sames
names, and in a C-like fashion we've used the `static` keywords to make
sure things are local to their compilation unit.
However, we cannot make a *type* local to its compilation unit in C, as
it doesn't make sense. But in C++, due to the template instantiation
phase, we need to be able to do that, as the compiler could create a
single template instantiation for a type that is defined differently in
different files. It can lead to very confusing bugs. This what the
anonymous namespaces are for, they make both funcions and type
definitions local to them.
So this patch drops the use of C-like `static` locality in favor of a
C++ anonymous namespace.
Change-Id: Ic1b74b0a589c250d9e7bb77d4c4864dababc4596
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
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| 919e3fe28a5024c53ede42922092bbc32e89dcb8 |
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14-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Create a base class for assemblers.
This base class defines an interface that assemblers must adhere to.
For now, we use it to hold the code buffer.
Change-Id: I487430bb98c7044e57b348cffa1e74a2a4c8026f
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
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| f5348cedd702124c90fc75e75d0195e2e485c620 |
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22-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove implicit 64 to 32 bit narrowing
This patch fixes cases of implicit 64 to 32 bit narrowing. The issue is
that `CodeBuffer` represents code offsets with `ptrdiff_t`, which will
be 64 bit on a 64 bit system. However, we want to support generating 32
bit code from a 64 bit program, therefore the 32 bit part of VIXL works
with `int32_t` for code offsets. We had implicit conversions happening
due to this.
We solve this by explicitely casting to `int32_t` in the AArch32
assembler when calling `GetCursorOffset`. If you are working with the
`CodeBuffer` directly, you are dealing with a code buffer on the host
and so will work with offsets as `ptrdiff_t`. But, when working with the
AArch32 assembler itself you will get offsets as `int32_t`. The
assembler is in charge of checking that the offsets it gets from the
code buffer fit into `int32_t`.
Additionally, we had narrowing cases when generally wrapping host
pointers into an Operand. This can only work if the pointer fits into 32
bits. This patch introduces a Operand::From() factory method that can be
used for converting any integral or pointer type to an immediate
operand.
Change-Id: Icc15711b34c2477ed997eef238e25496d86ea9aa
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
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| 5b0cbc8d721ff369c76e09ff1e7ab878ffcae4e9 |
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26-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Use assembler directly in generated assembler tests
A recent patch taught the MacroAssembler to optimize some instructions
before calling to the asssembler. These optimizations do not rely on
delegates. However, this introduced failures in our assembler tests
since we were relying on the MacroAssembler calling the Assembler
directly, for convevience in the test generator.
For example, the MacroAssembler does not generate any instructions when
one calls "Add(reg, reg, 0)" for example. But of course, the Assembler
should still generate an instruction and it should be tested that it
does. This means we cannot get away with using the MacroAssembler in
generated tests anymore.
This patch changes the test generator to have assembler tests call
assembler methods instead of macro-assembler methods. We still use a
MacroAssembler object, but generate the instruction under test using a
AssemblerAccurateScope. One major change in this patch is how we handle
generating IT instructions. Of course, we could previously rely on the
MacroAssembler to generate them, we now need to do it ourselves.
Finally, this patch also adds an assertion in generated assembler test
that actually fails the test! It seems I forgot to add it before and we
didn't see the regressions, sorry about that.
Change-Id: Ia904a8a11613cf33abe197858c8a8ce66e4e7add
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
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| 19c0535d3c9c0bec6eeecce0ae704a7fd527a9d8 |
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10-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
[test] Make generated tests satisfy VIXL's clang-format
The test generator would use Google's style guide instead of VIXL's when
running clang-format over the generated files. Now that VIXL has its own
".clang-format", let's use it.
Change-Id: I960ed290d1b7e762da9e96f105b83e749ed560a5
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
|
| 10dae1a549308bddc1931f29754d6a4459f70c9b |
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27-Jul-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Improve the API for selecting the ISA.
Specifically, replace SetT32(false) with SetA32(), and SetT32(true) with
SetT32(). This also adds a parameterised SetInstructionSet(...) helper, and
allows the instruction set to be set in the constructors.
Change-Id: I82609823a4b2af908b38c0a4240ff239561f7507
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
|
| 5e7413ae8e06eca1deeedda340d004d6f4bfb894 |
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25-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Update test files after changes to test configuration.
Change-Id: I8da54d5cb40686eea3d58fa1a1d2bac9b467604c
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
|
| d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c |
|
04-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Update naming to `aarch32` and `aarch64`.
Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
/external/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
|