Lines Matching refs:Address
37 Invalidates the instruction cache lines specified by Address and Length. If
38 Address is not aligned on a cache line boundary, then entire instruction
39 cache line containing Address is invalidated. If Address + Length is not
41 containing Address + Length -1 is invalidated. This function may choose to
44 lines are invalidated. Address is returned.
46 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
48 @param Address The base address of the instruction cache lines to
50 Address is a physical address. If the CPU is in a virtual
51 addressing mode, then Address is a virtual address.
55 @return Address.
61 IN VOID *Address,
66 return Address;
69 ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
70 return Address;
96 Writes back and invalidates the data cache lines specified by Address and
97 Length. If Address is not aligned on a cache line boundary, then entire data
98 cache line containing Address is written back and invalidated. If Address +
100 line containing Address + Length -1 is written back and invalidated. This
104 invalidated. Address is returned.
106 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
108 @param Address The base address of the data cache lines to write back and
110 Address is a physical address. If the CPU is in a virtual
111 addressing mode, then Address is a virtual address.
115 @return Address of cache invalidation.
121 IN VOID *Address,
132 return Address;
135 ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
144 return Address;
152 Start = (UINTN)Address;
162 return Address;
188 Writes back the data cache lines specified by Address and Length. If Address
190 containing Address is written back. If Address + Length is not aligned on a
191 cache line boundary, then the entire data cache line containing Address +
196 coherency domain of the calling CPU. Address is returned.
198 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
200 @param Address The base address of the data cache lines to write back. If
201 the CPU is in a physical addressing mode, then Address is a
203 mode, then Address is a virtual address.
206 @return Address of cache written in main memory.
212 IN VOID *Address,
216 return WriteBackInvalidateDataCacheRange (Address, Length);
243 Invalidates the data cache lines specified by Address and Length. If Address
245 containing Address is invalidated. If Address + Length is not aligned on a
246 cache line boundary, then the entire data cache line containing Address +
249 invalidated. Address is returned. This function must be used with care
255 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
257 @param Address The base address of the data cache lines to invalidate. If
258 the CPU is in a physical addressing mode, then Address is a
260 then Address is a virtual address.
263 @return Address.
269 IN VOID *Address,
277 return WriteBackInvalidateDataCacheRange (Address, Length);