1/** @file
2  Cache Maintenance Functions.
3
4  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
5  This program and the accompanying materials
6  are licensed and made available under the terms and conditions of the BSD License
7  which accompanies this distribution.  The full text of the license may be found at
8  http://opensource.org/licenses/bsd-license.php.
9
10  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13
14**/
15
16#include <Base.h>
17#include <Library/BaseLib.h>
18#include <Library/DebugLib.h>
19
20/**
21  Invalidates the entire instruction cache in cache coherency domain of the
22  calling CPU.
23
24**/
25VOID
26EFIAPI
27InvalidateInstructionCache (
28  VOID
29  )
30{
31}
32
33/**
34  Invalidates a range of instruction cache lines in the cache coherency domain
35  of the calling CPU.
36
37  Invalidates the instruction cache lines specified by Address and Length. If
38  Address is not aligned on a cache line boundary, then entire instruction
39  cache line containing Address is invalidated. If Address + Length is not
40  aligned on a cache line boundary, then the entire instruction cache line
41  containing Address + Length -1 is invalidated. This function may choose to
42  invalidate the entire instruction cache if that is more efficient than
43  invalidating the specified range. If Length is 0, then no instruction cache
44  lines are invalidated. Address is returned.
45
46  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
47
48  @param  Address The base address of the instruction cache lines to
49                  invalidate. If the CPU is in a physical addressing mode, then
50                  Address is a physical address. If the CPU is in a virtual
51                  addressing mode, then Address is a virtual address.
52
53  @param  Length  The number of bytes to invalidate from the instruction cache.
54
55  @return Address.
56
57**/
58VOID *
59EFIAPI
60InvalidateInstructionCacheRange (
61  IN      VOID                      *Address,
62  IN      UINTN                     Length
63  )
64{
65  if (Length == 0) {
66    return Address;
67  }
68
69  ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
70  return Address;
71}
72
73/**
74  Writes back and invalidates the entire data cache in cache coherency domain
75  of the calling CPU.
76
77  Writes back and invalidates the entire data cache in cache coherency domain
78  of the calling CPU. This function guarantees that all dirty cache lines are
79  written back to system memory, and also invalidates all the data cache lines
80  in the cache coherency domain of the calling CPU.
81
82**/
83VOID
84EFIAPI
85WriteBackInvalidateDataCache (
86  VOID
87  )
88{
89  AsmWbinvd ();
90}
91
92/**
93  Writes back and invalidates a range of data cache lines in the cache
94  coherency domain of the calling CPU.
95
96  Writes back and invalidates the data cache lines specified by Address and
97  Length. If Address is not aligned on a cache line boundary, then entire data
98  cache line containing Address is written back and invalidated. If Address +
99  Length is not aligned on a cache line boundary, then the entire data cache
100  line containing Address + Length -1 is written back and invalidated. This
101  function may choose to write back and invalidate the entire data cache if
102  that is more efficient than writing back and invalidating the specified
103  range. If Length is 0, then no data cache lines are written back and
104  invalidated. Address is returned.
105
106  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
107
108  @param  Address The base address of the data cache lines to write back and
109                  invalidate. If the CPU is in a physical addressing mode, then
110                  Address is a physical address. If the CPU is in a virtual
111                  addressing mode, then Address is a virtual address.
112  @param  Length  The number of bytes to write back and invalidate from the
113                  data cache.
114
115  @return Address of cache invalidation.
116
117**/
118VOID *
119EFIAPI
120WriteBackInvalidateDataCacheRange (
121  IN      VOID                      *Address,
122  IN      UINTN                     Length
123  )
124{
125  UINT32                            RegEbx;
126  UINT32                            RegEdx;
127  UINTN                             CacheLineSize;
128  UINTN                             Start;
129  UINTN                             End;
130
131  if (Length == 0) {
132    return Address;
133  }
134
135  ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
136
137  //
138  // If the CPU does not support CLFLUSH instruction,
139  // then promote flush range to flush entire cache.
140  //
141  AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);
142  if ((RegEdx & BIT19) == 0) {
143    AsmWbinvd ();
144    return Address;
145  }
146
147  //
148  // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H
149  //
150  CacheLineSize = (RegEbx & 0xff00) >> 5;
151
152  Start = (UINTN)Address;
153  //
154  // Calculate the cache line alignment
155  //
156  End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
157  Start &= ~((UINTN)CacheLineSize - 1);
158
159  do {
160    Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CacheLineSize;
161  } while (Start != End);
162  return Address;
163}
164
165/**
166  Writes back the entire data cache in cache coherency domain of the calling
167  CPU.
168
169  Writes back the entire data cache in cache coherency domain of the calling
170  CPU. This function guarantees that all dirty cache lines are written back to
171  system memory. This function may also invalidate all the data cache lines in
172  the cache coherency domain of the calling CPU.
173
174**/
175VOID
176EFIAPI
177WriteBackDataCache (
178  VOID
179  )
180{
181  WriteBackInvalidateDataCache ();
182}
183
184/**
185  Writes back a range of data cache lines in the cache coherency domain of the
186  calling CPU.
187
188  Writes back the data cache lines specified by Address and Length. If Address
189  is not aligned on a cache line boundary, then entire data cache line
190  containing Address is written back. If Address + Length is not aligned on a
191  cache line boundary, then the entire data cache line containing Address +
192  Length -1 is written back. This function may choose to write back the entire
193  data cache if that is more efficient than writing back the specified range.
194  If Length is 0, then no data cache lines are written back. This function may
195  also invalidate all the data cache lines in the specified range of the cache
196  coherency domain of the calling CPU. Address is returned.
197
198  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
199
200  @param  Address The base address of the data cache lines to write back. If
201                  the CPU is in a physical addressing mode, then Address is a
202                  physical address. If the CPU is in a virtual addressing
203                  mode, then Address is a virtual address.
204  @param  Length  The number of bytes to write back from the data cache.
205
206  @return Address of cache written in main memory.
207
208**/
209VOID *
210EFIAPI
211WriteBackDataCacheRange (
212  IN      VOID                      *Address,
213  IN      UINTN                     Length
214  )
215{
216  return WriteBackInvalidateDataCacheRange (Address, Length);
217}
218
219/**
220  Invalidates the entire data cache in cache coherency domain of the calling
221  CPU.
222
223  Invalidates the entire data cache in cache coherency domain of the calling
224  CPU. This function must be used with care because dirty cache lines are not
225  written back to system memory. It is typically used for cache diagnostics. If
226  the CPU does not support invalidation of the entire data cache, then a write
227  back and invalidate operation should be performed on the entire data cache.
228
229**/
230VOID
231EFIAPI
232InvalidateDataCache (
233  VOID
234  )
235{
236  AsmInvd ();
237}
238
239/**
240  Invalidates a range of data cache lines in the cache coherency domain of the
241  calling CPU.
242
243  Invalidates the data cache lines specified by Address and Length. If Address
244  is not aligned on a cache line boundary, then entire data cache line
245  containing Address is invalidated. If Address + Length is not aligned on a
246  cache line boundary, then the entire data cache line containing Address +
247  Length -1 is invalidated. This function must never invalidate any cache lines
248  outside the specified range. If Length is 0, then no data cache lines are
249  invalidated. Address is returned. This function must be used with care
250  because dirty cache lines are not written back to system memory. It is
251  typically used for cache diagnostics. If the CPU does not support
252  invalidation of a data cache range, then a write back and invalidate
253  operation should be performed on the data cache range.
254
255  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
256
257  @param  Address The base address of the data cache lines to invalidate. If
258                  the CPU is in a physical addressing mode, then Address is a
259                  physical address. If the CPU is in a virtual addressing mode,
260                  then Address is a virtual address.
261  @param  Length  The number of bytes to invalidate from the data cache.
262
263  @return Address.
264
265**/
266VOID *
267EFIAPI
268InvalidateDataCacheRange (
269  IN      VOID                      *Address,
270  IN      UINTN                     Length
271  )
272{
273  //
274  // Invalidation of a data cache range without writing back is not supported on
275  // x86 architecture, so write back and invalidate operation is performed.
276  //
277  return WriteBackInvalidateDataCacheRange (Address, Length);
278}
279