Lines Matching refs:UL
93 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
94 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
95 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
96 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
97 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
98 /* 1UL << 5 unused */
99 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */
100 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/
101 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */
102 #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */
103 #define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */
104 #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */
105 #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */
106 #define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */
107 #define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */
108 #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */
109 /* 1UL << 16 unused */
110 #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */
111 #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */
113 #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0)
114 #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1)
115 #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2)
125 #define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT)
126 #define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT)
127 #define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
128 #define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
129 #define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
130 #define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT)