1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2/*
3 *
4 * This file is provided under a dual BSD/GPLv2 license.  When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * Copyright(c) 2015 Intel Corporation.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
22 * Copyright(c) 2015 Intel Corporation.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 *  - Redistributions of source code must retain the above copyright
29 *    notice, this list of conditions and the following disclaimer.
30 *  - Redistributions in binary form must reproduce the above copyright
31 *    notice, this list of conditions and the following disclaimer in
32 *    the documentation and/or other materials provided with the
33 *    distribution.
34 *  - Neither the name of Intel Corporation nor the names of its
35 *    contributors may be used to endorse or promote products derived
36 *    from this software without specific prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 */
51
52/*
53 * This file contains defines, structures, etc. that are used
54 * to communicate between kernel and user code.
55 */
56
57#ifndef _LINUX__HFI1_USER_H
58#define _LINUX__HFI1_USER_H
59
60#include <linux/types.h>
61#include <rdma/rdma_user_ioctl.h>
62
63/*
64 * This version number is given to the driver by the user code during
65 * initialization in the spu_userversion field of hfi1_user_info, so
66 * the driver can check for compatibility with user code.
67 *
68 * The major version changes when data structures change in an incompatible
69 * way. The driver must be the same for initialization to succeed.
70 */
71#define HFI1_USER_SWMAJOR 6
72
73/*
74 * Minor version differences are always compatible
75 * a within a major version, however if user software is larger
76 * than driver software, some new features and/or structure fields
77 * may not be implemented; the user code must deal with this if it
78 * cares, or it must abort after initialization reports the difference.
79 */
80#define HFI1_USER_SWMINOR 3
81
82/*
83 * We will encode the major/minor inside a single 32bit version number.
84 */
85#define HFI1_SWMAJOR_SHIFT 16
86
87/*
88 * Set of HW and driver capability/feature bits.
89 * These bit values are used to configure enabled/disabled HW and
90 * driver features. The same set of bits are communicated to user
91 * space.
92 */
93#define HFI1_CAP_DMA_RTAIL        (1UL <<  0) /* Use DMA'ed RTail value */
94#define HFI1_CAP_SDMA             (1UL <<  1) /* Enable SDMA support */
95#define HFI1_CAP_SDMA_AHG         (1UL <<  2) /* Enable SDMA AHG support */
96#define HFI1_CAP_EXTENDED_PSN     (1UL <<  3) /* Enable Extended PSN support */
97#define HFI1_CAP_HDRSUPP          (1UL <<  4) /* Enable Header Suppression */
98/* 1UL << 5 unused */
99#define HFI1_CAP_USE_SDMA_HEAD    (1UL <<  6) /* DMA Hdr Q tail vs. use CSR */
100#define HFI1_CAP_MULTI_PKT_EGR    (1UL <<  7) /* Enable multi-packet Egr buffs*/
101#define HFI1_CAP_NODROP_RHQ_FULL  (1UL <<  8) /* Don't drop on Hdr Q full */
102#define HFI1_CAP_NODROP_EGR_FULL  (1UL <<  9) /* Don't drop on EGR buffs full */
103#define HFI1_CAP_TID_UNMAP        (1UL << 10) /* Disable Expected TID caching */
104#define HFI1_CAP_PRINT_UNIMPL     (1UL << 11) /* Show for unimplemented feats */
105#define HFI1_CAP_ALLOW_PERM_JKEY  (1UL << 12) /* Allow use of permissive JKEY */
106#define HFI1_CAP_NO_INTEGRITY     (1UL << 13) /* Enable ctxt integrity checks */
107#define HFI1_CAP_PKEY_CHECK       (1UL << 14) /* Enable ctxt PKey checking */
108#define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */
109/* 1UL << 16 unused */
110#define HFI1_CAP_SDMA_HEAD_CHECK  (1UL << 17) /* SDMA head checking */
111#define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */
112
113#define HFI1_RCVHDR_ENTSIZE_2    (1UL << 0)
114#define HFI1_RCVHDR_ENTSIZE_16   (1UL << 1)
115#define HFI1_RCVDHR_ENTSIZE_32   (1UL << 2)
116
117#define _HFI1_EVENT_FROZEN_BIT         0
118#define _HFI1_EVENT_LINKDOWN_BIT       1
119#define _HFI1_EVENT_LID_CHANGE_BIT     2
120#define _HFI1_EVENT_LMC_CHANGE_BIT     3
121#define _HFI1_EVENT_SL2VL_CHANGE_BIT   4
122#define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5
123#define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT
124
125#define HFI1_EVENT_FROZEN            (1UL << _HFI1_EVENT_FROZEN_BIT)
126#define HFI1_EVENT_LINKDOWN          (1UL << _HFI1_EVENT_LINKDOWN_BIT)
127#define HFI1_EVENT_LID_CHANGE        (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
128#define HFI1_EVENT_LMC_CHANGE        (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
129#define HFI1_EVENT_SL2VL_CHANGE      (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
130#define HFI1_EVENT_TID_MMU_NOTIFY    (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT)
131
132/*
133 * These are the status bits readable (in ASCII form, 64bit value)
134 * from the "status" sysfs file.  For binary compatibility, values
135 * must remain as is; removed states can be reused for different
136 * purposes.
137 */
138#define HFI1_STATUS_INITTED       0x1    /* basic initialization done */
139/* Chip has been found and initialized */
140#define HFI1_STATUS_CHIP_PRESENT 0x20
141/* IB link is at ACTIVE, usable for data traffic */
142#define HFI1_STATUS_IB_READY     0x40
143/* link is configured, LID, MTU, etc. have been set */
144#define HFI1_STATUS_IB_CONF      0x80
145/* A Fatal hardware error has occurred. */
146#define HFI1_STATUS_HWERROR     0x200
147
148/*
149 * Number of supported shared contexts.
150 * This is the maximum number of software contexts that can share
151 * a hardware send/receive context.
152 */
153#define HFI1_MAX_SHARED_CTXTS 8
154
155/*
156 * Poll types
157 */
158#define HFI1_POLL_TYPE_ANYRCV     0x0
159#define HFI1_POLL_TYPE_URGENT     0x1
160
161enum hfi1_sdma_comp_state {
162	FREE = 0,
163	QUEUED,
164	COMPLETE,
165	ERROR
166};
167
168/*
169 * SDMA completion ring entry
170 */
171struct hfi1_sdma_comp_entry {
172	__u32 status;
173	__u32 errcode;
174};
175
176/*
177 * Device status and notifications from driver to user-space.
178 */
179struct hfi1_status {
180	__u64 dev;      /* device/hw status bits */
181	__u64 port;     /* port state and status bits */
182	char freezemsg[0];
183};
184
185enum sdma_req_opcode {
186	EXPECTED = 0,
187	EAGER
188};
189
190#define HFI1_SDMA_REQ_VERSION_MASK 0xF
191#define HFI1_SDMA_REQ_VERSION_SHIFT 0x0
192#define HFI1_SDMA_REQ_OPCODE_MASK 0xF
193#define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4
194#define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF
195#define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8
196
197struct sdma_req_info {
198	/*
199	 * bits 0-3 - version (currently unused)
200	 * bits 4-7 - opcode (enum sdma_req_opcode)
201	 * bits 8-15 - io vector count
202	 */
203	__u16 ctrl;
204	/*
205	 * Number of fragments contained in this request.
206	 * User-space has already computed how many
207	 * fragment-sized packet the user buffer will be
208	 * split into.
209	 */
210	__u16 npkts;
211	/*
212	 * Size of each fragment the user buffer will be
213	 * split into.
214	 */
215	__u16 fragsize;
216	/*
217	 * Index of the slot in the SDMA completion ring
218	 * this request should be using. User-space is
219	 * in charge of managing its own ring.
220	 */
221	__u16 comp_idx;
222} __packed;
223
224/*
225 * SW KDETH header.
226 * swdata is SW defined portion.
227 */
228struct hfi1_kdeth_header {
229	__le32 ver_tid_offset;
230	__le16 jkey;
231	__le16 hcrc;
232	__le32 swdata[7];
233} __packed;
234
235/*
236 * Structure describing the headers that User space uses. The
237 * structure above is a subset of this one.
238 */
239struct hfi1_pkt_header {
240	__le16 pbc[4];
241	__be16 lrh[4];
242	__be32 bth[3];
243	struct hfi1_kdeth_header kdeth;
244} __packed;
245
246
247/*
248 * The list of usermode accessible registers.
249 */
250enum hfi1_ureg {
251	/* (RO)  DMA RcvHdr to be used next. */
252	ur_rcvhdrtail = 0,
253	/* (RW)  RcvHdr entry to be processed next by host. */
254	ur_rcvhdrhead = 1,
255	/* (RO)  Index of next Eager index to use. */
256	ur_rcvegrindextail = 2,
257	/* (RW)  Eager TID to be processed next */
258	ur_rcvegrindexhead = 3,
259	/* (RO)  Receive Eager Offset Tail */
260	ur_rcvegroffsettail = 4,
261	/* For internal use only; max register number. */
262	ur_maxreg,
263	/* (RW)  Receive TID flow table */
264	ur_rcvtidflowtable = 256
265};
266
267#endif /* _LINIUX__HFI1_USER_H */
268