Lines Matching refs:DReg
4219 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4222 if (DReg != ARM::NoRegister)
4223 return DReg;
4226 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4228 assert(DReg && "S-register with no D super-register?");
4229 return DReg;
4248 MachineInstr &MI, unsigned DReg,
4252 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
4258 ImplicitSReg = TRI->getSubReg(DReg,
4276 unsigned DstReg, SrcReg, DReg;
4318 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4325 .addReg(DReg, RegState::Undef)
4341 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4344 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4353 MIB.addReg(DReg, RegState::Define)
4354 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
4530 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4532 if (!DReg || !MI.definesRegister(DReg, TRI))
4552 unsigned DReg = Reg;
4556 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4557 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4560 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4561 assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4572 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
4574 MI.addRegisterKilled(DReg, TRI, true);