Cross Reference: /external/mesa3d/src/gallium/drivers/radeonsi/si_hw

Lines Matching refs:ctx
61 void si_need_cs_space(struct si_context *ctx)
63 	struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
64 	struct radeon_winsys_cs *ce_ib = ctx->ce_ib;
77 	if (unlikely(!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx.cs,
78 						   ctx->b.vram, ctx->b.gtt))) {
79 		ctx->b.gtt = 0;
80 		ctx->b.vram = 0;
81 		ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
84 	ctx->b.gtt = 0;
85 	ctx->b.vram = 0;
90 	if (!ctx->b.ws->cs_check_space(cs, 2048) ||
91 	    (ce_ib && !ctx->b.ws->cs_check_space(ce_ib, si_ce_needed_cs_space())))
92 		ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
98 	struct si_context *ctx = context;
99 	struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
100 	struct radeon_winsys *ws = ctx->b.ws;
102 	if (ctx->gfx_flush_in_progress)
105 	if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
108 	if (r600_check_device_reset(&ctx->b))
116 	if (radeon_emitted(ctx->b.dma.cs, 0)) {
118 		ctx->b.dma.flush(ctx, flags, NULL);
121 	ctx->gfx_flush_in_progress = true;
123 	r600_preflush_suspend_features(&ctx->b);
125 	ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
129 	if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
130 		ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
133 	si_emit_cache_flush(ctx);
135 	if (ctx->trace_buf)
136 		si_trace_emit(ctx);
138 	if (ctx->is_debug) {
140 		radeon_clear_saved_cs(&ctx->last_gfx);
141 		radeon_save_cs(ws, cs, &ctx->last_gfx);
142 		r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
143 		r600_resource_reference(&ctx->trace_buf, NULL);
147 	ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
149 		ws->fence_reference(fence, ctx->b.last_gfx_fence);
150 	ctx->b.num_gfx_cs_flushes++;
153 	if (ctx->screen->b.debug_flags & DBG_CHECK_VM) {
157 		ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
159 		si_check_vm_faults(&ctx->b, &ctx->last_gfx, RING_GFX);
162 	si_begin_new_cs(ctx);
163 	ctx->gfx_flush_in_progress = false;
166 void si_begin_new_cs(struct si_context *ctx)
168 	if (ctx->is_debug) {
172 		assert(!ctx->trace_buf);
173 		ctx->trace_buf = (struct r600_resource*)
174 				 pipe_buffer_create(ctx->b.b.screen, 0,
176 		if (ctx->trace_buf)
177 			pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b,
179 		ctx->trace_id = 0;
182 	if (ctx->trace_buf)
183 		si_trace_emit(ctx);
186 	if (ctx->b.chip_class >= CIK)
187 		ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
190 	ctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
195 	si_pm4_reset_emitted(ctx);
198 	si_pm4_emit(ctx, ctx->init_config);
199 	if (ctx->init_config_gs_rings)
200 		si_pm4_emit(ctx, ctx->init_config_gs_rings);
202 	if (ctx->ce_preamble_ib)
203 		si_ce_enable_loads(ctx->ce_preamble_ib);
204 	else if (ctx->ce_ib)
205 		si_ce_enable_loads(ctx->ce_ib);
207 	if (ctx->ce_preamble_ib)
208 		si_ce_reinitialize_all_descriptors(ctx);
210 	ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
211 	ctx->framebuffer.dirty_zsbuf = true;
212 	si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
214 	si_mark_atom_dirty(ctx, &ctx->clip_regs);
215 	si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
216 	ctx->msaa_sample_locs.nr_samples = 0;
217 	si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
218 	si_mark_atom_dirty(ctx, &ctx->msaa_config);
219 	si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
220 	si_mark_atom_dirty(ctx, &ctx->cb_render_state);
221 	si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
222 	si_mark_atom_dirty(ctx, &ctx->db_render_state);
223 	si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
224 	si_mark_atom_dirty(ctx, &ctx->spi_map);
225 	si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
226 	si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
227 	si_all_descriptors_begin_new_cs(ctx);
229 	ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
230 	ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
231 	ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
232 	si_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
233 	si_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
235 	r600_postflush_resume_features(&ctx->b);
237 	assert(!ctx->b.gfx.cs->prev_dw);
238 	ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
242 	si_invalidate_draw_sh_constants(ctx);
243 	ctx->last_index_size = -1;
244 	ctx->last_primitive_restart_en = -1;
245 	ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
246 	ctx->last_gs_out_prim = -1;
247 	ctx->last_prim = -1;
248 	ctx->last_multi_vgt_param = -1;
249 	ctx->last_rast_prim = -1;
250 	ctx->last_sc_line_stipple = ~0;
251 	ctx->last_vtx_reuse_depth = -1;
252 	ctx->emit_scratch_reloc = true;
253 	ctx->last_ls = NULL;
254 	ctx->last_tcs = NULL;
255 	ctx->last_tes_sh_base = -1;
256 	ctx->last_num_tcs_input_cp = -1;
258 	ctx->cs_shader_state.initialized = false;